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Merge pull request #5593 from jthacker/atmega_regs_common 

cpu/atmega_common: generalize register/peripheral definitions
pr/spi.typo
kYc0o 7 years ago committed by GitHub
parent
219bd8d6c7 2aec999900
commit
03d380845e
5 changed files with 74 additions and 48 deletions
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  1. 56
      cpu/atmega_common/include/atmega_regs_common.h
  2. 26
      cpu/atmega_common/periph/gpio.c
  3. 4
      cpu/atmega_common/periph/spi.c
  4. 2
      cpu/atmega_common/periph/timer.c
  5. 34
      cpu/atmega_common/thread_arch.c

56
cpu/atmega_common/include/atmega_regs_common.h
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@ -61,56 +61,60 @@ typedef struct {
} mega_uart_t;
/**
* @brief Base register address definitions
* @brief Timer register definitions and instances
* @{
*/
#if defined(TCCR1A)
#define MEGA_TIMER1_BASE (uint16_t *)(&TCCR1A)
#if defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1281__)
#define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A)
#define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A)
#define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A)
#define MEGA_TIMER1 ((mega_timer_t *)MEGA_TIMER1_BASE)
#endif
/** @} */
/**
* @brief Base register address definitions
* @{
*/
#define MEGA_UART0_BASE ((uint16_t *)(&UCSR0A))
#if defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1281__)
#define MEGA_UART1_BASE ((uint16_t *)(&UCSR1A))
#define MEGA_UART2_BASE ((uint16_t *)(&UCSR2A))
#define MEGA_UART3_BASE ((uint16_t *)(&UCSR3A))
#if defined(TCCR3A)
#define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A)
#define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE)
#endif
/** @} */
/**
* @brief Peripheral instances
* @{
*/
#define MEGA_TIMER1 ((mega_timer_t *)MEGA_TIMER1_BASE)
#if defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1281__)
#define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE)
#if defined(TCCR4A)
#define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A)
#define MEGA_TIMER4 ((mega_timer_t *)MEGA_TIMER4_BASE)
#endif
#if defined(TCCR5A)
#define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A)
#define MEGA_TIMER5 ((mega_timer_t *)MEGA_TIMER5_BASE)
#endif
/** @} */
/**
* @brief Peripheral instances
* @brief Peripheral register definitions and instances
* @{
*/
#if defined(UCSR0A)
#define MEGA_UART0_BASE ((uint16_t *)(&UCSR0A))
#define MEGA_UART0 ((mega_uart_t *)MEGA_UART0_BASE)
#if defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1281__)
#endif
#if defined(UCSR1A)
#define MEGA_UART1_BASE ((uint16_t *)(&UCSR1A))
#define MEGA_UART1 ((mega_uart_t *)MEGA_UART1_BASE)
#endif
#if defined(UCSR2A)
#define MEGA_UART2_BASE ((uint16_t *)(&UCSR2A))
#define MEGA_UART2 ((mega_uart_t *)MEGA_UART2_BASE)
#endif
#if defined(UCSR3A)
#define MEGA_UART3_BASE ((uint16_t *)(&UCSR3A))
#define MEGA_UART3 ((mega_uart_t *)MEGA_UART3_BASE)
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* ATMEGA2560_REGS_H */
#endif /* ATMEGA_REGS_COMMON_H */
/** @} */

26
cpu/atmega_common/periph/gpio.c
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@ -39,8 +39,18 @@
* @brief Define GPIO interruptions for an specific atmega CPU, by default
* 2 (for small atmega CPUs)
*/
#if defined(__AVR_ATmega2560__)
#define GPIO_EXT_INT_NUMOF (8U)
#if defined(INT2_vect)
#define GPIO_EXT_INT_NUMOF (3U)
#elif defined(INT3_vect)
#define GPIO_EXT_INT_NUMOF (4U)
#elif defined(INT4_vect)
#define GPIO_EXT_INT_NUMOF (4U)
#elif defined(INT5_vect)
#define GPIO_EXT_INT_NUMOF (4U)
#elif defined(INT6_vect)
#define GPIO_EXT_INT_NUMOF (4U)
#elif defined(INT7_vect)
#define GPIO_EXT_INT_NUMOF (4U)
#else
#define GPIO_EXT_INT_NUMOF (2U)
#endif
@ -237,32 +247,42 @@ ISR(INT1_vect, ISR_BLOCK)
irq_handler(1); /**< predefined interrupt pin */
}
#if defined(__AVR_ATmega2560__)
#if defined(INT2_vect)
ISR(INT2_vect, ISR_BLOCK)
{
irq_handler(2); /**< predefined interrupt pin */
}
#endif
#if defined(INT3_vect)
ISR(INT3_vect, ISR_BLOCK)
{
irq_handler(3); /**< predefined interrupt pin */
}
#endif
#if defined(INT4_vect)
ISR(INT4_vect, ISR_BLOCK)
{
irq_handler(4); /**< predefined interrupt pin */
}
#endif
#if defined(INT5_vect)
ISR(INT5_vect, ISR_BLOCK)
{
irq_handler(5); /**< predefined interrupt pin */
}
#endif
#if defined(INT6_vect)
ISR(INT6_vect, ISR_BLOCK)
{
irq_handler(6); /**< predefined interrupt pin */
}
#endif
#if defined(INT7_vect)
ISR(INT7_vect, ISR_BLOCK)
{
irq_handler(7); /**< predefined interrupt pin */

4
cpu/atmega_common/periph/spi.c
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@ -8,11 +8,11 @@
*/
/**
* @ingroup cpu_atmega2560
* @ingroup driver_periph
* @{
*
* @file
* @brief Low-level SPI driver implementation
* @brief Low-level SPI driver implementation for ATmega family
*
* @author Daniel Amkaer Sorensen <daniel.amkaer@gmail.com>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>

2
cpu/atmega_common/periph/timer.c
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@ -11,7 +11,7 @@
* @{
*
* @file
* @brief Low-level timer driver implementation for the ATmega2560 CPU
* @brief Low-level timer driver implementation for the ATmega family
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>

34
cpu/atmega_common/thread_arch.c
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@ -44,18 +44,18 @@ static void __enter_thread_mode(void);
* a marker (AFFE) - for debugging purposes (helps finding the stack
* -----------------------------------------------------------------------
* a 16 Bit pointer to sched_task_exit
* (Optional 17 bit (bit is set to zero) for ATmega2560
* (Optional 17 bit (bit is set to zero) for devices with > 128kb FLASH)
* -----------------------------------------------------------------------
* a 16 Bit pointer to task_func
* this is placed exactly at the place where the program counter would be
* stored normally and thus can be returned to when __context_restore()
* has been run
* (Optional 17 bit (bit is set to zero) for ATmega2560
* (Optional 17 bit (bit is set to zero) for devices with > 128kb FLASH)
* -----------------------------------------------------------------------
* saved registers from context:
* r0
* status register
* (Optional EIND and RAMPZ registers for ATmega2560)
* (Optional EIND and RAMPZ registers)
* r1 - r23
* pointer to arg in r24 and r25
* r26 - r31
@ -89,8 +89,8 @@ char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
tmp_adress >>= 8;
*stk = (uint8_t)(tmp_adress & (uint16_t) 0x00ff);
#if defined(__AVR_ATmega2560__)
/* The ATMega2560 uses a 17 bit PC, we set whole the top byte forcibly to 0 */
#if FLASHEND > 0x1ffff
/* Devices with more than 128kb FLASH use a 17 bit PC, we set whole the top byte forcibly to 0 */
stk--;
*stk = (uint8_t) 0x00;
#endif
@ -103,8 +103,8 @@ char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
tmp_adress >>= 8;
*stk = (uint8_t)(tmp_adress & (uint16_t) 0x00ff);
#if defined(__AVR_ATmega2560__)
/* The ATMega2560 uses a 17 byte PC, we set the top byte forcibly to 0 */
#if FLASHEND > 0x1ffff
/* Devices with more than 128kb FLASH use a 17 bit PC, we set whole the top byte forcibly to 0 */
stk--;
*stk = (uint8_t) 0x00;
#endif
@ -118,12 +118,12 @@ char *thread_arch_stack_init(thread_task_func_t task_func, void *arg,
stk--;
*stk = (uint8_t) 0x80;
#if defined(__AVR_ATmega2560__)
/* EIND */
#if defined(EIND)
stk--;
*stk = (uint8_t) 0x00;
#endif
/* RAMPZ */
#if defined(RAMPZ)
stk--;
*stk = (uint8_t) 0x00;
#endif
@ -259,10 +259,11 @@ __attribute__((always_inline)) static inline void __context_save(void)
"in r0, __SREG__ \n\t"
"cli \n\t"
"push r0 \n\t"
#if defined(__AVR_ATmega2560__)
/* EIND and RAMPZ */
"in r0, 0x3b \n\t"
#if defined(RAMPZ)
"in r0, __RAMPZ__ \n\t"
"push r0 \n\t"
#endif
#if defined(EIND)
"in r0, 0x3c \n\t"
"push r0 \n\t"
#endif
@ -348,12 +349,13 @@ __attribute__((always_inline)) static inline void __context_restore(void)
"pop r3 \n\t"
"pop r2 \n\t"
"pop r1 \n\t"
#if defined(__AVR_ATmega2560__)
/* EIND and RAMPZ */
#if defined(EIND)
"pop r0 \n\t"
"out 0x3c, r0 \n\t"
#endif
#if defined(RAMPZ)
"pop r0 \n\t"
"out 0x3b, r0 \n\t"
"out __RAMPZ__, r0 \n\t"
#endif
"pop r0 \n\t"
"out __SREG__, r0 \n\t"

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