stm32l1: initial port for the nucleo-l1 board and stm32l1 cpu

9 years ago · 07d76d7127
parent d8d3e7e4e5
commit 07d76d7127
32 changed files with 10524 additions and 0 deletions
--- a/boards/nucleo-l1/Makefile
+++ b/boards/nucleo-l1/Makefile
@ -0,0 +1,3 @@
+MODULE =$(BOARD)_base
+
+include $(RIOTBASE)/Makefile.base
--- a/boards/nucleo-l1/Makefile.features
+++ b/boards/nucleo-l1/Makefile.features
@ -0,0 +1,2 @@
+FEATURES_PROVIDED += periph_gpio periph_uart periph_spi periph_i2c periph_cpuid
+FEATURES_PROVIDED += cpp
--- a/boards/nucleo-l1/Makefile.include
+++ b/boards/nucleo-l1/Makefile.include
@ -0,0 +1,56 @@
+## the cpu to build for
+export CPU = stm32l1
+export CPU_MODEL = stm32l152ret6
+
+#define the default port depending on the host OS
+OS := $(shell uname)
+ifeq ($(OS),Linux)
+  PORT ?= /dev/ttyACM0
+else ifeq ($(OS),Darwin)
+  PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
+else
+  $(info CAUTION: No flash tool for your host system found!)
+  # TODO: add support for windows as host platform
+endif
+export PORT
+
+# define tools used for building the project
+export PREFIX = arm-none-eabi-
+export CC = $(PREFIX)gcc
+export CXX = $(PREFIX)g++
+export AR = $(PREFIX)ar
+export AS = $(PREFIX)as
+export LINK = $(PREFIX)gcc
+export SIZE = $(PREFIX)size
+export OBJCOPY = $(PREFIX)objcopy
+export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm
+export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/flash.sh
+export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
+export DEBUGSERVER = $(RIOTBOARD)/$(BOARD)/dist/debug-server.sh
+export RESET = $(RIOTBOARD)/$(BOARD)/dist/reset.sh
+
+# unwanted (CXXUWFLAGS) and extra (CXXEXFLAGS) flags for c++
+export CXXUWFLAGS +=
+export CXXEXFLAGS +=
+
+# define build specific options
+export CPU_USAGE = -mcpu=cortex-m3
+export FPU_USAGE =
+export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
+export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
+export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
+export LINKFLAGS += -ggdb -g3 -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
+# $(LINKERSCRIPT) is specified in cpu/Makefile.include
+export LINKFLAGS += -T$(LINKERSCRIPT)
+export OFLAGS = -O binary
+export FFLAGS = $(HEXFILE)
+export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(ELFFILE)
+export TERMFLAGS += -p "$(PORT)"
+
+# use the nano-specs of the NewLib when available
+ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
+export LINKFLAGS += -specs=nano.specs -lc -lnosys
+endif
+
+# export board specific includes to the global includes-listing
+export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/
--- a/boards/nucleo-l1/board.c
+++ b/boards/nucleo-l1/board.c
@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     board_nucleo-l1
+ * @{
+ *
+ * @file        board.c
+ * @brief       Board specific implementations for the nucleo-l1 board
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "cpu.h"
+
+static void leds_init(void);
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+
+    /* initialize the boards LEDs */
+    leds_init();
+}
+
+/**
+ * @brief Initialize the boards on-board LEDs
+ *
+ * The LED initialization is hard-coded in this function. As the LED is soldered
+ * onto the board it is fixed to its CPU pins.
+ *
+ * The green LED is connected to pin PA5
+ */
+static void leds_init(void)
+{
+    /* enable clock for port GPIOE */
+    RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
+
+    /* set output speed to 50MHz */
+    LED_GREEN_PORT->OSPEEDR |= 0x00000c00;
+    /* set output type to push-pull */
+    LED_GREEN_PORT->OTYPER &= ~(0x00000020);
+    /* configure pins as general outputs */
+    LED_GREEN_PORT->MODER &= ~(0x00000c00);
+    LED_GREEN_PORT->MODER |= 0x00000400;
+    /* disable pull resistors */
+    LED_GREEN_PORT->PUPDR &= ~(0x00000c00);
+
+    /* turn all LEDs off */
+    LED_GREEN_PORT->BRR = 0x00c0;
+}
--- a/boards/nucleo-l1/dist/debug-server.sh
+++ b/boards/nucleo-l1/dist/debug-server.sh
@ -0,0 +1,10 @@
+#!/bin/sh
+
+echo "##"
+echo "## Starting debug server"
+echo "##"
+
+openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \
+    -c "init" \
+    -c "targets" \
+    -c "reset halt"
--- a/boards/nucleo-l1/dist/debug.sh
+++ b/boards/nucleo-l1/dist/debug.sh
@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ ! -f "$2" ]; then
+    echo "ELF-file $2 does not exist"
+    exit 1
+fi
+
+echo "##"
+echo "## Debugging $2"
+echo "##"
+arm-none-eabi-gdb -tui -command="$1" $2
--- a/boards/nucleo-l1/dist/flash.sh
+++ b/boards/nucleo-l1/dist/flash.sh
@ -0,0 +1,13 @@
+#!/bin/bash
+
+echo "##"
+echo "## Flashing $1"
+echo "##"
+
+openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \
+    -c "init" \
+    -c "targets" \
+    -c "reset halt" \
+    -c "program $1 0x8000000 verify" \
+    -c "reset run"\
+    -c "shutdown"
--- a/boards/nucleo-l1/dist/gdb.conf
+++ b/boards/nucleo-l1/dist/gdb.conf
@ -0,0 +1 @@
+tar extended-remote :3333
--- a/boards/nucleo-l1/dist/openocd.cfg
+++ b/boards/nucleo-l1/dist/openocd.cfg
@ -0,0 +1,6 @@
+# stml1 Target
+source [find interface/stlink-v2-1.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l.cfg]
--- a/boards/nucleo-l1/dist/reset.sh
+++ b/boards/nucleo-l1/dist/reset.sh
@ -0,0 +1,10 @@
+#!/bin/bash
+
+echo "##"
+echo "## Resetting $1"
+echo "##"
+
+openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \
+    -c "init" \
+    -c "reset run"\
+    -c "shutdown"
--- a/boards/nucleo-l1/include/board.h
+++ b/boards/nucleo-l1/include/board.h
@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup    board_nucleo-l1 nucleo-l1
+ * @ingroup     boards
+ * @brief       Board specific files for the nucleo-l1 board.
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the nucleo-l1 board.
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include <stdint.h>
+
+#include "cpu.h"
+#include "periph_conf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Define the nominal CPU core clock in this board
+ */
+#define F_CPU               CLOCK_CORECLOCK
+
+/**
+ * @name Define the UART to be used as stdio and its baudrate
+ * @{
+ */
+#define STDIO               UART_0
+#define STDIO_BAUDRATE      (115200U)
+#define STDIO_RX_BUFSIZE    (64U)
+/** @} */
+
+/**
+ * @name Assign the hardware timer
+ */
+#define HW_TIMER            TIMER_0
+
+/**
+ * @name LED pin definitions
+ * @{
+ */
+#define LED_GREEN_PORT      (GPIOA)
+#define LED_GREEN_PIN       (5)
+/** @} */
+
+/**
+ * @name Macros for controlling the on-board LEDs.
+ * @{
+ */
+#define LED_RED_ON
+#define LED_RED_OFF
+#define LED_RED_TOGGLE
+
+#define LED_GREEN_ON        (LED_GREEN_PORT->ODR &= ~(1<<LED_GREEN_PIN))
+#define LED_GREEN_OFF       (LED_GREEN_PORT->ODR |= (1<<LED_GREEN_PIN))
+#define LED_GREEN_TOGGLE    (LED_GREEN_PORT->ODR ^= (1<<LED_GREEN_PIN))
+
+#define LED_ORANGE_ON
+#define LED_ORANGE_OFF
+#define LED_ORANGE_TOGGLE
+/** @} */
+
+/**
+ * @name Define the type for the radio packet length for the transceiver
+ */
+typedef uint8_t radio_packet_length_t;
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */
+/** @} */
--- a/boards/nucleo-l1/include/periph_conf.h
+++ b/boards/nucleo-l1/include/periph_conf.h
@ -0,0 +1,292 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     board_nucleo-l1
+ * @{
+ *
+ * @file        periph_conf.h
+ * @brief       Peripheral MCU configuration for the nucleo-l1 board
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ */
+
+#ifndef __PERIPH_CONF_H
+#define __PERIPH_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ **/
+#define CLOCK_HSI           (16000000U)             /* frequency of external oscillator */
+#define CLOCK_CORECLOCK     (32000000U)             /* targeted core clock frequency */
+/* configuration of PLL prescaler and multiply values */
+/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
+#define CLOCK_PLL_HSE_DIV   RCC_CFGR_PLLDIV2
+#define CLOCK_PLL_HSE_MUL   RCC_CFGR_PLLMUL4
+/* configuration of peripheral bus clock prescalers */
+#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1      /* AHB clock -> 32MHz */
+#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 32MHz */
+#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
+/* configuration of flash access cycles */
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+#define TIMER_NUMOF         (2U)
+#define TIMER_0_EN          1
+#define TIMER_1_EN          1
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV_0       TIM2
+#define TIMER_0_DEV_1       TIM3
+#define TIMER_0_CHANNELS    4
+#define TIMER_0_PRESCALER   (32U)
+#define TIMER_0_MAX_VALUE   (0xffff)
+#define TIMER_0_CLKEN()     (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
+#define TIMER_0_ISR_0       isr_tim2
+#define TIMER_0_ISR_1       isr_tim3
+#define TIMER_0_IRQ_CHAN_0  TIM2_IRQn
+#define TIMER_0_IRQ_CHAN_1  TIM3_IRQn
+#define TIMER_0_IRQ_PRIO    1
+#define TIMER_0_TRIG_SEL    TIM_SMCR_TS_0
+
+/* Timer 1 configuration */
+#define TIMER_1_DEV_0       TIM4
+#define TIMER_1_DEV_1       TIM5
+#define TIMER_1_CHANNELS    4
+#define TIMER_1_PRESCALER   (32U)
+#define TIMER_1_MAX_VALUE   (0xffff)
+#define TIMER_1_CLKEN()     (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
+#define TIMER_1_ISR_0       isr_tim4
+#define TIMER_1_ISR_1       isr_tim5
+#define TIMER_1_IRQ_CHAN_0  TIM4_IRQn
+#define TIMER_1_IRQ_CHAN_1  TIM5_IRQn
+#define TIMER_1_IRQ_PRIO    1
+#define TIMER_1_TRIG_SEL    TIM_SMCR_TS_1
+/** @} */
+
+/**
+ * @brief UART configuration
+ */
+#define UART_NUMOF          (1U)
+#define UART_0_EN           1
+#define UART_IRQ_PRIO       1
+
+/* UART 0 device configuration */
+#define UART_0_DEV          USART2
+#define UART_0_CLKEN()      (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
+#define UART_0_CLK          (CLOCK_CORECLOCK)   /* UART clock runs with 32MHz (F_CPU / 1) */
+#define UART_0_IRQ          USART2_IRQn
+#define UART_0_ISR          isr_usart2
+#define UART_0_BUS_FREQ     32000000
+/* UART 0 pin configuration */
+#define UART_0_PORT         GPIOA
+#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define UART_0_RX_PIN       3
+#define UART_0_TX_PIN       2
+#define UART_0_AF           7
+
+/**
+ * @brief GPIO configuration
+ */
+#define GPIO_NUMOF          16
+#define GPIO_0_EN           1
+#define GPIO_1_EN           1
+#define GPIO_2_EN           1
+#define GPIO_3_EN           1
+#define GPIO_4_EN           1
+#define GPIO_5_EN           1
+#define GPIO_6_EN           1
+#define GPIO_7_EN           1
+#define GPIO_8_EN           1
+#define GPIO_9_EN           1
+#define GPIO_10_EN          1
+#define GPIO_11_EN          1
+#define GPIO_12_EN          1
+#define GPIO_13_EN          1
+#define GPIO_14_EN          1
+#define GPIO_15_EN          1
+#define GPIO_IRQ_PRIO       1
+
+/* IRQ config */
+#define GPIO_IRQ_0          GPIO_13
+#define GPIO_IRQ_1          GPIO_14
+#define GPIO_IRQ_2          GPIO_7
+#define GPIO_IRQ_3          GPIO_0
+#define GPIO_IRQ_4          GPIO_5
+#define GPIO_IRQ_5          GPIO_12
+#define GPIO_IRQ_6          GPIO_11
+#define GPIO_IRQ_7          GPIO_1
+#define GPIO_IRQ_8          GPIO_3
+#define GPIO_IRQ_9          GPIO_2
+#define GPIO_IRQ_10         GPIO_4
+#define GPIO_IRQ_11         GPIO_6
+#define GPIO_IRQ_12         GPIO_15
+#define GPIO_IRQ_13         GPIO_8
+#define GPIO_IRQ_14         GPIO_9
+#define GPIO_IRQ_15         GPIO_10
+
+/* GPIO channel 0 config */
+#define GPIO_0_PORT         GPIOA                   /* Used for user button 1 */
+#define GPIO_0_PIN          3
+#define GPIO_0_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_0_EXTI_CFG()   (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PA)
+#define GPIO_0_IRQ          EXTI3_IRQn
+/* GPIO channel 1 config */
+#define GPIO_1_PORT         GPIOC
+#define GPIO_1_PIN          7
+#define GPIO_1_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_1_EXTI_CFG()   (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PC)
+#define GPIO_1_IRQ          EXTI9_5_IRQn
+/* GPIO channel 2 config */
+#define GPIO_2_PORT         GPIOA
+#define GPIO_2_PIN          9
+#define GPIO_2_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_2_EXTI_CFG()   (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA)
+#define GPIO_2_IRQ          EXTI9_5_IRQn
+/* GPIO channel 3 config */
+#define GPIO_3_PORT         GPIOA
+#define GPIO_3_PIN          8
+#define GPIO_3_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_3_EXTI_CFG()   (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA)
+#define GPIO_3_IRQ          EXTI9_5_IRQn
+/* GPIO channel 4 config */
+#define GPIO_4_PORT         GPIOB
+#define GPIO_4_PIN          10
+#define GPIO_4_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define GPIO_4_EXTI_CFG()   (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PB)
+#define GPIO_4_IRQ          EXTI15_10_IRQn
+/* GPIO channel 5 config */
+#define GPIO_5_PORT         GPIOB
+#define GPIO_5_PIN          4
+#define GPIO_5_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define GPIO_5_EXTI_CFG()   (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PB)
+#define GPIO_5_IRQ          EXTI4_IRQn
+/* GPIO channel 6 config */
+#define GPIO_6_PORT         GPIOC
+#define GPIO_6_PIN          11
+#define GPIO_6_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_6_EXTI_CFG()   (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PC)
+#define GPIO_6_IRQ          EXTI15_10_IRQn
+/* GPIO channel 7 config */
+#define GPIO_7_PORT         GPIOC
+#define GPIO_7_PIN          2
+#define GPIO_7_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_7_EXTI_CFG()   (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PC)
+#define GPIO_7_IRQ          EXTI2_IRQn
+/* GPIO channel 8 config */
+#define GPIO_8_PORT         GPIOA
+#define GPIO_8_PIN          13
+#define GPIO_8_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_8_EXTI_CFG()   (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PA)
+#define GPIO_8_IRQ          EXTI15_10_IRQn
+/* GPIO channel 9 config */
+#define GPIO_9_PORT         GPIOA
+#define GPIO_9_PIN          14
+#define GPIO_9_CLKEN()      (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_9_EXTI_CFG()   (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PA)
+#define GPIO_9_IRQ          EXTI15_10_IRQn
+/* GPIO channel 10 config */
+#define GPIO_10_PORT        GPIOA
+#define GPIO_10_PIN         15
+#define GPIO_10_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_10_EXTI_CFG()  (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PA)
+#define GPIO_10_IRQ         EXTI15_10_IRQn
+/* GPIO channel 11 config */
+#define GPIO_11_PORT        GPIOB   /* SPI CS Pin */
+#define GPIO_11_PIN         6
+#define GPIO_11_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define GPIO_11_EXTI_CFG()  (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PB)
+#define GPIO_11_IRQ         EXTI9_5_IRQn
+/* GPIO channel 12 config */
+#define GPIO_12_PORT        GPIOC
+#define GPIO_12_PIN         5
+#define GPIO_12_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_12_EXTI_CFG()  (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PC)
+#define GPIO_12_IRQ         EXTI9_5_IRQn
+/* GPIO channel 13 config */
+#define GPIO_13_PORT        GPIOA
+#define GPIO_13_PIN         0
+#define GPIO_13_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_13_EXTI_CFG()  (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
+#define GPIO_13_IRQ         EXTI0_IRQn
+/* GPIO channel 14 config */
+#define GPIO_14_PORT        GPIOA
+#define GPIO_14_PIN         1
+#define GPIO_14_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define GPIO_14_EXTI_CFG()  (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PA)
+#define GPIO_14_IRQ         EXTI1_IRQn
+/* GPIO channel 15 config */
+#define GPIO_15_PORT        GPIOC
+#define GPIO_15_PIN         12
+#define GPIO_15_CLKEN()     (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_15_EXTI_CFG()  (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PC)
+#define GPIO_15_IRQ         EXTI15_10_IRQn
+
+/**
+ * @brief SPI configuration
+ * @{
+ */
+#define SPI_NUMOF           (1U)
+#define SPI_0_EN            1
+
+/* SPI 0 device configuration */
+#define SPI_0_DEV           SPI1
+#define SPI_0_CLKEN()       (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define SPI_0_IRQ           SPI1_IRQn
+#define SPI_0_ISR           isr_spi1
+/* SPI 0 pin configuration */
+#define SPI_0_PORT_CLKEN()  (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define SPI_0_PORT          GPIOA
+#define SPI_0_PIN_SCK       5
+#define SPI_0_PIN_MOSI      7
+#define SPI_0_PIN_MISO      6
+#define SPI_0_PIN_AF        5
+/** @} */
+
+/**
+ * @name I2C configuration
+  * @{
+ */
+#define I2C_NUMOF           (1U)
+#define I2C_0_EN            1
+#define I2C_IRQ_PRIO        1
+#define I2C_APBCLK          (36000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV           I2C1
+#define I2C_0_CLKEN()       (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
+#define I2C_0_CLKDIS()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ       I2C1_EV_IRQn
+#define I2C_0_EVT_ISR       isr_i2c1_ev
+#define I2C_0_ERR_IRQ       I2C1_ER_IRQn
+#define I2C_0_ERR_ISR       isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_PORT_CLKEN()  (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define I2C_0_PORT          GPIOB
+#define I2C_0_SCL_PIN       8
+#define I2C_0_SCL_AF        4
+#define I2C_0_SDA_PIN       9
+#define I2C_0_SDA_AF        4
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PERIPH_CONF_H */
+/** @} */
--- a/cpu/stm32l1/Makefile
+++ b/cpu/stm32l1/Makefile
@ -0,0 +1,7 @@
+# define the module that is build
+MODULE =cpu
+
+# add a list of subdirectories, that should also be build
+DIRS += periph $(CORTEXM_COMMON)
+
+include $(RIOTBASE)/Makefile.base
--- a/cpu/stm32l1/Makefile.include
+++ b/cpu/stm32l1/Makefile.include
@ -0,0 +1,25 @@
+# this CPU implementation is using the new core/CPU interface
+export CFLAGS += -DCOREIF_NG=1
+
+# tell the build system that the CPU depends on the Cortex-M common files
+export USEMODULE += cortex-m3_common
+
+# define path to cortex-m common module, which is needed for this CPU
+export CORTEXM_COMMON = $(RIOTCPU)/cortex-m3_common/
+
+# define the linker script to use for this CPU
+export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/$(CPU_MODEL)_linkerscript.ld
+
+# include CPU specific includes
+export INCLUDES += -I$(RIOTCPU)/$(CPU)/include
+
+# explicitly tell the linker to link the syscalls and startup code.
+# Without this the interrupt vectors will not be linked correctly!
+export UNDEF += $(BINDIR)cpu/syscalls.o
+export UNDEF += $(BINDIR)cpu/startup.o
+
+# export the peripheral drivers to be linked into the final binary
+export USEMODULE += periph
+
+# CPU depends on the cortex-m common module, so include it
+include $(CORTEXM_COMMON)Makefile.include
--- a/cpu/stm32l1/cpu.c
+++ b/cpu/stm32l1/cpu.c
@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     cpu_stm32l1
+ * @{
+ *
+ * @file        cpu.c
+ * @brief       Implementation of the kernel cpu functions
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "board.h"
+#include "periph_conf.h"
+
+static void clk_init(void);
+
+void cpu_init(void)
+{
+    /* set PendSV priority to the lowest possible priority */
+    NVIC_SetPriority(PendSV_IRQn, 0xff);
+
+    /* initialize system clocks */
+    clk_init();
+
+    /* configure the vector table location to internal flash */
+    SCB->VTOR = FLASH_BASE;
+}
+
+/**
+ * @brief Configure the clock system of the stm32f1
+ *
+ */
+static void clk_init(void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+    /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */
+    RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL);
+    /* Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
+    /* Disable all interruptss  */
+    RCC->CIR = 0x0;
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
+    /* Enable HSE */
+    RCC->CR |= RCC_CR_HSION;
+    /* Wait till HSE is ready,
+     * NOTE: the MCU will stay here forever if no HSE clock is connected */
+    while (!(RCC->CR & RCC_CR_HSIRDY));
+    FLASH->ACR |= FLASH_ACR_ACC64;
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+    /* Flash 1 wait state */
+    FLASH->ACR |= CLOCK_FLASH_LATENCY;
+    /* Power enable */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    /* Select the Voltage Range 1 (1.8 V) */
+    PWR->CR = PWR_CR_VOS_0;
+    /* Wait Until the Voltage Regulator is ready */
+    while((PWR->CSR & PWR_CSR_VOSF) != 0);
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
+    /*  PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
+    RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+    /* Wait till PLL is ready */
+    while ((RCC->CR & RCC_CR_PLLRDY) == 0);
+    /* Select PLL as system clock source */
+    RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
+}
--- a/cpu/stm32l1/hwtimer_arch.c
+++ b/cpu/stm32l1/hwtimer_arch.c
@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     cpu_stm32l1
+ * @{
+ *
+ * @file        hwtimer_arch.c
+ * @brief       Implementation of the kernels hwtimer interface
+ *
+ * The hardware timer implementation uses the Cortex build-in system timer as backend.
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "arch/hwtimer_arch.h"
+#include "thread.h"
+#include "board.h"
+#include "periph/timer.h"
+
+#define ENABLE_DEBUG (0)
+#include "debug.h"
+
+
+void irq_handler(int channel);
+void (*timeout_handler)(int);
+
+
+void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
+{
+    timeout_handler = handler;
+    timer_init(HW_TIMER, 1, &irq_handler);
+}
+
+void hwtimer_arch_enable_interrupt(void)
+{
+    timer_irq_enable(HW_TIMER);
+}
+
+void hwtimer_arch_disable_interrupt(void)
+{
+    timer_irq_disable(HW_TIMER);
+}
+
+void hwtimer_arch_set(unsigned long offset, short timer)
+{
+    timer_set(HW_TIMER, timer, offset);
+}
+
+void hwtimer_arch_set_absolute(unsigned long value, short timer)
+{
+    timer_set_absolute(HW_TIMER, timer, value);
+}
+
+void hwtimer_arch_unset(short timer)
+{
+    timer_clear(HW_TIMER, timer);
+}
+
+unsigned long hwtimer_arch_now(void)
+{
+    return timer_read(HW_TIMER);
+}
+
+void irq_handler(int channel)
+{
+    timeout_handler((short)channel);
+}
--- a/cpu/stm32l1/include/cpu-conf.h
+++ b/cpu/stm32l1/include/cpu-conf.h
@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup        cpu_stm32l1 stm32l1
+ * @addtogroup      cpu
+ * @brief           CPU specific implementations for the STM32F1
+ * @{
+ *
+ * @file
+ * @brief           Implementation specific CPU configuration options
+ *
+ * @author          Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ */
+
+#ifndef CPUCONF_H_
+#define CPUCONF_H_
+
+#include "stm32l1xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Kernel configuration
+ *
+ * @{
+ */
+#define KERNEL_CONF_STACKSIZE_PRINTF    (1024)
+
+#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
+#define KERNEL_CONF_STACKSIZE_DEFAULT   (1024)
+#endif
+
+#define KERNEL_CONF_STACKSIZE_IDLE      (256)
+/** @} */
+
+/**
+ * @name UART0 buffer size definition for compatibility reasons
+ *
+ * TODO: remove once the remodeling of the uart0 driver is done
+ * @{
+ */
+#ifndef UART0_BUFSIZE
+#define UART0_BUFSIZE                   (128)
+#endif
+/** @} */
+
+/**
+ * @name Length for reading CPU_ID
+ */
+#define CPUID_ID_LEN                      (12)
+
+/**
+ * @name Definition of different panic modes
+ */
+typedef enum {
+    HARD_FAULT,
+    WATCHDOG,
+    BUS_FAULT,
+    USAGE_FAULT,
+    DUMMY_HANDLER
+} panic_t;
+
+#define TRANSCEIVER_BUFFER_SIZE (3)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CPU_CONF_H */
+/** @} */
+/** @} */
--- a/cpu/stm32l1/include/hwtimer_cpu.h
+++ b/cpu/stm32l1/include/hwtimer_cpu.h
@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup         cpu_stm32l1
+ * @{
+ *
+ * @file
+ * @brief           CPU specific hwtimer configuration options
+ *
+ * @author          Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ */
+
+#ifndef HWTIMER_CPU_H_
+#define HWTIMER_CPU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Hardware timer configuration
+ * @{
+ */
+#define HWTIMER_MAXTIMERS       (4)             /**< the CPU implementation supports 4 HW timers */
+#define HWTIMER_SPEED           (1000000U)      /**< the HW timer runs with 1MHz */
+#define HWTIMER_MAXTICKS        (0xFFFFFFFF)    /**< 32-bit timer */
+#define HWTIMER_WAIT_OVERHEAD   (3)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HWTIMER_CPU_H_ */
+/** @} */
--- a/cpu/stm32l1/include/stm32l1xx.h
+++ b/cpu/stm32l1/include/stm32l1xx.h
--- a/cpu/stm32l1/lpm_arch.c
+++ b/cpu/stm32l1/lpm_arch.c
@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup     cpu_stm32l1
+ * @{
+ *
+ * @file        lpm_arch.c
+ * @brief       Implementation of the kernel's lpm interface
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "arch/lpm_arch.h"
+
+void lpm_arch_init(void)
+{
+    /* TODO */
+}
+
+enum lpm_mode lpm_arch_set(enum lpm_mode target)
+{
+    /* TODO */
+    return 0;
+}
+
+enum lpm_mode lpm_arch_get(void)
+{
+    /* TODO */
+    return 0;
+}
+
+void lpm_arch_awake(void)
+{
+    /* TODO */
+}
+
+void lpm_arch_begin_awake(void)
+{
+    /* TODO */
+}
+
+void lpm_arch_end_awake(void)
+{
+    /* TODO */
+}
--- a/cpu/stm32l1/periph/Makefile
+++ b/cpu/stm32l1/periph/Makefile
@ -0,0 +1,5 @@
+# define the module name
+MODULE = periph
+
+# include RIOTs generic Makefile
+include $(RIOTBASE)/Makefile.base
--- a/cpu/stm32l1/periph/cpuid.c
+++ b/cpu/stm32l1/periph/cpuid.c
@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 FU Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @addtogroup  driver_periph
+ * @{
+ *
+ * @file        cpuid.c
+ * @brief       Low-level CPUID driver implementation
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ */
+
+#include <string.h>
+#include "cpu-conf.h"
+
+#include "periph/cpuid.h"
+
+#define STM32L1_CPUID_ADDR  (0x1ff800d0)
+
+void cpuid_get(void *id)
+{
+    memcpy(id, (void *)(STM32L1_CPUID_ADDR), CPUID_ID_LEN);
+}
+
+/** @} */
--- a/cpu/stm32l1/periph/gpio.c
+++ b/cpu/stm32l1/periph/gpio.c
@ -0,0 +1,587 @@
+/*
+ * Copyright (C) 2014 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @addtogroup  driver_periph
+ * @{
+ *
+ * @file
+ * @brief       Low-level GPIO driver implementation
+ *
+ * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "sched.h"
+#include "thread.h"
+#include "periph/gpio.h"
+#include "periph_conf.h"
+
+/* guard file in case no GPIO devices are defined */
+#if GPIO_NUMOF
+
+typedef struct {
+    gpio_cb_t cb;
+    void *arg;
+} gpio_state_t;
+
+static gpio_state_t gpio_config[GPIO_NUMOF];
+
+/* static port mappings */
+static GPIO_TypeDef *const gpio_port_map[GPIO_NUMOF] = {
+#if GPIO_0_EN
+    [GPIO_0] = GPIO_0_PORT,
+#endif
+#if GPIO_1_EN
+    [GPIO_1] = GPIO_1_PORT,
+#endif
+#if GPIO_2_EN
+    [GPIO_2] = GPIO_2_PORT,
+#endif
+#if GPIO_3_EN
+    [GPIO_3] = GPIO_3_PORT,
+#endif
+#if GPIO_4_EN
+    [GPIO_4] = GPIO_4_PORT,
+#endif
+#if GPIO_5_EN
+    [GPIO_5] = GPIO_5_PORT,
+#endif
+#if GPIO_6_EN
+    [GPIO_6] = GPIO_6_PORT,
+#endif
+#if GPIO_7_EN
+    [GPIO_7] = GPIO_7_PORT,
+#endif
+#if GPIO_8_EN
+    [GPIO_8] = GPIO_8_PORT,
+#endif
+#if GPIO_9_EN
+    [GPIO_9] = GPIO_9_PORT,
+#endif
+#if GPIO_10_EN
+    [GPIO_10] = GPIO_10_PORT,
+#endif
+#if GPIO_11_EN
+    [GPIO_11] = GPIO_11_PORT,
+#endif
+#if GPIO_12_EN
+    [GPIO_12] = GPIO_12_PORT,
+#endif
+#if GPIO_13_EN
+    [GPIO_13] = GPIO_13_PORT,
+#endif
+#if GPIO_14_EN
+    [GPIO_14] = GPIO_14_PORT,
+#endif
+#if GPIO_15_EN
+    [GPIO_15] = GPIO_15_PORT,
+#endif
+};
+
+/* static pin mappings */
+static const uint8_t gpio_pin_map[GPIO_NUMOF] = {
+#if GPIO_0_EN
+    [GPIO_0] = GPIO_0_PIN,
+#endif
+#if GPIO_1_EN
+    [GPIO_1] = GPIO_1_PIN,
+#endif
+#if GPIO_2_EN
+    [GPIO_2] = GPIO_2_PIN,
+#endif
+#if GPIO_3_EN
+    [GPIO_3] = GPIO_3_PIN,
+#endif
+#if GPIO_4_EN
+    [GPIO_4] = GPIO_4_PIN,
+#endif
+#if GPIO_5_EN
+    [GPIO_5] = GPIO_5_PIN,
+#endif
+#if GPIO_6_EN
+    [GPIO_6] = GPIO_6_PIN,
+#endif
+#if GPIO_7_EN
+    [GPIO_7] = GPIO_7_PIN,
+#endif
+#if GPIO_8_EN
+    [GPIO_8] = GPIO_8_PIN,
+#endif
+#if GPIO_9_EN
+    [GPIO_9] = GPIO_9_PIN,
+#endif
+#if GPIO_10_EN
+    [GPIO_10] = GPIO_10_PIN,
+#endif
+#if GPIO_11_EN
+    [GPIO_11] = GPIO_11_PIN,
+#endif
+#if GPIO_12_EN
+    [GPIO_12] = GPIO_12_PIN,
+#endif
+#if GPIO_13_EN
+    [GPIO_13] = GPIO_13_PIN,
+#endif
+#if GPIO_14_EN
+    [GPIO_14] = GPIO_14_PIN,
+#endif
+#if GPIO_15_EN
+    [GPIO_15] = GPIO_15_PIN,
+#endif
+};
+
+/* static irq mappings */
+static const IRQn_Type gpio_irq_map[GPIO_NUMOF] = {
+#if GPIO_0_EN
+    [GPIO_0] = GPIO_0_IRQ,
+#endif
+#if GPIO_1_EN
+    [GPIO_1] = GPIO_1_IRQ,
+#endif
+#if GPIO_2_EN
+    [GPIO_2] = GPIO_2_IRQ,
+#endif
+#if GPIO_3_EN
+    [GPIO_3] = GPIO_3_IRQ,
+#endif
+#if GPIO_4_EN
+    [GPIO_4] = GPIO_4_IRQ,
+#endif
+#if GPIO_5_EN
+    [GPIO_5] = GPIO_5_IRQ,
+#endif
+#if GPIO_6_EN
+    [GPIO_6] = GPIO_6_IRQ,
+#endif
+#if GPIO_7_EN
+    [GPIO_7] = GPIO_7_IRQ,
+#endif
+#if GPIO_8_EN
+    [GPIO_8] = GPIO_8_IRQ,
+#endif
+#if GPIO_9_EN
+    [GPIO_9] = GPIO_9_IRQ,
+#endif
+#if GPIO_10_EN
+    [GPIO_10] = GPIO_10_IRQ,
+#endif
+#if GPIO_11_EN
+    [GPIO_11] = GPIO_11_IRQ,
+#endif
+#if GPIO_12_EN
+    [GPIO_12] = GPIO_12_IRQ,
+#endif
+#if GPIO_13_EN
+    [GPIO_13] = GPIO_13_IRQ,
+#endif
+#if GPIO_14_EN
+    [GPIO_14] = GPIO_14_IRQ,
+#endif
+#if GPIO_15_EN
+    [GPIO_15] = GPIO_15_IRQ,
+#endif
+};
+
+int gpio_init_out(gpio_t dev, gpio_pp_t pullup)
+{
+    GPIO_TypeDef *port;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return -1;
+    }
+
+    port = gpio_port_map[dev];
+    pin = gpio_pin_map[dev];
+
+    port->MODER &= ~(2 << (2 * pin));           /* set pin to output mode */
+    port->MODER |= (1 << (2 * pin));
+    port->OTYPER &= ~(1 << pin);                /* set to push-pull configuration */
+    port->OSPEEDR |= (3 << (2 * pin));          /* set to high speed */
+    port->PUPDR &= ~(3 << (2 * pin));           /* configure push-pull resistors */
+    port->PUPDR |= (pullup << (2 * pin));
+    port->ODR &= ~(1 << pin);                   /* set pin to low signal */
+
+    return 0; /* all OK */
+}
+
+int gpio_init_in(gpio_t dev, gpio_pp_t pullup)
+{
+    GPIO_TypeDef *port;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return -1;
+    }
+
+    port = gpio_port_map[dev];
+    pin = gpio_pin_map[dev];
+
+    port->MODER &= ~(3 << (2 * pin));           /* configure pin as input */
+    port->PUPDR &= ~(3 << (2 * pin));           /* configure push-pull resistors */
+    port->PUPDR |= (pullup << (2 * pin));
+
+    return 0; /* everything alright here */
+}
+
+int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg)
+{
+    int res;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return -1;
+    }
+
+    pin = gpio_pin_map[dev];
+
+    /* configure pin as input */
+    res = gpio_init_in(dev, pullup);
+    if (res < 0) {
+        return res;
+    }
+
+    /* enable clock of the SYSCFG module for EXTI configuration */
+    RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
+
+    /* read pin number, set EXIT channel and enable global interrupt for EXTI channel */
+    switch (dev) {
+#ifdef GPIO_0_EN
+        case GPIO_0:
+            GPIO_0_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_1_EN
+        case GPIO_1:
+            GPIO_1_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_2_EN
+        case GPIO_2:
+            GPIO_2_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_3_EN
+        case GPIO_3:
+            GPIO_3_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_4_EN
+        case GPIO_4:
+            GPIO_4_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_5_EN
+        case GPIO_5:
+            GPIO_5_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_6_EN
+        case GPIO_6:
+            GPIO_6_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_7_EN
+        case GPIO_7:
+            GPIO_7_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_8_EN
+        case GPIO_8:
+            GPIO_8_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_9_EN
+        case GPIO_9:
+            GPIO_9_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_10_EN
+        case GPIO_10:
+            GPIO_10_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_11_EN
+        case GPIO_11:
+            GPIO_11_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_12_EN
+        case GPIO_12:
+            GPIO_12_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_13_EN
+        case GPIO_13:
+            GPIO_13_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_14_EN
+        case GPIO_14:
+            GPIO_14_EXTI_CFG();
+            break;
+#endif
+#ifdef GPIO_15_EN
+        case GPIO_15:
+            GPIO_15_EXTI_CFG();
+            break;
+#endif
+    }
+
+    NVIC_EnableIRQ(gpio_irq_map[dev]);
+
+    /* set callback */
+    gpio_config[dev].cb = cb;
+    gpio_config[dev].arg = arg;
+
+    /* configure the event that triggers an interrupt */
+    switch (flank) {
+        case GPIO_RISING:
+            EXTI->RTSR |= (1 << pin);
+            EXTI->FTSR &= ~(1 << pin);
+            break;
+        case GPIO_FALLING:
+            EXTI->RTSR &= ~(1 << pin);
+            EXTI->FTSR |= (1 << pin);
+            break;
+        case GPIO_BOTH:
+            EXTI->RTSR |= (1 << pin);
+            EXTI->FTSR |= (1 << pin);
+            break;
+    }
+
+    /* clear any pending requests */
+    EXTI->PR = (1 << pin);
+    /* unmask the pins interrupt channel */
+    EXTI->IMR |= (1 << pin);
+
+    return 0;
+}
+
+void gpio_irq_enable(gpio_t dev)
+{
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return;
+    }
+
+    pin = gpio_pin_map[dev];
+    EXTI->IMR |= (1 << pin);
+}
+
+void gpio_irq_disable(gpio_t dev)
+{
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return;
+    }
+
+    pin = gpio_pin_map[dev];
+    EXTI->IMR &= ~(1 << pin);
+}
+
+int gpio_read(gpio_t dev)
+{
+    GPIO_TypeDef *port;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return -1;
+    }
+
+    port = gpio_port_map[dev];
+    pin = gpio_pin_map[dev];
+
+    if (port->MODER & (1 << (pin * 2))) {       /* if configured as output */
+        return port->ODR & (1 << pin);          /* read output data register */
+    } else {
+        return port->IDR & (1 << pin);          /* else read input data register */
+    }
+}
+
+void gpio_set(gpio_t dev)
+{
+    GPIO_TypeDef *port;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return;
+    }
+
+    port = gpio_port_map[dev];
+    pin = gpio_pin_map[dev];
+
+    port->ODR |= (1 << pin);
+}
+
+void gpio_clear(gpio_t dev)
+{
+    GPIO_TypeDef *port;
+    uint8_t pin;
+
+    if (dev >= GPIO_NUMOF) {
+        return;
+    }
+
+    port = gpio_port_map[dev];
+    pin = gpio_pin_map[dev];
+
+    port->ODR &= ~(1 << pin);
+}
+
+void gpio_toggle(gpio_t dev)
+{
+    if (gpio_read(dev)) {
+        gpio_clear(dev);
+    } else {
+        gpio_set(dev);
+    }
+}
+
+void gpio_write(gpio_t dev, int value)
+{
+    if (value) {
+        gpio_set(dev);
+    } else {
+        gpio_clear(dev);
+    }
+}
+
+#ifdef GPIO_IRQ_0
+void isr_exti0(void)
+{
+    if (EXTI->PR & EXTI_PR_PR0) {
+        EXTI->PR |= EXTI_PR_PR0;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_0].cb(gpio_config[GPIO_IRQ_0].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#ifdef GPIO_IRQ_1
+void isr_exti1(void)
+{
+    if (EXTI->PR & EXTI_PR_PR1) {
+        EXTI->PR |= EXTI_PR_PR1;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_1].cb(gpio_config[GPIO_IRQ_1].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#ifdef GPIO_IRQ_2
+void isr_exti2(void)
+{
+    if (EXTI->PR & EXTI_PR_PR2) {
+        EXTI->PR |= EXTI_PR_PR2;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_2].cb(gpio_config[GPIO_IRQ_2].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#ifdef GPIO_IRQ_3
+void isr_exti3(void)
+{
+    if (EXTI->PR & EXTI_PR_PR3) {
+        EXTI->PR |= EXTI_PR_PR3;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_3].cb(gpio_config[GPIO_IRQ_3].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#ifdef GPIO_IRQ_4
+void isr_exti4(void)
+{
+    if (EXTI->PR & EXTI_PR_PR4) {
+        EXTI->PR |= EXTI_PR_PR4;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_4].cb(gpio_config[GPIO_IRQ_4].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#if defined(GPIO_IRQ_5) || defined(GPIO_IRQ_6) || defined(GPIO_IRQ_7) || defined(GPIO_IRQ_8) || defined(GPIO_IRQ_9)
+void isr_exti9_5(void)
+{
+    if (EXTI->PR & EXTI_PR_PR5) {
+        EXTI->PR |= EXTI_PR_PR5;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_5].cb(gpio_config[GPIO_IRQ_5].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR6) {
+        EXTI->PR |= EXTI_PR_PR6;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_6].cb(gpio_config[GPIO_IRQ_6].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR7) {
+        EXTI->PR |= EXTI_PR_PR7;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_7].cb(gpio_config[GPIO_IRQ_7].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR8) {
+        EXTI->PR |= EXTI_PR_PR8;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_8].cb(gpio_config[GPIO_IRQ_8].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR9) {
+        EXTI->PR |= EXTI_PR_PR9;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_9].cb(gpio_config[GPIO_IRQ_9].arg);
+    }
+    if (sched_context_switch_request) {
+        thread_yield();
+    }
+}
+#endif
+
+#if defined(GPIO_IRQ_10) || defined(GPIO_IRQ_11) || defined(GPIO_IRQ_12) || defined(GPIO_IRQ_13) || defined(GPIO_IRQ_14) || defined(GPIO_IRQ_15)
+void isr_exti15_10(void)
+{
+	if (EXTI->PR & EXTI_PR_PR10) {
+        EXTI->PR |= EXTI_PR_PR10;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_10].cb(gpio_config[GPIO_IRQ_10].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR11) {
+        EXTI->PR |= EXTI_PR_PR11;        /* clear status bit by writing a 1 to it */
+        gpio_config[GPIO_IRQ_11].cb(gpio_config[GPIO_IRQ_11].arg);
+    }
+    else if (EXTI->PR & EXTI_PR_PR12) {
+        EXTI->PR |= EXTI_PR_PR12;        /* clear status bit by writing a 1 to it */