Adding Support for Stellaris Launchpad LM4f120. This board is based on ARM Cortex M4 from TI.
Rakendra Thapa
8 years ago
parent
63cf9a3d4b
commit
0b673e66da
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# tell the Makefile.base which module to build
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MODULE = $(BOARD)_base
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include $(RIOTBASE)/Makefile.base
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FEATURES_PROVIDED += cpp
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#FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_MCU_GROUP = cortex_m4
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@ -0,0 +1,23 @@
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# define the cpu used by the ek-lm4f120xl board
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export CPU = lm4f120
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export CPU_MODEL = lm4f120
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#define the default port depending on the host OS
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
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# setup serial terminal
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include $(RIOTBOARD)/Makefile.include.serial
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# this board uses openocd
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include $(RIOTBOARD)/Makefile.include.openocd
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# include cortex defaults
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include $(RIOTBOARD)/Makefile.include.cortexm_common
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# define stellaris specific flags and includes
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export STELLARISWARE = $(RIOTCPU)/stellaris_common/include
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# define build specific options
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PART = LM4F120H5QR
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export CFLAGS += -I$(STELLARISWARE) -DPART_$(PART) -c -DTARGET_IS_BLIZZARD_RA1
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/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_ek-lm4f120xl
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* @{
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*
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* @file board.c
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* @brief Board specific implementations for the Stellaris Launchpad LM4F120 board
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*
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* @}
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*/
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#include "board.h"
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static void leds_init(void);
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void board_init(void)
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{
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/* initialize the boards LEDs, this is done for debugging purpose */
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leds_init();
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/* initialize the CPU */
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cpu_init();
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}
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/**
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* @brief initialize the boards on-boards LEDS.
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*/
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static void leds_init(void)
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{
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// enable clock for PORTF
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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//configure the pins as general output
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ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
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// Turn Red led on
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ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2);
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}
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File diff suppressed because it is too large
Load Diff
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source [find board/ek-lm4f120xl.cfg]
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/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup ek-lm4f120xl
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* @ingroup boards_ek-lm4f120xl
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* @brief Board specific files for the Stellaris Launchpad LM4F120 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the Stellaris Launchpad LM4F120 board
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*/
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#ifndef __BOARD_H
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#define __BOARD_H
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#include "cpu.h"
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#include "periph/uart.h"
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#include "periph/timer.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Define the boards stdio
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* @{
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*/
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#define STDIO UART_0
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#define STDIO_BAUDRATE 115200
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#define STDIO_RX_BUFSIZE UART0_BUFSIZE
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/** @} */
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/**
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* @name Assign the hardware timer
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*/
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#define HW_TIMER TIMER_0
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LED_GREEN_PIN 0x08
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#define LED_BLUE_PIN 0x04
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#define LED_RED_PIN 0x02
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#define LED_GREEN_ON GPIO_PORTF_DATA_R |= LED_GREEN_PIN
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#define LED_GREEN_OFF GPIO_PORTF_DATA_R &= ~(LED_GREEN_PIN)
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#define LED_GREEN_TOGGLE /* not available */
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#define LED_BLUE_ON GPIO_PORTF_DATA_R |= LED_BLUE_PIN
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#define LED_BLUE_OFF GPIO_PORTF_DATA_R &= ~(LED_BLUE_PIN)
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#define LED_BLUE_TOGGLE /* not available */
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#define LED_RED_ON GPIO_PORTF_DATA_R |= LED_RED_PIN
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#define LED_RED_OFF GPIO_PORTF_DATA_R &= ~(LED_RED_PIN)
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#define LED_RED_TOGGLE /* not available */
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/* @} */
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#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
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#define VAL_I(x) printf(#x ": %d\n",x);
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#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
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#define VAL_S(x) printf(#x ":%s\n", x);
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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extern void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /** __BOARD_H */
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/** @} */
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@ -0,0 +1,385 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_ek-lm4f120xl
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the ek-lm4f120xl board
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 0
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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//#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 2
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#define TIMER_0_PRESCALER (39U)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_ISR WTIMER0IntHandler
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#define TIMER_0_IRQ_CHAN Timer0A_IRQn
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/* Timer 1 configuration */
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#define TIMER_1_CHANNELS 2
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#define TIMER_1_PRESCALER (39U)
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_ISR TIMER1IntHandler
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#define TIMER_1_IRQ_CHAN Timer1A_IRQn
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/** @} */
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_1_EN 0
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#define UART_IRQ_PRIO 1
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#define UART_CLK ROM_SysCtlClockGet() /*RT clock runs with 40MHz */
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/* UART 0 device configuration */
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#define UART_0_DEV UART0_BASE
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#define UART_0_CLK (40000000) /* UART clock runs with 42MHz (F_CPU / 4) */
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#define UART_0_IRQ_CHAN UART0_IRQn
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#define UART_0_ISR UARTIntHandler
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN UART_PA1_U0TX
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#define UART_0_RX_PIN UART_PA0_U0RX
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV UART1_BASE
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#define UART_1_CLK (40000000) /* UART clock runs with 40MHz (F_CPU / 4) */
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#define UART_1_IRQ_CHAN UART1_IRQn
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#define UART_1_ISR UART1IntHandler
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOD
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#define UART_1_TX_PIN 8
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#define UART_1_RX_PIN 9
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#define UART_1_AF 7
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (2U)
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#define ADC_0_EN 1
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#define ADC_1_EN 1
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#define ADC_MAX_CHANNELS 2
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/** @} */
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/* ADC 0 configuration */
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#define ADC_0_DEV ADC0_BASE
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#define ADC_0_CHANNELS 2
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#define ADC_0_PORT GPIO_PORTE_BASE
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/* ADC 0 channel 0 pin config */
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#define ADC_0_CH0 1
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#define ADC_0_CH0_PIN GPIO_PIN_3
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/* ADC 0 channel 1 pin config */
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#define ADC_0_CH1 4
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#define ADC_0_CH1_PIN 4
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/* ADC 1 configuration */
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#define ADC_1_DEV ADC1_BASE
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#define ADC_1_CHANNELS 2
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#define ADC_1_PORT GPIO_PORTE_BASE
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#define ADC_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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/* ADC 1 channel 0 pin config */
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#define ADC_1_CH0 11
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#define ADC_1_CH0_PIN GPIO_PIN_2
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/* ADC 1 channel 1 pin config */
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#define ADC_1_CH1 12
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#define ADC_1_CH1_PIN 2
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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#define DAC_NUMOF (1U)
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#define DAC_0_EN 1
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#define DAC_MAX_CHANNELS 2
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/* DAC 0 configuration */
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#define DAC_0_DEV DAC
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#define DAC_0_CHANNELS 2
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#define DAC_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
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#define DAC_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
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#define DAC_0_PORT GPIOA
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#define DAC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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/* DAC 0 channel config */
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#define DAC_0_CH0_PIN 4
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#define DAC_0_CH1_PIN 5
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (2U)
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 4
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/* PWM 0 device configuration */
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#define PWM_0_DEV TIM1
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#define PWM_0_CHANNELS 4
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#define PWM_0_CLK (168000000U)
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#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM1EN)
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#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN)
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/* PWM 0 pin configuration */
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#define PWM_0_PORT GPIOE
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#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN)
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#define PWM_0_PIN_CH0 9
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#define PWM_0_PIN_CH1 11
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#define PWM_0_PIN_CH2 13
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#define PWM_0_PIN_CH3 14
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#define PWM_0_PIN_AF 1
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/* PWM 1 device configuration */
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#define PWM_1_DEV TIM3
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#define PWM_1_CHANNELS 3
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#define PWM_1_CLK (84000000U)
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#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
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#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN)
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/* PWM 1 pin configuration */
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#define PWM_1_PORT GPIOB
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#define PWM_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define PWM_1_PIN_CH0 4
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#define PWM_1_PIN_CH1 5
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#define PWM_1_PIN_CH2 0
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#define PWM_1_PIN_CH3 1
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#define PWM_1_PIN_AF 2
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define RANDOM_NUMOF (1U)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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/* SPI 1 device config */
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#define SPI_1_DEV SPI2
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#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
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#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
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#define SPI_1_BUS_DIV 0 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
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#define SPI_1_IRQ SPI2_IRQn
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#define SPI_1_IRQ_HANDLER isr_spi2
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/* SPI 1 pin configuration */
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#define SPI_1_SCK_PORT GPIOB
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#define SPI_1_SCK_PIN 13
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#define SPI_1_SCK_AF 5
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#define SPI_1_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define SPI_1_MISO_PORT GPIOB
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#define SPI_1_MISO_PIN 14
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#define SPI_1_MISO_AF 5
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#define SPI_1_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define SPI_1_MOSI_PORT GPIOB
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#define SPI_1_MOSI_PIN 15
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#define SPI_1_MOSI_AF 5
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#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (42000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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*/
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#define GPIO_NUMOF 12
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
|
||||
#define GPIO_4_EN 1
|
||||
#define GPIO_5_EN 1
|
||||
#define GPIO_6_EN 1
|
||||
#define GPIO_7_EN 1
|
||||
#define GPIO_8_EN 1
|
||||
#define GPIO_9_EN 1
|
||||
#define GPIO_10_EN 1
|
||||
#define GPIO_11_EN 1
|
||||
#define GPIO_IRQ_PRIO 1
|
||||
|
||||
/* IRQ config */
|
||||
#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_1 could be used here */
|
||||
#define GPIO_IRQ_1 GPIO_2
|
||||
#define GPIO_IRQ_2 GPIO_3
|
||||
#define GPIO_IRQ_3 GPIO_4
|
||||
#define GPIO_IRQ_4 GPIO_5
|
||||
#define GPIO_IRQ_5 GPIO_6
|
||||
#define GPIO_IRQ_6 GPIO_7
|
||||
#define GPIO_IRQ_7 GPIO_8
|
||||
#define GPIO_IRQ_8 GPIO_9
|
||||
#define GPIO_IRQ_9 GPIO_10
|
||||
#define GPIO_IRQ_10 GPIO_11
|
||||
#define GPIO_IRQ_11 -1/* not configured */
|
||||
#define GPIO_IRQ_12 -1/* not configured */
|
||||
#define GPIO_IRQ_13 -1/* not configured */
|
||||
#define GPIO_IRQ_14 -1/* not configured */
|
||||
#define GPIO_IRQ_15 -1/* not configured */
|
||||
|
||||
/* GPIO channel 0 config */
|
||||
#define GPIO_0_PORT GPIOA /* Used for user button 1 */
|
||||
#define GPIO_0_PIN 0
|
||||
#define GPIO_0_CLK 0 /* 0: PORT A, 1: B ... */
|
||||
#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
|
||||
#define GPIO_0_IRQ EXTI0_IRQn
|
||||
/* GPIO channel 1 config */
|
||||
#define GPIO_1_PORT GPIOE /* LIS302DL INT1 */
|
||||
#define GPIO_1_PIN 0
|
||||
#define GPIO_1_CLK 4
|
||||
#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE)
|
||||
#define GPIO_1_IRQ EXTI0_IRQn
|
||||
/* GPIO channel 2 config */
|
||||
#define GPIO_2_PORT GPIOE /* LIS302DL INT2 */
|
||||
#define GPIO_2_PIN 1
|
||||
#define GPIO_2_CLK 4
|
||||
#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE)
|
||||
#define GPIO_2_IRQ EXTI1_IRQn
|
||||
/* GPIO channel 3 config */
|
||||
#define GPIO_3_PORT GPIOE
|
||||
#define GPIO_3_PIN 2
|
||||
#define GPIO_3_CLK 4
|
||||
#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE)
|
||||
#define GPIO_3_IRQ EXTI2_IRQn
|
||||
/* GPIO channel 4 config */
|
||||
#define GPIO_4_PORT GPIOE /* LIS302DL CS */
|
||||
#define GPIO_4_PIN 3
|
||||
#define GPIO_4_CLK 4
|
||||
#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE)
|
||||
#define GPIO_4_IRQ EXTI3_IRQn
|
||||
/* GPIO channel 5 config */
|
||||
#define GPIO_5_PORT GPIOD /* CS43L22 RESET */
|
||||
#define GPIO_5_PIN 4
|
||||
#define GPIO_5_CLK 3
|
||||
#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PD)
|
||||
#define GPIO_5_IRQ EXTI4_IRQn
|
||||
/* GPIO channel 6 config */
|
||||
#define GPIO_6_PORT GPIOD /* LD8 */
|
||||
#define GPIO_6_PIN 5
|
||||
#define GPIO_6_CLK 3
|
||||
#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PD)
|
||||
#define GPIO_6_IRQ EXTI9_5_IRQn
|
||||
/* GPIO channel 7 config */
|
||||
#define GPIO_7_PORT GPIOD
|
||||
#define GPIO_7_PIN 6
|
||||
#define GPIO_7_CLK 3
|
||||
#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PD)
|
||||
#define GPIO_7_IRQ EXTI9_5_IRQn
|
||||
/* GPIO channel 8 config */
|
||||
#define GPIO_8_PORT GPIOD
|
||||
#define GPIO_8_PIN 7
|
||||
#define GPIO_8_CLK 3
|
||||
#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PD)
|
||||
#define GPIO_8_IRQ EXTI9_5_IRQn
|
||||
/* GPIO channel 9 config */
|
||||
#define GPIO_9_PORT GPIOA
|
||||
#define GPIO_9_PIN 8
|
||||
#define GPIO_9_CLK 0
|
||||
#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA)
|
||||
#define GPIO_9_IRQ EXTI9_5_IRQn
|
||||
/* GPIO channel 10 config */
|
||||
#define GPIO_10_PORT GPIOA /* LD7 */
|
||||
#define GPIO_10_PIN 9
|
||||
#define GPIO_10_CLK 0
|
||||
#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA)
|
||||
#define GPIO_10_IRQ EXTI9_5_IRQn
|
||||
/* GPIO channel 11 config */
|
||||
#define GPIO_11_PORT GPIOD
|
||||
#define GPIO_11_PIN 10
|
||||
#define GPIO_11_CLK 3
|
||||
#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PD)
|
||||
#define GPIO_11_IRQ EXTI15_10_IRQn
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,295 @@
|
||||
!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/
|
||||
!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/
|
||||
!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/
|
||||
!_TAG_PROGRAM_NAME Exuberant Ctags //
|
||||
!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/
|
||||
!_TAG_PROGRAM_VERSION 5.9~svn20110310 //
|
||||
ADC_0_CH0 include/periph_conf.h 119;" d
|
||||
ADC_0_CH0_PIN include/periph_conf.h 120;" d
|
||||
ADC_0_CH1 include/periph_conf.h 122;" d
|
||||
ADC_0_CH1_PIN include/periph_conf.h 123;" d
|
||||
ADC_0_CHANNELS include/periph_conf.h 113;" d
|
||||
ADC_0_CLKDIS include/periph_conf.h 115;" d
|
||||
ADC_0_CLKEN include/periph_conf.h 114;" d
|
||||
ADC_0_DEV include/periph_conf.h 112;" d
|
||||
ADC_0_EN include/periph_conf.h 107;" d
|
||||
ADC_0_PORT include/periph_conf.h 116;" d
|
||||
ADC_0_PORT_CLKEN include/periph_conf.h 117;" d
|
||||
ADC_1_CH0 include/periph_conf.h 134;" d
|
||||
ADC_1_CH0_PIN include/periph_conf.h 135;" d
|
||||
ADC_1_CH1 include/periph_conf.h 137;" d
|
||||
ADC_1_CH1_PIN include/periph_conf.h 138;" d
|
||||
ADC_1_CHANNELS include/periph_conf.h 127;" d
|
||||
ADC_1_CLKDIS include/periph_conf.h 129;" d
|
||||
ADC_1_CLKEN include/periph_conf.h 128;" d
|
||||
ADC_1_DEV include/periph_conf.h 126;" d
|
||||
ADC_1_EN include/periph_conf.h 108;" d
|
||||
ADC_1_PORT include/periph_conf.h 131;" d
|
||||
ADC_1_PORT_CLKEN include/periph_conf.h 132;" d
|
||||
ADC_MAX_CHANNELS include/periph_conf.h 109;" d
|
||||
ADC_NUMOF include/periph_conf.h 106;" d
|
||||
CLK16 include/board.h 39;" d
|
||||
CLK40 include/board.h 38;" d
|
||||
CLK50 include/board.h 37;" d
|
||||
CLK80 include/board.h 36;" d
|
||||
DAC_0_CH0_PIN include/periph_conf.h 159;" d
|
||||
DAC_0_CH1_PIN include/periph_conf.h 160;" d
|
||||
DAC_0_CHANNELS include/periph_conf.h 153;" d
|
||||
DAC_0_CLKDIS include/periph_conf.h 155;" d
|
||||
DAC_0_CLKEN include/periph_conf.h 154;" d
|
||||
DAC_0_DEV include/periph_conf.h 152;" d
|
||||
DAC_0_EN include/periph_conf.h 148;" d
|
||||
DAC_0_PORT include/periph_conf.h 156;" d
|
||||
DAC_0_PORT_CLKEN include/periph_conf.h 157;" d
|
||||
DAC_MAX_CHANNELS include/periph_conf.h 149;" d
|
||||
DAC_NUMOF include/periph_conf.h 147;" d
|
||||
F_CPU include/board.h 35;" d
|
||||
GPIO_0_CLK include/periph_conf.h 329;" d
|
||||
GPIO_0_EN include/periph_conf.h 294;" d
|
||||
GPIO_0_EXTI_CFG include/periph_conf.h 330;" d
|
||||
GPIO_0_IRQ include/periph_conf.h 331;" d
|
||||
GPIO_0_PIN include/periph_conf.h 328;" d
|
||||
GPIO_0_PORT include/periph_conf.h 327;" d
|
||||
GPIO_10_CLK include/periph_conf.h 389;" d
|
||||
GPIO_10_EN include/periph_conf.h 304;" d
|
||||
GPIO_10_EXTI_CFG include/periph_conf.h 390;" d
|
||||
GPIO_10_IRQ include/periph_conf.h 391;" d
|
||||
GPIO_10_PIN include/periph_conf.h 388;" d
|
||||
GPIO_10_PORT include/periph_conf.h 387;" d
|
||||
GPIO_11_CLK include/periph_conf.h 395;" d
|
||||
GPIO_11_EN include/periph_conf.h 305;" d
|
||||
GPIO_11_EXTI_CFG include/periph_conf.h 396;" d
|
||||
GPIO_11_IRQ include/periph_conf.h 397;" d
|
||||
GPIO_11_PIN include/periph_conf.h 394;" d
|
||||
GPIO_11_PORT include/periph_conf.h 393;" d
|
||||
GPIO_1_CLK include/periph_conf.h 335;" d
|
||||
GPIO_1_EN include/periph_conf.h 295;" d
|
||||
GPIO_1_EXTI_CFG include/periph_conf.h 336;" d
|
||||
GPIO_1_IRQ include/periph_conf.h 337;" d
|
||||
GPIO_1_PIN include/periph_conf.h 334;" d
|
||||
GPIO_1_PORT include/periph_conf.h 333;" d
|
||||
GPIO_2_CLK include/periph_conf.h 341;" d
|
||||
GPIO_2_EN include/periph_conf.h 296;" d
|
||||
GPIO_2_EXTI_CFG include/periph_conf.h 342;" d
|
||||
GPIO_2_IRQ include/periph_conf.h 343;" d
|
||||
GPIO_2_PIN include/periph_conf.h 340;" d
|
||||
GPIO_2_PORT include/periph_conf.h 339;" d
|
||||
GPIO_3_CLK include/periph_conf.h 347;" d
|
||||
GPIO_3_EN include/periph_conf.h 297;" d
|
||||
GPIO_3_EXTI_CFG include/periph_conf.h 348;" d
|
||||
GPIO_3_IRQ include/periph_conf.h 349;" d
|
||||
GPIO_3_PIN include/periph_conf.h 346;" d
|
||||
GPIO_3_PORT include/periph_conf.h 345;" d
|
||||
GPIO_4_CLK include/periph_conf.h 353;" d
|
||||
GPIO_4_EN include/periph_conf.h 298;" d
|
||||
GPIO_4_EXTI_CFG include/periph_conf.h 354;" d
|
||||
GPIO_4_IRQ include/periph_conf.h 355;" d
|
||||
GPIO_4_PIN include/periph_conf.h 352;" d
|
||||
GPIO_4_PORT include/periph_conf.h 351;" d
|
||||
GPIO_5_CLK include/periph_conf.h 359;" d
|
||||
GPIO_5_EN include/periph_conf.h 299;" d
|
||||
GPIO_5_EXTI_CFG include/periph_conf.h 360;" d
|
||||
GPIO_5_IRQ include/periph_conf.h 361;" d
|
||||
GPIO_5_PIN include/periph_conf.h 358;" d
|
||||
GPIO_5_PORT include/periph_conf.h 357;" d
|
||||
GPIO_6_CLK include/periph_conf.h 365;" d
|
||||
GPIO_6_EN include/periph_conf.h 300;" d
|
||||
GPIO_6_EXTI_CFG include/periph_conf.h 366;" d
|
||||
GPIO_6_IRQ include/periph_conf.h 367;" d
|
||||
GPIO_6_PIN include/periph_conf.h 364;" d
|
||||
GPIO_6_PORT include/periph_conf.h 363;" d
|
||||
GPIO_7_CLK include/periph_conf.h 371;" d
|
||||
GPIO_7_EN include/periph_conf.h 301;" d
|
||||
GPIO_7_EXTI_CFG include/periph_conf.h 372;" d
|
||||
GPIO_7_IRQ include/periph_conf.h 373;" d
|
||||
GPIO_7_PIN include/periph_conf.h 370;" d
|
||||
GPIO_7_PORT include/periph_conf.h 369;" d
|
||||
GPIO_8_CLK include/periph_conf.h 377;" d
|
||||
GPIO_8_EN include/periph_conf.h 302;" d
|
||||
GPIO_8_EXTI_CFG include/periph_conf.h 378;" d
|
||||
GPIO_8_IRQ include/periph_conf.h 379;" d
|
||||
GPIO_8_PIN include/periph_conf.h 376;" d
|
||||
GPIO_8_PORT include/periph_conf.h 375;" d
|
||||
GPIO_9_CLK include/periph_conf.h 383;" d
|
||||
GPIO_9_EN include/periph_conf.h 303;" d
|
||||
GPIO_9_EXTI_CFG include/periph_conf.h 384;" d
|
||||
GPIO_9_IRQ include/periph_conf.h 385;" d
|
||||
GPIO_9_PIN include/periph_conf.h 382;" d
|
||||
GPIO_9_PORT include/periph_conf.h 381;" d
|
||||
GPIO_IRQ_0 include/periph_conf.h 309;" d
|
||||
GPIO_IRQ_1 include/periph_conf.h 310;" d
|
||||
GPIO_IRQ_10 include/periph_conf.h 319;" d
|
||||
GPIO_IRQ_11 include/periph_conf.h 320;" d
|
||||
GPIO_IRQ_12 include/periph_conf.h 321;" d
|
||||
GPIO_IRQ_13 include/periph_conf.h 322;" d
|
||||
GPIO_IRQ_14 include/periph_conf.h 323;" d
|
||||
GPIO_IRQ_15 include/periph_conf.h 324;" d
|
||||
GPIO_IRQ_2 include/periph_conf.h 311;" d
|
||||
GPIO_IRQ_3 include/periph_conf.h 312;" d
|
||||
GPIO_IRQ_4 include/periph_conf.h 313;" d
|
||||
GPIO_IRQ_5 include/periph_conf.h 314;" d
|
||||
GPIO_IRQ_6 include/periph_conf.h 315;" d
|
||||
GPIO_IRQ_7 include/periph_conf.h 316;" d
|
||||
GPIO_IRQ_8 include/periph_conf.h 317;" d
|
||||
GPIO_IRQ_9 include/periph_conf.h 318;" d
|
||||
GPIO_IRQ_PRIO include/periph_conf.h 306;" d
|
||||
GPIO_NUMOF include/periph_conf.h 293;" d
|
||||
HW_TIMER include/board.h 53;" d
|
||||
I2C_0_CLKDIS include/periph_conf.h 273;" d
|
||||
I2C_0_CLKEN include/periph_conf.h 272;" d
|
||||
I2C_0_DEV include/periph_conf.h 271;" d
|
||||
I2C_0_EN include/periph_conf.h 266;" d
|
||||
I2C_0_ERR_IRQ include/periph_conf.h 276;" d
|
||||
I2C_0_ERR_ISR include/periph_conf.h 277;" d
|
||||
I2C_0_EVT_IRQ include/periph_conf.h 274;" d
|
||||
I2C_0_EVT_ISR include/periph_conf.h 275;" d
|
||||
I2C_0_SCL_AF include/periph_conf.h 281;" d
|
||||
I2C_0_SCL_CLKEN include/periph_conf.h 282;" d
|
||||
I2C_0_SCL_PIN include/periph_conf.h 280;" d
|
||||
I2C_0_SCL_PORT include/periph_conf.h 279;" d
|
||||
I2C_0_SDA_AF include/periph_conf.h 285;" d
|
||||
I2C_0_SDA_CLKEN include/periph_conf.h 286;" d
|
||||
I2C_0_SDA_PIN include/periph_conf.h 284;" d
|
||||
I2C_0_SDA_PORT include/periph_conf.h 283;" d
|
||||
I2C_APBCLK include/periph_conf.h 268;" d
|
||||
I2C_IRQ_PRIO include/periph_conf.h 267;" d
|
||||
I2C_NUMOF include/periph_conf.h 265;" d
|
||||
LED_BLUE_OFF include/board.h 68;" d
|
||||
LED_BLUE_ON include/board.h 67;" d
|
||||
LED_BLUE_PIN include/board.h 60;" d
|
||||
LED_BLUE_TOGGLE include/board.h 69;" d
|
||||
LED_GREEN_OFF include/board.h 64;" d
|
||||
LED_GREEN_ON include/board.h 63;" d
|
||||
LED_GREEN_PIN include/board.h 59;" d
|
||||
LED_GREEN_TOGGLE include/board.h 65;" d
|
||||
LED_RED_OFF include/board.h 72;" d
|
||||
LED_RED_ON include/board.h 71;" d
|
||||
LED_RED_PIN include/board.h 61;" d
|
||||
LED_RED_TOGGLE include/board.h 73;" d
|
||||
MODULE Makefile /^MODULE = $(BOARD)_base$/;" m
|
||||
PWM_0_CHANNELS include/periph_conf.h 173;" d
|
||||
PWM_0_CLK include/periph_conf.h 174;" d
|
||||
PWM_0_CLKDIS include/periph_conf.h 176;" d
|
||||
PWM_0_CLKEN include/periph_conf.h 175;" d
|
||||
PWM_0_DEV include/periph_conf.h 172;" d
|
||||
PWM_0_EN include/periph_conf.h 167;" d
|
||||
PWM_0_PIN_AF include/periph_conf.h 184;" d
|
||||
PWM_0_PIN_CH0 include/periph_conf.h 180;" d
|
||||
PWM_0_PIN_CH1 include/periph_conf.h 181;" d
|
||||
PWM_0_PIN_CH2 include/periph_conf.h 182;" d
|
||||
PWM_0_PIN_CH3 include/periph_conf.h 183;" d
|
||||
PWM_0_PORT include/periph_conf.h 178;" d
|
||||
PWM_0_PORT_CLKEN include/periph_conf.h 179;" d
|
||||
PWM_1_CHANNELS include/periph_conf.h 188;" d
|
||||
PWM_1_CLK include/periph_conf.h 189;" d
|
||||
PWM_1_CLKDIS include/periph_conf.h 191;" d
|
||||
PWM_1_CLKEN include/periph_conf.h 190;" d
|
||||
PWM_1_DEV include/periph_conf.h 187;" d
|
||||
PWM_1_EN include/periph_conf.h 168;" d
|
||||
PWM_1_PIN_AF include/periph_conf.h 199;" d
|
||||
PWM_1_PIN_CH0 include/periph_conf.h 195;" d
|
||||
PWM_1_PIN_CH1 include/periph_conf.h 196;" d
|
||||
PWM_1_PIN_CH2 include/periph_conf.h 197;" d
|
||||
PWM_1_PIN_CH3 include/periph_conf.h 198;" d
|
||||
PWM_1_PORT include/periph_conf.h 193;" d
|
||||
PWM_1_PORT_CLKEN include/periph_conf.h 194;" d
|
||||
PWM_MAX_CHANNELS include/periph_conf.h 169;" d
|
||||
PWM_NUMOF include/periph_conf.h 166;" d
|
||||
RANDOM_NUMOF include/periph_conf.h 206;" d
|
||||
SPI_0_BUS_DIV include/periph_conf.h 222;" d
|
||||
SPI_0_CLKDIS include/periph_conf.h 221;" d
|
||||
SPI_0_CLKEN include/periph_conf.h 220;" d
|
||||
SPI_0_DEV include/periph_conf.h 219;" d
|
||||
SPI_0_EN include/periph_conf.h 214;" d
|
||||
SPI_0_IRQ include/periph_conf.h 223;" d
|
||||
SPI_0_IRQ_HANDLER include/periph_conf.h 224;" d
|
||||
SPI_0_MISO_AF include/periph_conf.h 232;" d
|
||||
SPI_0_MISO_PIN include/periph_conf.h 231;" d
|
||||
SPI_0_MISO_PORT include/periph_conf.h 230;" d
|
||||
SPI_0_MISO_PORT_CLKEN include/periph_conf.h 233;" d
|
||||
SPI_0_MOSI_AF include/periph_conf.h 236;" d
|
||||
SPI_0_MOSI_PIN include/periph_conf.h 235;" d
|
||||
SPI_0_MOSI_PORT include/periph_conf.h 234;" d
|
||||
SPI_0_MOSI_PORT_CLKEN include/periph_conf.h 237;" d
|
||||
SPI_0_SCK_AF include/periph_conf.h 228;" d
|
||||
SPI_0_SCK_PIN include/periph_conf.h 227;" d
|
||||
SPI_0_SCK_PORT include/periph_conf.h 226;" d
|
||||
SPI_0_SCK_PORT_CLKEN include/periph_conf.h 229;" d
|
||||
SPI_1_BUS_DIV include/periph_conf.h 243;" d
|
||||
SPI_1_CLKDIS include/periph_conf.h 242;" d
|
||||
SPI_1_CLKEN include/periph_conf.h 241;" d
|
||||
SPI_1_DEV include/periph_conf.h 240;" d
|
||||
SPI_1_EN include/periph_conf.h 215;" d
|
||||
SPI_1_IRQ include/periph_conf.h 244;" d
|
||||
SPI_1_IRQ_HANDLER include/periph_conf.h 245;" d
|
||||
SPI_1_MISO_AF include/periph_conf.h 253;" d
|
||||
SPI_1_MISO_PIN include/periph_conf.h 252;" d
|
||||
SPI_1_MISO_PORT include/periph_conf.h 251;" d
|
||||
SPI_1_MISO_PORT_CLKEN include/periph_conf.h 254;" d
|
||||
SPI_1_MOSI_AF include/periph_conf.h 257;" d
|
||||
SPI_1_MOSI_PIN include/periph_conf.h 256;" d
|
||||
SPI_1_MOSI_PORT include/periph_conf.h 255;" d
|
||||
SPI_1_MOSI_PORT_CLKEN include/periph_conf.h 258;" d
|
||||
SPI_1_SCK_AF include/periph_conf.h 249;" d
|
||||
SPI_1_SCK_PIN include/periph_conf.h 248;" d
|
||||
SPI_1_SCK_PORT include/periph_conf.h 247;" d
|
||||
SPI_1_SCK_PORT_CLKEN include/periph_conf.h 250;" d
|
||||
SPI_IRQ_PRIO include/periph_conf.h 216;" d
|
||||
SPI_NUMOF include/periph_conf.h 213;" d
|
||||
STDIO include/board.h 45;" d
|
||||
STDIO_BAUDRATE include/board.h 46;" d
|
||||
STDIO_RX_BUFSIZE include/board.h 47;" d
|
||||
SetupClock board.c /^void SetupClock(int clk)$/;" f
|
||||
SetupFPU board.c /^void SetupFPU(void)$/;" f
|
||||
TIMER_0_CHANNELS include/periph_conf.h 43;" d
|
||||
TIMER_0_CLKEN include/periph_conf.h 46;" d
|
||||
TIMER_0_DEV include/periph_conf.h 42;" d
|
||||
TIMER_0_EN include/periph_conf.h 37;" d
|
||||
TIMER_0_IRQ_CHAN include/periph_conf.h 48;" d
|
||||
TIMER_0_ISR include/periph_conf.h 47;" d
|
||||
TIMER_0_MAX_VALUE include/periph_conf.h 45;" d
|
||||
TIMER_0_PRESCALER include/periph_conf.h 44;" d
|
||||
TIMER_1_CHANNELS include/periph_conf.h 52;" d
|
||||
TIMER_1_CLKEN include/periph_conf.h 55;" d
|
||||
TIMER_1_DEV include/periph_conf.h 51;" d
|
||||
TIMER_1_EN include/periph_conf.h 38;" d
|
||||
TIMER_1_IRQ_CHAN include/periph_conf.h 57;" d
|
||||
TIMER_1_ISR include/periph_conf.h 56;" d
|
||||
TIMER_1_MAX_VALUE include/periph_conf.h 54;" d
|
||||
TIMER_1_PRESCALER include/periph_conf.h 53;" d
|
||||
TIMER_IRQ_PRIO include/periph_conf.h 39;" d
|
||||
TIMER_NUMOF include/periph_conf.h 36;" d
|
||||
TRACE include/board.h 75;" d
|
||||
UART_0_AF include/periph_conf.h 83;" d
|
||||
UART_0_CLK include/periph_conf.h 75;" d
|
||||
UART_0_CLKDIS include/periph_conf.h 74;" d
|
||||
UART_0_CLKEN include/periph_conf.h 73;" d
|
||||
UART_0_DEV include/periph_conf.h 72;" d
|
||||
UART_0_EN include/periph_conf.h 67;" d
|
||||
UART_0_IRQ_CHAN include/periph_conf.h 76;" d
|
||||
UART_0_ISR include/periph_conf.h 77;" d
|
||||
UART_0_PORT include/periph_conf.h 80;" d
|
||||
UART_0_PORT_CLKEN include/periph_conf.h 79;" d
|
||||
UART_0_RX_PIN include/periph_conf.h 82;" d
|
||||
UART_0_TX_PIN include/periph_conf.h 81;" d
|
||||
UART_1_AF include/periph_conf.h 99;" d
|
||||
UART_1_CLK include/periph_conf.h 91;" d
|
||||
UART_1_CLKDIS include/periph_conf.h 90;" d
|
||||
UART_1_CLKEN include/periph_conf.h 89;" d
|
||||
UART_1_DEV include/periph_conf.h 88;" d
|
||||
UART_1_EN include/periph_conf.h 68;" d
|
||||
UART_1_IRQ_CHAN include/periph_conf.h 92;" d
|
||||
UART_1_ISR include/periph_conf.h 93;" d
|
||||
UART_1_PORT include/periph_conf.h 96;" d
|
||||
UART_1_PORT_CLKEN include/periph_conf.h 95;" d
|
||||
UART_1_RX_PIN include/periph_conf.h 98;" d
|
||||
UART_1_TX_PIN include/periph_conf.h 97;" d
|
||||
UART_CLK include/periph_conf.h 70;" d
|
||||
UART_IRQ_PRIO include/periph_conf.h 69;" d
|
||||
UART_NUMOF include/periph_conf.h 66;" d
|
||||
VAL_I include/board.h 76;" d
|
||||
VAL_S include/board.h 78;" d
|
||||
VAL_X include/board.h 77;" d
|
||||
__BOARD_H include/board.h 22;" d
|
||||
__PERIPH_CONF_H include/periph_conf.h 20;" d
|
||||
board_init board.c /^void board_init(void)$/;" f
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,7 @@
|
||||
# define the module that is build
|
||||
MODULE = cpu
|
||||
|
||||
# add a list of subdirectories, that should also be build
|
||||
DIRS = periph $(RIOTCPU)/cortexm_common
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
@ -0,0 +1,6 @@
|
||||
export CPU_ARCH = cortex-m4f
|
||||
|
||||
# use hwtimer compatibility module
|
||||
USEMODULE += hwtimer_compat
|
||||
|
||||
include $(RIOTCPU)/Makefile.include.cortexm_common
|
||||
@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lm4f120
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of the CPU initialization
|
||||
*
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "irq.h"
|
||||
#include "kernel.h"
|
||||
#include "kernel_internal.h"
|
||||
#include "sched.h"
|
||||
#include "thread.h"
|
||||
#include "arch/thread_arch.h"
|
||||
#include "arch/irq_arch.h"
|
||||
|
||||
unsigned long __attribute__((naked))
|
||||
CPUipsrGet(void)
|
||||
{
|
||||
unsigned long ulRet;
|
||||
|
||||
//
|
||||
// Read IPSR
|
||||
//
|
||||
__asm(" mrs r0, IPSR\n"
|
||||
" bx lr\n"
|
||||
: "=r" (ulRet));
|
||||
|
||||
//
|
||||
// The return is handled in the inline assembly, but the compiler will
|
||||
// still complain if there is not an explicit return here (despite the fact
|
||||
// that this does not result in any code being produced because of the
|
||||
// naked attribute).
|
||||
//
|
||||
return(ulRet);
|
||||
}
|
||||
|
||||
void __attribute__((naked))
|
||||
DisableInterrupts(void)
|
||||
{
|
||||
__asm(" CPSID I\n"
|
||||
" BX LR\n");
|
||||
}
|
||||
|
||||
void __attribute__((naked))
|
||||
EnableInterrupts(void)
|
||||
{
|
||||
__asm(" CPSIE I\n"
|
||||
" BX LR\n");
|
||||
}
|
||||
/**
|
||||
* @brief Initialize the CPU, set IRQ priorities
|
||||
*/
|
||||
void cpu_init(void)
|
||||
{
|
||||
// initializes the Cortex-M core
|
||||
cortexm_init();
|
||||
|
||||
/* initialize the clock system */
|
||||
cpu_clock_init(CLK40);
|
||||
}
|
||||
|
||||
void setup_fpu(void)
|
||||
{
|
||||
ROM_FPUEnable();
|
||||
ROM_FPULazyStackingEnable();
|
||||
}
|
||||
|
||||
void cpu_clock_init(int clk)
|
||||
{
|
||||
setup_fpu();
|
||||
switch(clk){
|
||||
case CLK80:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
case CLK50:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
case CLK40:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
case CLK16:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
case CLK1:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_1MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
default:
|
||||
ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup cpu_lm4f120
|
||||
* @ingroup cpu
|
||||
* @brief CPU specific implementations for the Stellaris Launchpad LM4F120 board
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific hwtimer configuration options
|
||||
*12
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __CPU_CONF_H
|
||||
#define __CPU_CONF_H
|
||||
|
||||
#include "hw_ints.h"
|
||||
#include "hw_memmap.h"
|
||||
#include "hw_nvic.h"
|
||||
#include "hw_sysctl.h"
|
||||
#include "hw_types.h"
|
||||
#include "lm4f120h5qr.h"
|
||||
#include "cortex-m4-def.h"
|
||||
#include "stellaris_periph/cpu.h"
|
||||
#include "stellaris_periph/debug.h"
|
||||
#include "stellaris_periph/interrupt.h"
|
||||
#include "stellaris_periph/sysctl.h"
|
||||
#include "stellaris_periph/adc.h"
|
||||
#include "stellaris_periph/gpio.h"
|
||||
#include "stellaris_periph/timer.h"
|
||||
#include "stellaris_periph/pin_map.h"
|
||||
#include "stellaris_periph/uart.h"
|
||||
#include "stellaris_periph/fpu.h"
|
||||
#include "stellaris_periph/rom.h"
|
||||
#include "hwtimer_cpu.h"
|
||||
#include "periph/uart.h"
|
||||
#include "stdio.h"
|
||||
#include "stdlib.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ARM Cortex-M specific CPU configuration
|
||||
* @{
|
||||
*/
|
||||
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
||||
#define CPU_IRQ_NUMOF (48U)
|
||||
#define CPU_FLASH_BASE FLASH_BASE
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Length for reading CPU_ID
|
||||
*/
|
||||
#define CPUID_ID_LEN (12)
|
||||
#define CPUID_ADDR NVIC_CPUID
|
||||
|
||||
/**
|
||||
* @name CC110X buffer size definitions for the stm32f4
|
||||
* @{
|
||||
*/
|
||||
#ifdef MODULE_CC110X
|
||||
#define TRANSCEIVER_BUFFER_SIZE (10)
|
||||
#define RX_BUF_SIZE (10)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Define the nominal CPU core clock in this board
|
||||
*/
|
||||
#define F_CPU 1000000
|
||||
#define CLK80 1
|
||||
#define CLK50 2
|
||||
#define CLK40 3
|
||||
#define CLK16 4
|
||||
#define CLK1 5
|
||||
|
||||
|
||||
extern unsigned long CPUipsrGet(void);
|
||||
extern void DisableInterrupts(void);
|
||||
extern void EnableInterrupts(void);
|
||||
extern void setup_fpu(void);
|
||||
extern void cpu_clock_init(int);
|
||||
extern int uart_init_testing(uart_t uart, uint32_t baudrate);
|
||||
extern void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CPU_CONF_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lm4f120
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific hwtimer configuration options
|
||||
*
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __HWTIMER_CPU_H
|
||||
#define __HWTIMER_CPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Hardware timer configuration
|
||||
* @{
|
||||
*/
|
||||
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
|
||||
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
|
||||
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
|
||||
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
|
||||
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HWTIMER_CPU_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,150 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm4.h
|
||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
|
||||
* @version V4.00
|
||||
* @date 22. August 2014
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __LM4F120H5QR_H__
|
||||
#define __LM4F120H5QR_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< LM4F120H5QR provides an MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< LM4F120H5QR uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup cpu_specific_Peripheral_interrupt_number_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LM4F120H5QR Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
|
||||
/****** LM4F specific Interrupt Numbers **********************************************************************/
|
||||
GPIOPortA_IRQn = 0,
|
||||
GPIOPortB_IRQn = 1,
|
||||
GPIOPortC_IRQn = 2,
|
||||
GPIOPortD_IRQn = 3,
|
||||
GPIOPortE_IRQn = 4,
|
||||
UART0_IRQn = 5,
|
||||
UART1_IRQn = 6,
|
||||
SSI0_IRQn = 7,
|
||||
I2C0_IRQn = 8,
|
||||
PWMFault_IRQn = 9,
|
||||
PWM0_IRQn = 10,
|
||||
PWM1_IRQn = 11,
|
||||
PWM2_IRQn = 12,
|
||||
Quadrature0_IRQn = 13,
|
||||
ADC0_IRQn = 14,
|
||||
ADC1_IRQn = 15,
|
||||
ADC2_IRQn = 16,
|
||||
ADC3_IRQn = 17,
|
||||
WDT_IRQn = 18,
|
||||
Timer0A_IRQn = 19,
|
||||
Timer0B_IRQn = 20,
|
||||
Timer1A_IRQn = 21,
|
||||
Timer1B_IRQn = 22,
|
||||
Timer2A_IRQn = 23,
|
||||
Timer2B_IRQn = 24,
|
||||
Comp0_IRQn = 25,
|
||||
Comp1_IRQn = 26,
|
||||
Comp2_IRQn = 27,
|
||||
SysCtl_IRQn = 28,
|
||||
FlashCtl_IRQn = 29,
|
||||
GPIOPortF_IRQn = 30,
|
||||
GPIOPortG_IRQn = 31,
|
||||
GPIOPortH_IRQn = 32,
|
||||
UART2_IRQn = 33,
|
||||
SSI1_IRQn = 34,
|
||||
Timer3A_IRQn = 35,
|
||||
Timer3B_IRQn = 36,
|
||||
I2C1_IRQn = 37,
|
||||
Quadrature1_IRQn = 38,
|
||||
CAN0_IRQn = 39,
|
||||
CAN1_IRQn = 40,
|
||||
CAN2_IRQn = 41,
|
||||
Ethernet_IRQn = 42,
|
||||
Hibernate_IRQn = 43,
|
||||
USB0_IRQn = 44,
|
||||
PWM3_IRQn = 45,
|
||||
uDMA_IRQn = 46,
|
||||
uDMA_Error_IRQn = 47,
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*
|
||||
typedef enum
|
||||
{
|
||||
// ****** Cortex-M4 Processor Exceptions Numbers ****************************************************************
|
||||
NonMaskableInt_IRQn = 2, //!< 2 Non Maskable Interrupt
|
||||
MemoryManagement_IRQn = 4, //!< 4 Cortex-M4 Memory Management Interrupt
|
||||
BusFault_IRQn = 5, //!< 5 Cortex-M4 Bus Fault Interrupt
|
||||
UsageFault_IRQn = 6, //!< 6 Cortex-M4 Usage Fault Interrupt
|
||||
SVCall_IRQn = 11, //!< 11 Cortex-M4 SV Call Interrupt
|
||||
DebugMonitor_IRQn = 12, //!< 12 Cortex-M4 Debug Monitor Interrupt
|
||||
PendSV_IRQn = 14, //!< 14 Cortex-M4 Pend SV Interrupt
|
||||
SysTick_IRQn = 15, //!< 15 Cortex-M4 System Tick Interrupt
|
||||
} IRQn_Type;
|
||||
*/
|
||||
|
||||
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
|
||||
#include <stdint.h> /* standard types definitions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM4_H_GENERIC */
|
||||
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lm4f120
|
||||
* @{
|
||||
*
|
||||
* @file lm4f120_linkerscript.ld
|
||||
* @brief Linker description file for LM4FXXX microcontrollers.
|
||||
*
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lm4f120
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of the kernels power management interface
|
||||
*
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "arch/lpm_arch.h"
|
||||
|
||||
void lpm_arch_init(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
enum lpm_mode lpm_arch_set(enum lpm_mode target)
|
||||
{
|
||||
/* TODO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
enum lpm_mode lpm_arch_get(void)
|
||||
{
|
||||
/* TODO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
void lpm_arch_awake(void)
|
||||
{
|
||||
/* TODO*/
|
||||
}
|
||||
|
||||
void lpm_arch_begin_awake(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void lpm_arch_end_awake(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
@ -0,0 +1,3 @@
|
||||
MODULE = periph
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
@ -0,0 +1,221 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lm4f120
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Low-level ADC driver implementation
|
||||
*
|
||||
* @author Rakendra Thapa <rakendrathapa@gmail.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "periph/adc.h"
|
||||
#include "periph_conf.h"
|
||||
|
||||
/* guard in case that no ADC device is defined */
|
||||
#if ADC_NUMOF
|
||||
|
||||
typedef struct {
|
||||
int max_value;
|
||||
} adc_config_t;
|
||||
|
||||
adc_config_t adc_config[ADC_NUMOF];
|
||||
|
||||
int adc_init(adc_t dev, adc_precision_t precision)
|
||||
{
|
||||
adc_poweron(dev);
|
||||
// ADC0 is used with AIN0 on port E3.
|
||||
// ADC1 is used with AIN1 on port E2.
|
||||
// GPIO port E needs to be enabled so that these pinds can be used
|
||||
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
|
||||
|
||||
// Set the ADC to 125KSPS.
|
||||
// This requires less power and produce longer samping time,
|
||||
// creating accurate conversions
|
||||
ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS);
|
||||
|
||||
switch (precision) {
|
||||
case ADC_RES_6BIT:
|
||||
case ADC_RES_8BIT:
|
||||
case ADC_RES_10BIT:
|
||||
#if ADC_0_EN
|
||||
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S);
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S);
|
||||
#endif
|
||||
adc_config[dev].max_value = 0x3ff;
|
||||
break;
|
||||
case ADC_RES_12BIT:
|
||||
#if ADC_0_EN
|
||||
ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S);
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S);
|
||||
#endif
|
||||
adc_config[dev].max_value = 0xfff;
|
||||
break;
|
||||
case ADC_RES_14BIT:
|
||||
case ADC_RES_16BIT:
|
||||
break;
|
||||
}
|
||||
switch (dev) {
|
||||
#if ADC_0_EN
|
||||
case ADC_0:
|
||||
// Select the Analog ADC Function for these pins.
|
||||
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
|
||||
|
||||
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
|
||||
ROM_ADCSequenceDisable(ADC0_BASE, 3);
|
||||
|
||||
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
|
||||
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
|
||||
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
|
||||
ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
|
||||
|
||||
// Configure step 0 on sequence 3.
|
||||
// Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag.
|
||||
// (ADC_CTL_IE) to be set to enable Interrupt.
|
||||
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
|
||||
ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END);
|
||||
|
||||
// Clear the interrupt status flag. This is done to make sure
|
||||
// the interrupt flag is cleared before we sample.
|
||||
ROM_ADCIntClear(ADC0_BASE, 3);
|
||||
|
||||
// Since sample sequence 3 is now configured, it must be enabled.
|
||||
ROM_ADCSequenceEnable(ADC0_BASE, 3);
|
||||
|
||||
break;
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
case ADC_1:
|
||||
// Select the Analog ADC Function for these pins.
|
||||
ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
|
||||
|
||||
// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
|
||||
ROM_ADCSequenceDisable(ADC1_BASE, 3);
|
||||
|
||||
// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
|
||||
// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
|
||||
// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
|
||||
ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
|
||||
|
||||
// Configure step 0 on sequence 3.
|
||||
// Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag.
|
||||
// (ADC_CTL_IE) to be set to enable Interrupt.
|
||||
ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0,
|
||||
ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END);
|
||||
|
||||
// Clear the interrupt status flag. This is done to make sure
|
||||
// the interrupt flag is cleared before we sample.
|
||||
ROM_ADCIntClear(ADC1_BASE, 3);
|
||||
|
||||
// Since sample sequence 3 is now configured, it must be enabled.
|
||||
ROM_ADCSequenceEnable(ADC1_BASE, 3);
|
||||
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int adc_sample(adc_t dev, int channel)
|
||||
{
|
||||
unsigned long ulADC_val=0;
|
||||
|
||||
switch (dev) {
|
||||
#if ADC_0_EN
|
||||
case ADC_0:
|
||||
// Trigger the ADC conversion
|
||||
ROM_ADCProcessorTrigger(ADC0_BASE, 3);
|
||||
|
||||
// Wait for conversion to be completed.
|
||||
while(!ROM_ADCIntStatus(ADC0_BASE, 3, false));
|
||||
|
||||
// Read ADC value.
|
||||
ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val);
|
||||
|
||||
// Clear the ADC interrupt flag
|
||||
ROM_ADCIntClear(ADC0_BASE, 3);
|
||||
break;
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
case ADC_1:
|
||||
// Trigger the ADC conversion
|
||||
ROM_ADCProcessorTrigger(ADC1_BASE, 3);
|
||||
|
||||
// Wait for conversion to be completed.
|
||||
while(!ROM_ADCIntStatus(ADC1_BASE, 3, false));
|
||||
|
||||
// Read ADC value.
|
||||
ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val);
|
||||
|
||||
// Clear the ADC interrupt flag
|
||||
ROM_ADCIntClear(ADC1_BASE, 3);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* return result */
|
||||
return ((int)ulADC_val);
|
||||
}
|
||||
|
||||
void adc_poweron(adc_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if ADC_0_EN
|
||||
case ADC_0:
|
||||
// The ADC0 Peripheral must be enabled for use
|
||||
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
|
||||
break;
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
case ADC_1:
|
||||
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void adc_poweroff(adc_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if ADC_0_EN
|
||||
case ADC_0:
|
||||
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
|
||||
break;
|
||||
#endif
|
||||
#if ADC_1_EN
|
||||
case ADC_1:
|
||||
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
int adc_map(adc_t dev, int value, int min, int max)
|
||||
{
|
||||
return (int)adc_mapf(dev, value, (float)min, (float)max);
|
||||
}
|
||||
|
||||
float adc_mapf(adc_t dev, int value, float min, float max)
|
||||
{
|
||||
return ((max - min) / ((float)adc_config[dev].max_value)) * value;
|
||||
}
|
||||
|
||||
#endif /* ADC_NUMOF */
|
||||
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup driver_periph
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
| < | ||||