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at86rf231 TX and RX driver is using vtimer instead of hwtimer_ functions, TO CHECK vtimer debug function prototype fixdev/timer
Alaeddine WESLATI
10 years ago
15 changed files with 855 additions and 8 deletions
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INCLUDES = -I$(RIOTBASE)/sys/include -I$(RIOTBASE)/sys/net -I$(RIOTBASE)/core/include -Iinclude/ -I$(RIOTBASE)/sys/net/ieee802154/
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MODULE =at86rf231
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DIRS =
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all: $(BINDIR)$(MODULE).a |
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@for i in $(DIRS) ; do $(MAKE) -C $$i ; done ;
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include $(RIOTBASE)/Makefile.base |
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clean:: |
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@for i in $(DIRS) ; do $(MAKE) -C $$i clean ; done ;
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/**
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* at86rf231.c - Implementation of at86rf231 functions. |
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* Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr> |
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* |
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* This source code is licensed under the GNU Lesser General Public License, |
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* Version 2. See the file LICENSE for more details. |
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*/ |
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#include <at86rf231.h> |
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//#define ENABLE_DEBUG
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#include <debug.h> |
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static uint16_t radio_pan; |
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static uint8_t radio_channel; |
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static uint16_t radio_address; |
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static uint64_t radio_address_long; |
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int transceiver_pid; |
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void at86rf231_init(int tpid) |
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{ |
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transceiver_pid = tpid; |
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at86rf231_gpio_spi_interrupts_init(); |
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at86rf231_reset(); |
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// TODO : Enable addr decode, auto ack, auto crc
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// and configure security, power, channel, pan
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at86rf231_switch_to_rx(); |
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} |
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void at86rf231_switch_to_rx(void) |
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{ |
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at86rf231_disable_interrupts(); |
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// Send a FORCE TRX OFF command
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at86rf231_reg_write(AT86RF231_REG__TRX_STATE, AT86RF231_TRX_STATE__FORCE_TRX_OFF); |
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// Reset IRQ to TRX END only
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at86rf231_reg_write(AT86RF231_REG__IRQ_MASK, AT86RF231_IRQ_STATUS_MASK__TRX_END); |
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// Read IRQ to clear it
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at86rf231_reg_read(AT86RF231_REG__IRQ_STATUS); |
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// Enable IRQ interrupt
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at86rf231_enable_interrupts(); |
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// Start RX
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at86rf231_reg_write(AT86RF231_REG__TRX_STATE, AT86RF231_TRX_STATE__RX_ON); |
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// wait until it is on RX_ON state
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uint8_t status; |
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uint8_t max_wait = 100; // TODO : move elsewhere, this is in 10us
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do |
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{ |
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status = at86rf231_get_status(); |
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vtimer_usleep(10); |
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if (!--max_wait) |
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{ |
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printf("at86rf231 : ERROR : could not enter RX_ON mode"); |
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break; |
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} |
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}
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while ((status & AT86RF231_TRX_STATUS_MASK__TRX_STATUS) != AT86RF231_TRX_STATUS__RX_ON); |
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} |
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void at86rf231_rx_irq(void) |
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{ |
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at86rf231_rx_handler(); |
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} |
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uint16_t at86rf231_set_address(uint16_t address) |
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{ |
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radio_address = address; |
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at86rf231_reg_write(AT86RF231_REG__SHORT_ADDR_0, (uint8_t)(0x0F & radio_address)); |
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at86rf231_reg_write(AT86RF231_REG__SHORT_ADDR_1, (uint8_t)(radio_address >> 8)); |
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return radio_address; |
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} |
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uint16_t at86rf231_get_address(void) |
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{ |
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return radio_address; |
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} |
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uint64_t at86rf231_set_address_long(uint64_t address) |
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{ |
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radio_address_long = address; |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_0, (uint8_t)(0x0F & radio_address)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_1, (uint8_t)(radio_address >> 8)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_2, (uint8_t)(radio_address >> 16)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_3, (uint8_t)(radio_address >> 24)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_4, (uint8_t)(radio_address >> 32)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_5, (uint8_t)(radio_address >> 40)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_6, (uint8_t)(radio_address >> 48)); |
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at86rf231_reg_write(AT86RF231_REG__IEEE_ADDR_7, (uint8_t)(radio_address >> 56)); |
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return radio_address_long; |
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} |
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uint64_t at86rf231_get_address_long(void) |
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{ |
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return radio_address_long; |
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} |
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uint16_t at86rf231_set_pan(uint16_t pan) |
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{ |
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radio_pan = pan; |
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at86rf231_reg_write(AT86RF231_REG__PAN_ID_0, (uint8_t)(0x0F & radio_pan)); |
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at86rf231_reg_write(AT86RF231_REG__PAN_ID_1, (uint8_t)(radio_pan >> 8)); |
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return radio_pan; |
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} |
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uint16_t at86rf231_get_pan(void) |
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{ |
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return radio_pan; |
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} |
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uint8_t at86rf231_set_channel(uint8_t channel) |
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{ |
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radio_channel = channel; |
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if (channel < RF86RF231_MIN_CHANNEL || |
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channel > RF86RF231_MAX_CHANNEL) { |
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radio_channel = RF86RF231_MAX_CHANNEL; |
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} |
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at86rf231_reg_write(AT86RF231_REG__PHY_CC_CCA, AT86RF231_PHY_CC_CCA_DEFAULT__CCA_MODE | radio_channel); |
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return radio_channel; |
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} |
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uint8_t at86rf231_get_channel(void) |
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{
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return radio_channel; |
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//return at86rf231_reg_read(AT86RF231_REG__PHY_CC_CCA) & 0x0F;
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} |
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void at86rf231_set_monitor(uint8_t mode) |
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{ |
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// TODO
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} |
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void at86rf231_swap_fcf_bytes(uint8_t *buf) |
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{ |
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uint8_t tmp; |
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tmp = buf[1]; |
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buf[1] = buf[2]; |
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buf[2] = tmp; |
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} |
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#include <at86rf231.h> |
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#include <at86rf231_arch.h> |
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#include <transceiver.h> |
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#include <msg.h> |
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//#define ENABLE_DEBUG
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#include <debug.h> |
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at86rf231_packet_t at86rf231_rx_buffer[AT86RF231_RX_BUF_SIZE]; |
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uint8_t buffer[AT86RF231_RX_BUF_SIZE][AT86RF231_MAX_PKT_LENGTH]; |
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volatile uint8_t rx_buffer_next; |
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void at86rf231_rx_handler(void) |
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{ |
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uint8_t lqi, fcs_rssi; |
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// read packet length
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at86rf231_read_fifo(&at86rf231_rx_buffer[rx_buffer_next].length, 1); |
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// read psdu, read packet with length as first byte and lqi as last byte.
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uint8_t *buf = buffer[rx_buffer_next]; |
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at86rf231_read_fifo(buf, at86rf231_rx_buffer[rx_buffer_next].length); |
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at86rf231_swap_fcf_bytes(buf); |
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// read lqi which is appended after the psdu
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lqi = buf[at86rf231_rx_buffer[rx_buffer_next].length-1]; |
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// read fcs and rssi, from a register
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fcs_rssi = at86rf231_reg_read(AT86RF231_REG__PHY_RSSI); |
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// build package
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at86rf231_rx_buffer[rx_buffer_next].lqi = lqi; |
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// RSSI has no meaning here, it should be read during packet reception.
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at86rf231_rx_buffer[rx_buffer_next].rssi = fcs_rssi & 0x0F; // bit[4:0]
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// bit7, boolean, 1 FCS valid, 0 FCS not valid
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at86rf231_rx_buffer[rx_buffer_next].crc = (fcs_rssi >> 7) & 0x01; |
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if(at86rf231_rx_buffer[rx_buffer_next].crc == 0) { |
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DEBUG("Got packet with invalid crc.\n"); |
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return; |
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} |
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read_802154_frame(&buf[1], &at86rf231_rx_buffer[rx_buffer_next].frame, |
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at86rf231_rx_buffer[rx_buffer_next].length-2); |
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if(at86rf231_rx_buffer[rx_buffer_next].frame.fcf.frame_type != 2) { |
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#ifdef ENABLE_DEBUG |
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print_802154_fcf_frame(&at86rf231_rx_buffer[rx_buffer_next].frame); |
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#endif |
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/* notify transceiver thread if any */ |
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if (transceiver_pid) { |
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msg_t m; |
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m.type = (uint16_t) RCV_PKT_AT86RF231; |
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m.content.value = rx_buffer_next; |
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msg_send_int(&m, transceiver_pid); |
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} |
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} else { |
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#ifdef ENABLE_DEBUG |
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DEBUG("GOT ACK for SEQ %u\n", at86rf231_rx_buffer[rx_buffer_next].frame.seq_nr); |
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print_802154_fcf_frame(&at86rf231_rx_buffer[rx_buffer_next].frame); |
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#endif |
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} |
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// shift to next buffer element
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if (++rx_buffer_next == AT86RF231_RX_BUF_SIZE) { |
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rx_buffer_next = 0; |
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} |
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// Read IRQ to clear it
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at86rf231_reg_read(AT86RF231_REG__IRQ_STATUS); |
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} |
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#include <at86rf231_spi.h> |
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#include <at86rf231_arch.h> |
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#include <at86rf231_settings.h> |
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void at86rf231_reg_write(uint8_t addr, uint8_t value) |
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{ |
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// Start the SPI transfer
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at86rf231_spi_select(); |
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// Send first byte being the command and address
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at86rf231_spi_transfer_byte(AT86RF231_ACCESS_REG | AT86RF231_ACCESS_WRITE | addr); |
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// Send value
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at86rf231_spi_transfer_byte(value); |
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// End the SPI transfer
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at86rf231_spi_unselect(); |
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} |
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uint8_t at86rf231_reg_read(uint8_t addr) |
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{ |
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uint8_t value; |
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// Start the SPI transfer
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at86rf231_spi_select(); |
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// Send first byte being the command and address
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at86rf231_spi_transfer_byte(AT86RF231_ACCESS_REG | AT86RF231_ACCESS_READ | addr); |
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// Send value
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value = at86rf231_spi_transfer_byte(0); |
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// End the SPI transfer
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at86rf231_spi_unselect(); |
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return value; |
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} |
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void at86rf231_read_fifo(uint8_t* data, uint8_t length) |
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{ |
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// Start the SPI transfer
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at86rf231_spi_select(); |
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// Send Frame Buffer Write access
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at86rf231_spi_transfer_byte(AT86RF231_ACCESS_FRAMEBUFFER | AT86RF231_ACCESS_READ); |
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at86rf231_spi_transfer(0, data, length); |
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// End the SPI transfer
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at86rf231_spi_unselect(); |
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} |
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void at86rf231_write_fifo(const uint8_t* data, uint8_t length) |
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{ |
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// Start the SPI transfer
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at86rf231_spi_select(); |
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// Send Frame Buffer Write access
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at86rf231_spi_transfer_byte(AT86RF231_ACCESS_FRAMEBUFFER | AT86RF231_ACCESS_WRITE); |
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at86rf231_spi_transfer(data, 0, length); |
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// End the SPI transfer
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at86rf231_spi_unselect(); |
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} |
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@ -0,0 +1,106 @@
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#include <at86rf231.h> |
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#include <at86rf231_arch.h> |
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static void at86rf231_xmit(uint8_t *data, uint8_t length); |
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static void at86rf231_gen_pkt(uint8_t *buf, at86rf231_packet_t *packet); |
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static uint8_t sequenz_nr; |
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int16_t at86rf231_send(at86rf231_packet_t *packet) |
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{ |
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// Set missing frame information
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packet->frame.fcf.frame_ver = 0; |
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if (packet->frame.src_pan_id == packet->frame.dest_pan_id) { |
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packet->frame.fcf.panid_comp = 1; |
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} else { |
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packet->frame.fcf.panid_comp = 0; |
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} |
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if(packet->frame.fcf.src_addr_m == 2) { |
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packet->frame.src_addr[1] = (uint8_t)(at86rf231_get_address() >> 8); |
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packet->frame.src_addr[0] = (uint8_t)(at86rf231_get_address() & 0xFF); |
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} else if (packet->frame.fcf.src_addr_m == 3) { |
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packet->frame.src_addr[7] = (uint8_t)(at86rf231_get_address_long() >> 56); |
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packet->frame.src_addr[6] = (uint8_t)(at86rf231_get_address_long() >> 48); |
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packet->frame.src_addr[5] = (uint8_t)(at86rf231_get_address_long() >> 40); |
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packet->frame.src_addr[4] = (uint8_t)(at86rf231_get_address_long() >> 32); |
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packet->frame.src_addr[3] = (uint8_t)(at86rf231_get_address_long() >> 24); |
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packet->frame.src_addr[2] = (uint8_t)(at86rf231_get_address_long() >> 16); |
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packet->frame.src_addr[1] = (uint8_t)(at86rf231_get_address_long() >> 8); |
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packet->frame.src_addr[0] = (uint8_t)(at86rf231_get_address_long() & 0xFF); |
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} |
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packet->frame.src_pan_id = at86rf231_get_pan(); |
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packet->frame.seq_nr = sequenz_nr; |
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sequenz_nr += 1; |
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// calculate size of the frame (payload + FCS) */
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packet->length = get_802154_hdr_len(&packet->frame) + packet->frame.payload_len + 2; |
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if(packet->length > AT86RF231_MAX_PKT_LENGTH) { |
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return -1; |
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} |
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// FCS is added in hardware
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uint8_t pkt[packet->length-2]; |
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/* generate pkt */ |
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at86rf231_gen_pkt(pkt, packet); |
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// transmit packet
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at86rf231_xmit(pkt, packet->length-2); |
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} |
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static void at86rf231_xmit(uint8_t *data, uint8_t length) |
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{ |
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// Go to state PLL_ON
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at86rf231_reg_write(AT86RF231_REG__TRX_STATE, AT86RF231_TRX_STATE__PLL_ON); |
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// wait until it is on PLL_ON state
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uint8_t status; |
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uint8_t max_wait = 100; // TODO : move elsewhere, this is in 10us
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do |
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{ |
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status = at86rf231_get_status(); |
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vtimer_usleep(10); |
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if (!--max_wait) |
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{ |
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printf("at86rf231 : ERROR : could not enter PLL_ON mode"); |
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break; |
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} |
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}
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while ((status & AT86RF231_TRX_STATUS_MASK__TRX_STATUS) != AT86RF231_TRX_STATUS__PLL_ON); |
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// copy the packet to the radio FIFO
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at86rf231_write_fifo(data, length); |
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// Start TX
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at86rf231_reg_write(AT86RF231_REG__TRX_STATE, AT86RF231_TRX_STATE__TX_START); |
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} |
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/**
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* @brief Static function to generate byte array from at86rf231 packet. |
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* |
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*/ |
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static void at86rf231_gen_pkt(uint8_t *buf, at86rf231_packet_t *packet) |
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{ |
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uint8_t index, offset; |
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index = init_802154_frame(&packet->frame, &buf[1]); |
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// add length for at86rf231
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buf[0] = packet->length; |
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index++; |
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offset = index; |
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while(index < packet->length-2) { |
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buf[index] = packet->frame.payload[index-offset]; |
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index += 1; |
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} |
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at86rf231_swap_fcf_bytes(buf); |
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} |
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@ -0,0 +1,64 @@
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#ifndef AT86RF231_H_ |
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#define AT86RF231_H_ |
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#include <stdio.h> |
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#include <stdint.h> |
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#include <ieee802154/ieee802154_frame.h> |
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#include <at86rf231_settings.h> |
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#define AT86RF231_MAX_PKT_LENGTH 127 |
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#define AT86RF231_MAX_DATA_LENGTH 118 |
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/**
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* Structure to represent a at86rf231 packet. |
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*/ |
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typedef struct __attribute__ ((packed)) { |
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/* @{ */ |
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uint8_t length; /** < the length of the frame of the frame including fcs*/ |
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ieee802154_frame_t frame; /** < the ieee802154 frame */ |
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int8_t rssi; /** < the rssi value */ |
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uint8_t crc; /** < 1 if crc was successfull, 0 otherwise */ |
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uint8_t lqi; /** < the link quality indicator */ |
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/* @} */ |
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} at86rf231_packet_t; |
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void at86rf231_init(int tpid); |
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//void at86rf231_reset(void);
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void at86rf231_rx(void); |
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void at86rf231_rx_handler(void); |
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int16_t at86rf231_send(at86rf231_packet_t *packet); |
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uint8_t at86rf231_set_channel(uint8_t channel); |
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uint8_t at86rf231_get_channel(void); |
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uint16_t at86rf231_set_pan(uint16_t pan); |
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uint16_t at86rf231_get_pan(void); |
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uint16_t at86rf231_set_address(uint16_t address); |
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uint16_t at86rf231_get_address(void); |
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uint64_t at86rf231_get_address_long(void); |
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uint64_t at86rf231_set_address_long(uint64_t address); |
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void at86rf231_set_monitor(uint8_t mode); |
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void at86rf231_swap_fcf_bytes(uint8_t *buf); |
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enum |
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{ |
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RF86RF231_MAX_TX_LENGTH = 125, |
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RF86RF231_MAX_RX_LENGTH = 127, |
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RF86RF231_MIN_CHANNEL = 11, |
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RF86RF231_MAX_CHANNEL = 26 |
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}; |
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extern at86rf231_packet_t at86rf231_rx_buffer[AT86RF231_RX_BUF_SIZE]; |
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#endif |
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@ -0,0 +1,21 @@
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#ifndef AT86RF231_ARCH_H_ |
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#define AT86RF231_ARCH_H_ |
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|
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#include <stdint.h> |
||||
|
||||
void at86rf231_gpio_spi_interrupts_init(void); |
||||
|
||||
void at86rf231_reset(void); |
||||
uint8_t at86rf231_get_status(void); |
||||
|
||||
void at86rf231_switch_to_rx(void); |
||||
|
||||
void at86rf231_spi_select(void); |
||||
void at86rf231_spi_unselect(void); |
||||
|
||||
uint8_t at86rf231_spi_transfer_byte(uint8_t byte); |
||||
|
||||
void at86rf231_init_interrupts(void); |
||||
void at86rf231_enable_interrupts(void); |
||||
void at86rf231_disable_interrupts(void); |
||||
#endif |
||||
@ -0,0 +1,221 @@
|
||||
#ifndef AT86AT86RF231_SETTINGS_H |
||||
#define AT86AT86RF231_SETTINGS_H |
||||
|
||||
#define AT86RF231_RX_BUF_SIZE 3 |
||||
|
||||
enum at86rf231_access |
||||
{ |
||||
AT86RF231_ACCESS_REG = 0x80, |
||||
AT86RF231_ACCESS_FRAMEBUFFER = 0x20, |
||||
AT86RF231_ACCESS_SRAM = 0x00, |
||||
|
||||
AT86RF231_ACCESS_READ = 0x00, |
||||
AT86RF231_ACCESS_WRITE = 0x40, |
||||
}; |
||||
|
||||
enum at86rf231_register |
||||
{ |
||||
AT86RF231_REG__TRX_STATUS = 0x01, |
||||
AT86RF231_REG__TRX_STATE = 0x02, |
||||
AT86RF231_REG__TRX_CTRL_0 = 0x03, |
||||
AT86RF231_REG__TRX_CTRL_1 = 0x04, |
||||
AT86RF231_REG__PHY_TX_PWR = 0x05, |
||||
AT86RF231_REG__PHY_RSSI = 0x06, |
||||
AT86RF231_REG__PHY_ED_LEVEL = 0x07, |
||||
AT86RF231_REG__PHY_CC_CCA = 0x08, |
||||
AT86RF231_REG__CCA_THRES = 0x09, |
||||
AT86RF231_REG__RX_CTRL = 0x0A, |
||||
AT86RF231_REG__SFD_VALUE = 0x0B, |
||||
AT86RF231_REG__TRX_CTRL_2 = 0x0C, |
||||
AT86RF231_REG__ANT_DIV = 0x0D, |
||||
AT86RF231_REG__IRQ_MASK = 0x0E, |
||||
AT86RF231_REG__IRQ_STATUS = 0x0F, |
||||
AT86RF231_REG__VREG_CTRL = 0x10, |
||||
AT86RF231_REG__BATMON = 0x11, |
||||
AT86RF231_REG__XOSC_CTRL = 0x12, |
||||
|
||||
AT86RF231_REG__RX_SYN = 0x15, |
||||
|
||||
AT86RF231_REG__XAH_CTRL_1 = 0x17, |
||||
AT86RF231_REG__FTN_CTRL = 0x18, |
||||
|
||||
AT86RF231_REG__PLL_CF = 0x1A, |
||||
AT86RF231_REG__PLL_DCU = 0x1B, |
||||
AT86RF231_REG__PART_NUM = 0x1C, |
||||
AT86RF231_REG__VERSION_NUM = 0x1D, |
||||
AT86RF231_REG__MAN_ID_0 = 0x1E, |
||||
AT86RF231_REG__MAN_ID_1 = 0x1F, |
||||
AT86RF231_REG__SHORT_ADDR_0 = 0x20, |
||||
AT86RF231_REG__SHORT_ADDR_1 = 0x21, |
||||
AT86RF231_REG__PAN_ID_0 = 0x22, |
||||
AT86RF231_REG__PAN_ID_1 = 0x23, |
||||
|
||||
AT86RF231_REG__IEEE_ADDR_0 = 0x24, |
||||
AT86RF231_REG__IEEE_ADDR_1 = 0x25, |
||||
AT86RF231_REG__IEEE_ADDR_2 = 0x26, |
||||
AT86RF231_REG__IEEE_ADDR_3 = 0x27, |
||||
AT86RF231_REG__IEEE_ADDR_4 = 0x28, |
||||
AT86RF231_REG__IEEE_ADDR_5 = 0x29, |
||||
AT86RF231_REG__IEEE_ADDR_6 = 0x2A, |
||||
AT86RF231_REG__IEEE_ADDR_7 = 0x2B, |
||||
|
||||
AT86RF231_REG__XAH_CTRL_0 = 0x2C, |
||||
AT86RF231_REG__CSMA_SEED_0 = 0x2D, |
||||
AT86RF231_REG__CSMA_SEED_1 = 0x2E, |
||||
AT86RF231_REG__CSMA_BE = 0x2F, |
||||
|
||||
|
||||
AT86RF231_REG__TST_CTRL_DIGI = 0x36, |
||||
}; |
||||
|
||||
enum |
||||
{ |
||||
AT86RF231_TRX_CTRL_0_MASK__PAD_IO = 0xC0, |
||||
AT86RF231_TRX_CTRL_0_MASK__PAD_IO_CLKM = 0x30, |
||||
AT86RF231_TRX_CTRL_0_MASK__CLKM_SHA_SEL = 0x08, |
||||
AT86RF231_TRX_CTRL_0_MASK__CLKM_CTRL = 0x07, |
||||
|
||||
AT86RF231_TRX_CTRL_0_DEFAULT__PAD_IO = 0x00, |
||||
AT86RF231_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM = 0x10, |
||||
AT86RF231_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL = 0x08, |
||||
AT86RF231_TRX_CTRL_0_DEFAULT__CLKM_CTRL = 0x01, |
||||
|
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__OFF = 0x00, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__1MHz = 0x01, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__2MHz = 0x02, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__4MHz = 0x03, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__8MHz = 0x04, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__16MHz = 0x05, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__250kHz = 0x06, |
||||
AT86RF231_TRX_CTRL_0_CLKM_CTRL__62_5kHz = 0x07, |
||||
}; |
||||
|
||||
enum |
||||
{ |
||||
AT86RF231_TRX_CTRL_1_MASK__PA_EXT_EN = 0x80, |
||||
AT86RF231_TRX_CTRL_1_MASK__IRQ_2_EXT_EN = 0x40, |
||||
AT86RF231_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON = 0x20, |
||||
AT86RF231_TRX_CTRL_1_MASK__RX_BL_CTRL = 0x10, |
||||
AT86RF231_TRX_CTRL_1_MASK__SPI_CMD_MODE = 0x0C, |
||||
AT86RF231_TRX_CTRL_1_MASK__IRQ_MASK_MODE = 0x02, |
||||
AT86RF231_TRX_CTRL_1_MASK__IRQ_POLARITY = 0x01, |
||||
}; |
||||
|
||||
enum |
||||
{ |
||||
AT86RF231_TRX_CTRL_2_MASK__RX_SAFE_MODE = 0x80, |
||||
AT86RF231_TRX_CTRL_2_MASK__OQPSK_DATA_RATE = 0x03, |
||||
}; |
||||
|
||||
enum |
||||
{ |
||||
AT86RF231_IRQ_STATUS_MASK__BAT_LOW = 0x80, |
||||
AT86RF231_IRQ_STATUS_MASK__TRX_UR = 0x40, |
||||
AT86RF231_IRQ_STATUS_MASK__AMI = 0x20, |
||||
AT86RF231_IRQ_STATUS_MASK__CCA_ED_DONE = 0x10, |
||||
AT86RF231_IRQ_STATUS_MASK__TRX_END = 0x08, |
||||
AT86RF231_IRQ_STATUS_MASK__RX_START = 0x04, |
||||
AT86RF231_IRQ_STATUS_MASK__PLL_UNLOCK = 0x02, |
||||
AT86RF231_IRQ_STATUS_MASK__PLL_LOCK = 0x01, |
||||
}; |
||||
|
||||
enum at86rf231_trx_status |
||||
{ |
||||
AT86RF231_TRX_STATUS_MASK__CCA_DONE = 0x80, |
||||
AT86RF231_TRX_STATUS_MASK__CCA_STATUS = 0x40, |
||||
AT86RF231_TRX_STATUS_MASK__TRX_STATUS = 0x1F, |
||||
|
||||
AT86RF231_TRX_STATUS__P_ON = 0x00, |
||||
AT86RF231_TRX_STATUS__BUSY_RX = 0x01, |
||||
AT86RF231_TRX_STATUS__BUSY_TX = 0x02, |
||||
AT86RF231_TRX_STATUS__RX_ON = 0x06, |
||||
AT86RF231_TRX_STATUS__TRX_OFF = 0x08, |
||||
AT86RF231_TRX_STATUS__PLL_ON = 0x09, |
||||
AT86RF231_TRX_STATUS__SLEEP = 0x0F, |
||||
AT86RF231_TRX_STATUS__BUSY_RX_AACK = 0x11, |
||||
AT86RF231_TRX_STATUS__BUSY_TX_ARET = 0x12, |
||||
AT86RF231_TRX_STATUS__RX_AACK_ON = 0x16, |
||||
AT86RF231_TRX_STATUS__TX_ARET_ON = 0x19, |
||||
AT86RF231_TRX_STATUS__RX_ON_NOCLK = 0x1C, |
||||
AT86RF231_TRX_STATUS__RX_AACK_ON_NOCLK = 0x1D, |
||||
AT86RF231_TRX_STATUS__BUSY_RX_AACK_NOCLK = 0x1E, |
||||
AT86RF231_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS = 0x1F, |
||||
}; |
||||
|
||||
enum at86rf231_trx_state |
||||
{ |
||||
AT86RF231_TRX_STATE__NOP = 0x00, |
||||
AT86RF231_TRX_STATE__TX_START = 0x02, |
||||
AT86RF231_TRX_STATE__FORCE_TRX_OFF = 0x03, |
||||
AT86RF231_TRX_STATE__FORCE_PLL_ON = 0x04, |
||||
AT86RF231_TRX_STATE__RX_ON = 0x06, |
||||
AT86RF231_TRX_STATE__TRX_OFF = 0x08, |
||||
AT86RF231_TRX_STATE__PLL_ON = 0x09, |
||||
AT86RF231_TRX_STATE__RX_AACK_ON = 0x16, |
||||
AT86RF231_TRX_STATE__TX_ARET_ON = 0x19, |
||||
}; |
||||
|
||||
enum at86rf231_phy_cc_cca |
||||
{ |
||||
AT86RF231_PHY_CC_CCA_MASK__CCA_REQUEST = 0x80, |
||||
AT86RF231_PHY_CC_CCA_MASK__CCA_MODE = 0x60, |
||||
AT86RF231_PHY_CC_CCA_MASK__CHANNEL = 0x1F, |
||||
|
||||
AT86RF231_PHY_CC_CCA_DEFAULT__CCA_MODE = 0x20, |
||||
}; |
||||
|
||||
enum at86rf231_phy_tx_pwr |
||||
{ |
||||
AT86RF231_PHY_TX_PWR_MASK__PA_BUF_LT = 0xC0, |
||||
AT86RF231_PHY_TX_PWR_MASK__PA_LT = 0x30, |
||||
AT86RF231_PHY_TX_PWR_MASK__TX_PWR = 0x0F, |
||||
|
||||
AT86RF231_PHY_TX_PWR_DEFAULT__PA_BUF_LT = 0xC0, |
||||
AT86RF231_PHY_TX_PWR_DEFAULT__PA_LT = 0x00, |
||||
AT86RF231_PHY_TX_PWR_DEFAULT__TX_PWR = 0x00, |
||||
|
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__3dBm = 0x00, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__2_8dBm = 0x01, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__2_3dBm = 0x02, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__1_8dBm = 0x03, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__1_3dBm = 0x04, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__0_7dBm = 0x05, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__0dBm = 0x06, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m1dBm = 0x07, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m2dBm = 0x08, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m3dBm = 0x09, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m4dBm = 0x0A, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m5dBm = 0x0B, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m7dBm = 0x0C, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m9dBm = 0x0D, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m12dBm = 0x0E, |
||||
AT86RF231_PHY_TX_PWR_TX_PWR_VALUE__m17dBm = 0x0F, |
||||
|
||||
}; |
||||
|
||||
enum at86rf231_phy_rssi |
||||
{ |
||||
AT86RF231_PHY_RSSI_MASK__RX_CRC_VALID = 0x80, |
||||
AT86RF231_PHY_RSSI_MASK__RND_VALUE = 0x60, |
||||
AT86RF231_PHY_RSSI_MASK__RSSI = 0x1F, |
||||
}; |
||||
|
||||
enum at86rf231_xosc_ctrl |
||||
{ |
||||
AT86RF231_XOSC_CTRL__XTAL_MODE_CRYSTAL = 0xF0, |
||||
AT86RF231_XOSC_CTRL__XTAL_MODE_EXTERNAL = 0xF0, |
||||
}; |
||||
|
||||
enum |
||||
{ |
||||
AT86RF231_TIMING__VCC_TO_P_ON = 330, |
||||
AT86RF231_TIMING__SLEEP_TO_TRX_OFF = 380, |
||||
AT86RF231_TIMING__TRX_OFF_TO_PLL_ON = 110, |
||||
AT86RF231_TIMING__TRX_OFF_TO_RX_ON = 110, |
||||
AT86RF231_TIMING__PLL_ON_TO_BUSY_TX = 16, |
||||
|
||||
AT86RF231_TIMING__RESET = 100, |
||||
AT86RF231_TIMING__RESET_TO_TRX_OFF = 37, |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,9 @@
|
||||
#ifndef AT86RF231_SPI_H_ |
||||
#define AT86RF231_SPI_H_ |
||||
|
||||
#include <stdint.h> |
||||
|
||||
uint8_t at86rf231_reg_read(uint8_t addr); |
||||
void at86rf231_reg_write(uint8_t addr, uint8_t value); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue