
5 changed files with 90 additions and 0 deletions
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|
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/* |
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* NXP Kinetis CPU with the following memory layout: |
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* 1024 kB flash @ 0x00000000 |
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* 256 kB RAM, split into two banks: 64 kB SRAM_L, 192 kB SRAM_U. |
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000 |
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*/ |
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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MEMORY |
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{ |
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400 |
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 |
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 1024K - 0x410 |
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ram (rwx) : ORIGIN = 0x20000000 - 64K, LENGTH = 256K |
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} |
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INCLUDE kinetis.ld |
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/* |
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* NXP Kinetis CPU with the following memory layout: |
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* 256 kB flash @ 0x00000000 |
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* 32 kB RAM, split into two banks: 16 kB SRAM_L, 16 kB SRAM_U. |
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000 |
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*/ |
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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|
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MEMORY |
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{ |
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400 |
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 |
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x410 |
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ram (rwx) : ORIGIN = 0x20000000 - 16K, LENGTH = 32K |
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} |
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INCLUDE kinetis.ld |
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/* |
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* NXP Kinetis CPU with the following memory layout: |
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* 256 kB flash @ 0x00000000 |
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* 64 kB RAM, split into two banks: 32 kB SRAM_L, 32 kB SRAM_U. |
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000 |
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*/ |
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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|
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MEMORY |
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{ |
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400 |
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 |
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x410 |
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ram (rwx) : ORIGIN = 0x20000000 - 32K, LENGTH = 64K |
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} |
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INCLUDE kinetis.ld |
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|
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/* |
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* NXP Kinetis CPU with the following memory layout: |
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* 512 kB flash @ 0x00000000 |
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* 64 kB RAM, split into two banks: 32 kB SRAM_L, 32 kB SRAM_U. |
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000 |
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*/ |
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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|
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MEMORY |
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{ |
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400 |
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 |
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 512K - 0x410 |
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ram (rwx) : ORIGIN = 0x20000000 - 32K, LENGTH = 64K |
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} |
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INCLUDE kinetis.ld |
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/* |
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* NXP Kinetis CPU with the following memory layout: |
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* 512 kB flash @ 0x00000000 |
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* 128 kB RAM, split into two banks: 64 kB SRAM_L, 64 kB SRAM_U. |
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000 |
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*/ |
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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MEMORY |
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{ |
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400 |
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10 |
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 512K - 0x410 |
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ram (rwx) : ORIGIN = 0x20000000 - 64K, LENGTH = 128K |
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} |
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INCLUDE kinetis.ld |
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