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kinetis_common: Refactor GPIO implementation

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This is a rewrite of the Kinetis GPIO driver which follows the
refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y)
macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin.

The interrupt pin handling is now implemented as a linked list, this
is more memory efficient, but with a minor variation in interrupt
latency depending on in what order the pins were initialized at
runtime.

Because the linked list entries are taken from a shared pool, there is
also the possibility of running out of available configuration slots,
define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if
you need more than 16 pins configured for interrupts in the same
application.

[1]: https://github.com/RIOT-OS/RIOT/pull/3095
cc430
Joakim Nohlgård 8 years ago
parent c78fd9f4ed
commit 142c28094e
13 changed files with 452 additions and 2308 deletions
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24
boards/frdm-k64f/include/board.h
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@ -48,9 +48,9 @@ extern "C"
* @name LED pin definitions
* @{
*/
#define LED_R_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK)) /**< Clock Enable for PORTD*/
#define LED_G_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK)) /**< Clock Enable for PORTD*/
#define LED_B_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK)) /**< Clock Enable for PORTA*/
#define LED_R_PORT_CLKEN() (PORTB_CLOCK_GATE = 1) /**< Clock Enable for PORTD*/
#define LED_G_PORT_CLKEN() (PORTE_CLOCK_GATE = 1) /**< Clock Enable for PORTE*/
#define LED_B_PORT_CLKEN() (PORTB_CLOCK_GATE = 1) /**< Clock Enable for PORTB*/
#define LED_R_PORT PORTB /**< PORT for Red LED*/
#define LED_R_GPIO GPIOB /**< GPIO-Device for Red LED*/
#define LED_G_PORT PORTE /**< PORT for Green LED*/
@ -66,15 +66,15 @@ extern "C"
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_B_ON (LED_B_GPIO->PCOR |= (1 << LED_B_PIN))
#define LED_B_OFF (LED_B_GPIO->PSOR |= (1 << LED_B_PIN))
#define LED_B_TOGGLE (LED_B_GPIO->PTOR |= (1 << LED_B_PIN))
#define LED_G_ON (LED_G_GPIO->PCOR |= (1 << LED_G_PIN))
#define LED_G_OFF (LED_G_GPIO->PSOR |= (1 << LED_G_PIN))
#define LED_G_TOGGLE (LED_G_GPIO->PTOR |= (1 << LED_G_PIN))
#define LED_R_ON (LED_R_GPIO->PCOR |= (1 << LED_R_PIN))
#define LED_R_OFF (LED_R_GPIO->PSOR |= (1 << LED_R_PIN))
#define LED_R_TOGGLE (LED_R_GPIO->PTOR |= (1 << LED_R_PIN))
#define LED_B_ON (LED_B_GPIO->PCOR = (1 << LED_B_PIN))
#define LED_B_OFF (LED_B_GPIO->PSOR = (1 << LED_B_PIN))
#define LED_B_TOGGLE (LED_B_GPIO->PTOR = (1 << LED_B_PIN))
#define LED_G_ON (LED_G_GPIO->PCOR = (1 << LED_G_PIN))
#define LED_G_OFF (LED_G_GPIO->PSOR = (1 << LED_G_PIN))
#define LED_G_TOGGLE (LED_G_GPIO->PTOR = (1 << LED_G_PIN))
#define LED_R_ON (LED_R_GPIO->PCOR = (1 << LED_R_PIN))
#define LED_R_OFF (LED_R_GPIO->PSOR = (1 << LED_R_PIN))
#define LED_R_TOGGLE (LED_R_GPIO->PTOR = (1 << LED_R_PIN))
/* for compatability to other boards */
#define LED_GREEN_ON LED_G_ON

55
boards/frdm-k64f/include/periph_conf.h
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@ -258,60 +258,7 @@ extern "C"
* @name GPIO configuration
* @{
*/
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_IRQ_PRIO 1
#define ISR_PORT_A isr_porta
#define ISR_PORT_B isr_portb
#define ISR_PORT_C isr_portc
#define ISR_PORT_D isr_portd
/* GPIO channel 0 config */
#define GPIO_0_DEV GPIOB /* LED_R */
#define GPIO_0_PORT PORTB
#define GPIO_0_PORT_BASE PORTB_BASE
#define GPIO_0_PIN 22
#define GPIO_0_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
#define GPIO_0_IRQ PORTB_IRQn
/* GPIO channel 1 config */
#define GPIO_1_DEV GPIOE /* LED_G */
#define GPIO_1_PORT PORTE
#define GPIO_1_PORT_BASE PORTE_BASE
#define GPIO_1_PIN 26
#define GPIO_1_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_1_IRQ PORTE_IRQn
/* GPIO channel 2 config */
#define GPIO_2_DEV GPIOB /* LED_B */
#define GPIO_2_PORT PORTB
#define GPIO_2_PORT_BASE PORTB_BASE
#define GPIO_2_PIN 21
#define GPIO_2_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
#define GPIO_2_IRQ PORTB_IRQn
/* GPIO channel 3 config */
#define GPIO_3_DEV GPIOC /* SW2 */
#define GPIO_3_PORT PORTC
#define GPIO_3_PORT_BASE PORTC_BASE
#define GPIO_3_PIN 6
#define GPIO_3_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define GPIO_3_IRQ PORTC_IRQn
/* GPIO channel 4 config */
#define GPIO_4_DEV GPIOB /* A0 (Arduino Headers) */
#define GPIO_4_PORT PORTB
#define GPIO_4_PORT_BASE PORTB_BASE
#define GPIO_4_PIN 2
#define GPIO_4_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
#define GPIO_4_IRQ PORTB_IRQn
/* GPIO channel 5 config */
#define GPIO_5_DEV GPIOB /* A1 (Arduino Headers) */
#define GPIO_5_PORT PORTB
#define GPIO_5_PORT_BASE PORTB_BASE
#define GPIO_5_PIN 3
#define GPIO_5_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
#define GPIO_5_IRQ PORTB_IRQn
#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/** @} */
/**

40
boards/mulle/include/board.h
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@ -47,15 +47,15 @@
* @{
*/
#define LED_RED_GPIO GPIO_0
#define LED_RED_PORT GPIO_0_DEV
#define LED_RED_PIN GPIO_0_PIN
#define LED_YELLOW_GPIO GPIO_1
#define LED_YELLOW_PORT GPIO_1_DEV
#define LED_YELLOW_PIN GPIO_1_PIN
#define LED_GREEN_GPIO GPIO_2
#define LED_GREEN_PORT GPIO_2_DEV
#define LED_GREEN_PIN GPIO_2_PIN
#define LED_RED_PORT PTC
#define LED_RED_PIN 15
#define LED_RED_GPIO GPIO_PIN(PORT_C, LED_RED_PIN)
#define LED_YELLOW_PORT PTC
#define LED_YELLOW_PIN 14
#define LED_YELLOW_GPIO GPIO_PIN(PORT_C, LED_YELLOW_PIN)
#define LED_GREEN_PORT PTC
#define LED_GREEN_PIN 13
#define LED_GREEN_GPIO GPIO_PIN(PORT_C, LED_GREEN_PIN)
/** @} */
@ -92,11 +92,11 @@ void board_init(void);
* @{
*/
#define AT86RF231_SPI SPI_0
#define AT86RF231_CS GPIO_14
#define AT86RF231_INT GPIO_12
#define AT86RF231_CS GPIO_PIN(PORT_D, 4)
#define AT86RF231_INT GPIO_PIN(PORT_B, 9)
/** @todo work around missing RESET pin on Mulle v0.6x */
#define AT86RF231_RESET GPIO_5
#define AT86RF231_SLEEP GPIO_13
#define AT86RF231_RESET GPIO_PIN(PORT_C, 12)
#define AT86RF231_SLEEP GPIO_PIN(PORT_E, 6)
#define AT86RF231_SPI_CLK SPI_SPEED_5MHZ
/** @} */
@ -105,9 +105,9 @@ void board_init(void);
* @{
*/
#define LIS3DH_INT1 GPIO_3
#define LIS3DH_INT2 GPIO_4
#define LIS3DH_CS GPIO_15
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_SPI SPI_2
/** @} */
@ -116,9 +116,9 @@ void board_init(void);
* @name Mulle power control configuration
*/
/** @{ */
#define MULLE_POWER_AVDD GPIO_6 /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_7 /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_5 /**< VSEC enable pin */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
/** @} */
/**
@ -127,7 +127,7 @@ void board_init(void);
/** @{ */
/** FRAM SPI bus, SPI_2 in RIOT is mapped to hardware bus SPI0, see periph_conf.h */
#define MULLE_NVRAM_SPI_DEV SPI_2
#define MULLE_NVRAM_SPI_CS GPIO_16 /**< FRAM CS pin */
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
/** @} */

313
boards/mulle/include/periph_conf.h
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@ -63,7 +63,7 @@ extern "C"
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_1_EN 0
#define TIMER_IRQ_PRIO 1
#define TIMER_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define TIMER_BASE PIT
#define TIMER_MAX_VALUE (0xffffffff)
#define TIMER_CLOCK SystemBusClock
@ -94,7 +94,7 @@ extern "C"
#define UART_2_EN 0
#define UART_3_EN 0
#define UART_4_EN 0
#define UART_IRQ_PRIO 1
#define UART_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/* UART 0 device configuration */
#define UART_0_DEV UART1
@ -301,7 +301,7 @@ extern "C"
#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO 1
#define SPI_0_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_0_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
@ -335,7 +335,7 @@ extern "C"
#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO 1
#define SPI_1_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_1_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
@ -369,7 +369,7 @@ extern "C"
#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO 1
#define SPI_2_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_2_FREQ SystemBusClock
/* SPI 2 pin configuration, must be the same as the other RIOT device using this
* hardware module */
@ -429,7 +429,7 @@ extern "C"
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO 1
#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/**
* @name I2C baud rate configuration
* @{
@ -468,304 +468,7 @@ extern "C"
* @name GPIO configuration
* @{
*/
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_12_EN 1
#define GPIO_13_EN 1
#define GPIO_14_EN 1
#define GPIO_15_EN 1
#define GPIO_16_EN 1
#define GPIO_17_EN 1
#define GPIO_18_EN 1
#define GPIO_19_EN 1
#define GPIO_20_EN 1
#define GPIO_21_EN 1
#define GPIO_22_EN 1
#define GPIO_23_EN 1
#define GPIO_24_EN 1
#define GPIO_25_EN 1
#define GPIO_26_EN 1
#define GPIO_IRQ_PRIO 1
/* GPIO channel 0 config */
/* Red LED */
#define GPIO_0_PORT PORTC
#define GPIO_0_PORT_BASE PORTC_BASE
#define GPIO_0_DEV PTC
#define GPIO_0_PIN 15
#define GPIO_0_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_0_IRQ PORTC_IRQn
#define GPIO_0_ISR isr_portc_pin_detect
/* GPIO channel 1 config */
/* Yellow LED */
#define GPIO_1_PORT PORTC
#define GPIO_1_PORT_BASE PORTC_BASE
#define GPIO_1_DEV PTC
#define GPIO_1_PIN 14
#define GPIO_1_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_1_IRQ PORTC_IRQn
#define GPIO_1_ISR isr_portc_pin_detect
/* GPIO channel 2 config */
/* Green LED */
#define GPIO_2_PORT PORTC
#define GPIO_2_PORT_BASE PORTC_BASE
#define GPIO_2_DEV PTC
#define GPIO_2_PIN 13
#define GPIO_2_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_2_IRQ PORTC_IRQn
#define GPIO_2_ISR isr_portc_pin_detect
/* GPIO channel 3 config */
/* LIS3DH INT1 */
#define GPIO_3_PORT PORTC
#define GPIO_3_PORT_BASE PORTC_BASE
#define GPIO_3_DEV PTC
#define GPIO_3_PIN 18
#define GPIO_3_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_3_IRQ PORTC_IRQn
#define GPIO_3_ISR isr_portc_pin_detect
/* GPIO channel 4 config */
/* LIS3DH INT2 */
#define GPIO_4_PORT PORTC
#define GPIO_4_PORT_BASE PORTC_BASE
#define GPIO_4_DEV PTC
#define GPIO_4_PIN 17
#define GPIO_4_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_4_IRQ PORTC_IRQn
#define GPIO_4_ISR isr_portc_pin_detect
/* GPIO channel 5 config */
/* VSEC enable */
#define GPIO_5_PORT PORTB
#define GPIO_5_PORT_BASE PORTB_BASE
#define GPIO_5_DEV PTB
#define GPIO_5_PIN 16
#define GPIO_5_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_5_IRQ PORTB_IRQn
#define GPIO_5_ISR isr_portb_pin_detect
/* GPIO channel 6 config */
/* AVDD enable */
#define GPIO_6_PORT PORTB
#define GPIO_6_PORT_BASE PORTB_BASE
#define GPIO_6_DEV PTB
#define GPIO_6_PIN 17
#define GPIO_6_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_6_IRQ PORTB_IRQn
#define GPIO_6_ISR isr_portb_pin_detect
/* GPIO channel 7 config */
/* VPERIPH enable */
#define GPIO_7_PORT PORTD
#define GPIO_7_PORT_BASE PORTD_BASE
#define GPIO_7_DEV PTD
#define GPIO_7_PIN 7
#define GPIO_7_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_7_IRQ PORTD_IRQn
#define GPIO_7_ISR isr_portd_pin_detect
/* GPIO channel 8 config */
/* MC34673 enable */
#define GPIO_8_PORT PORTB
#define GPIO_8_PORT_BASE PORTB_BASE
#define GPIO_8_DEV PTB
#define GPIO_8_PIN 23
#define GPIO_8_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_8_IRQ PORTB_IRQn
#define GPIO_8_ISR isr_portb_pin_detect
/* GPIO channel 9 config */
/* MC34673 CHG */
#define GPIO_9_PORT PORTB
#define GPIO_9_PORT_BASE PORTB_BASE
#define GPIO_9_DEV PTB
#define GPIO_9_PIN 22
#define GPIO_9_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_9_IRQ PORTB_IRQn
#define GPIO_9_ISR isr_portb_pin_detect
/* GPIO channel 10 config */
/* MC34673 PPR */
#define GPIO_10_PORT PORTB
#define GPIO_10_PORT_BASE PORTB_BASE
#define GPIO_10_DEV PTB
#define GPIO_10_PIN 21
#define GPIO_10_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_10_IRQ PORTB_IRQn
#define GPIO_10_ISR isr_portb_pin_detect
/* GPIO channel 11 config */
/* MC34673 FAST */
#define GPIO_11_PORT PORTB
#define GPIO_11_PORT_BASE PORTB_BASE
#define GPIO_11_DEV PTB
#define GPIO_11_PIN 20
#define GPIO_11_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_11_IRQ PORTB_IRQn
#define GPIO_11_ISR isr_portb_pin_detect
/* GPIO channel 12 config */
/* AT86RF212 IRQ */
#define GPIO_12_PORT PORTB
#define GPIO_12_PORT_BASE PORTB_BASE
#define GPIO_12_DEV PTB
#define GPIO_12_PIN 9
#define GPIO_12_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_12_IRQ PORTB_IRQn
#define GPIO_12_ISR isr_portb_pin_detect
/* GPIO channel 13 config */
/* AT86RF212 SLP_TR */
#define GPIO_13_PORT PORTE
#define GPIO_13_PORT_BASE PORTE_BASE
#define GPIO_13_DEV PTE
#define GPIO_13_PIN 6
#define GPIO_13_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_13_IRQ PORTE_IRQn
#define GPIO_13_ISR isr_porte_pin_detect
/* GPIO channel 14 config */
/* AT86RF212 SS */
#define GPIO_14_PORT PORTD
#define GPIO_14_PORT_BASE PORTD_BASE
#define GPIO_14_DEV PTD
#define GPIO_14_PIN 4
#define GPIO_14_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_14_IRQ PORTD_IRQn
#define GPIO_14_ISR isr_portd_pin_detect
/* GPIO channel 15 config */
/* LIS3DH CS */
#define GPIO_15_PORT PORTD
#define GPIO_15_PORT_BASE PORTD_BASE
#define GPIO_15_DEV PTD
#define GPIO_15_PIN 0
#define GPIO_15_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_15_IRQ PORTD_IRQn
#define GPIO_15_ISR isr_portd_pin_detect
/* GPIO channel 16 config */
/* FM25L04B CS */
#define GPIO_16_PORT PORTD
#define GPIO_16_PORT_BASE PORTD_BASE
#define GPIO_16_DEV PTD
#define GPIO_16_PIN 6
#define GPIO_16_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_16_IRQ PORTD_IRQn
#define GPIO_16_ISR isr_portd_pin_detect
/* GPIO channel 17 config */
/* M25P16 CS */
#define GPIO_17_PORT PORTD
#define GPIO_17_PORT_BASE PORTD_BASE
#define GPIO_17_DEV PTD
#define GPIO_17_PIN 5
#define GPIO_17_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_17_IRQ PORTD_IRQn
#define GPIO_17_ISR isr_portd_pin_detect
/* GPIO channel 18 config */
/* General purpose expansion PTB18 */
#define GPIO_18_PORT PORTB
#define GPIO_18_PORT_BASE PORTB_BASE
#define GPIO_18_DEV PTB
#define GPIO_18_PIN 18
#define GPIO_18_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_18_IRQ PORTB_IRQn
#define GPIO_18_ISR isr_portb_pin_detect
/* GPIO channel 19 config */
/* General purpose expansion PTB19 */
#define GPIO_19_PORT PORTB
#define GPIO_19_PORT_BASE PORTB_BASE
#define GPIO_19_DEV PTB
#define GPIO_19_PIN 19
#define GPIO_19_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_19_IRQ PORTB_IRQn
#define GPIO_19_ISR isr_portb_pin_detect
/* GPIO channel 20 config */
/* General purpose expansion PTC0 */
#define GPIO_20_PORT PORTC
#define GPIO_20_PORT_BASE PORTC_BASE
#define GPIO_20_DEV PTC
#define GPIO_20_PIN 0
#define GPIO_20_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_20_IRQ PORTC_IRQn
#define GPIO_20_ISR isr_portc_pin_detect
/* GPIO channel 21 config */
/* General purpose expansion PTC1 */
#define GPIO_21_PORT PORTC
#define GPIO_21_PORT_BASE PORTC_BASE
#define GPIO_21_DEV PTC
#define GPIO_21_PIN 1
#define GPIO_21_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_21_IRQ PORTC_IRQn
#define GPIO_21_ISR isr_portc_pin_detect
/* GPIO channel 22 config */
/* General purpose expansion PTC2 */
#define GPIO_22_PORT PORTC
#define GPIO_22_PORT_BASE PORTC_BASE
#define GPIO_22_DEV PTC
#define GPIO_22_PIN 2
#define GPIO_22_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_22_IRQ PORTC_IRQn
#define GPIO_22_ISR isr_portc_pin_detect
/* GPIO channel 23 config */
/* General purpose expansion PTC5 */
#define GPIO_23_PORT PORTC
#define GPIO_23_PORT_BASE PORTC_BASE
#define GPIO_23_DEV PTC
#define GPIO_23_PIN 5
#define GPIO_23_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_23_IRQ PORTC_IRQn
#define GPIO_23_ISR isr_portc_pin_detect
/* GPIO channel 24 config */
/* General purpose expansion PTC6 */
#define GPIO_24_PORT PORTC
#define GPIO_24_PORT_BASE PORTC_BASE
#define GPIO_24_DEV PTC
#define GPIO_24_PIN 6
#define GPIO_24_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_24_IRQ PORTC_IRQn
#define GPIO_24_ISR isr_portc_pin_detect
/* GPIO channel 25 config */
/* General purpose expansion PTC7 */
#define GPIO_25_PORT PORTC
#define GPIO_25_PORT_BASE PORTC_BASE
#define GPIO_25_DEV PTC
#define GPIO_25_PIN 7
#define GPIO_25_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_25_IRQ PORTC_IRQn
#define GPIO_25_ISR isr_portc_pin_detect
/* GPIO channel 26 config */
/* General purpose expansion PTE4 */
#define GPIO_26_PORT PORTE
#define GPIO_26_PORT_BASE PORTE_BASE
#define GPIO_26_DEV PTE
#define GPIO_26_PIN 4
#define GPIO_26_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_26_IRQ PORTE_IRQn
#define GPIO_26_ISR isr_porte_pin_detect
#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/** @} */
@ -782,7 +485,7 @@ extern "C"
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_IRQ_PRIO 1
#define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define RTT_IRQ RTC_IRQn
#define RTT_ISR isr_rtc_alarm
#define RTT_DEV RTC

22
boards/pba-d-01-kw2x/include/board.h
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@ -66,15 +66,15 @@ extern "C"
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_B_ON (LED_B_GPIO->PCOR |= (1 << LED_B_PIN))
#define LED_B_OFF (LED_B_GPIO->PSOR |= (1 << LED_B_PIN))
#define LED_B_TOGGLE (LED_B_GPIO->PTOR |= (1 << LED_B_PIN))
#define LED_G_ON (LED_G_GPIO->PCOR |= (1 << LED_G_PIN))
#define LED_G_OFF (LED_G_GPIO->PSOR |= (1 << LED_G_PIN))
#define LED_G_TOGGLE (LED_G_GPIO->PTOR |= (1 << LED_G_PIN))
#define LED_R_ON (LED_R_GPIO->PCOR |= (1 << LED_R_PIN))
#define LED_R_OFF (LED_R_GPIO->PSOR |= (1 << LED_R_PIN))
#define LED_R_TOGGLE (LED_R_GPIO->PTOR |= (1 << LED_R_PIN))
#define LED_B_ON (LED_B_GPIO->PCOR = (1 << LED_B_PIN))
#define LED_B_OFF (LED_B_GPIO->PSOR = (1 << LED_B_PIN))
#define LED_B_TOGGLE (LED_B_GPIO->PTOR = (1 << LED_B_PIN))
#define LED_G_ON (LED_G_GPIO->PCOR = (1 << LED_G_PIN))
#define LED_G_OFF (LED_G_GPIO->PSOR = (1 << LED_G_PIN))
#define LED_G_TOGGLE (LED_G_GPIO->PTOR = (1 << LED_G_PIN))
#define LED_R_ON (LED_R_GPIO->PCOR = (1 << LED_R_PIN))
#define LED_R_OFF (LED_R_GPIO->PSOR = (1 << LED_R_PIN))
#define LED_R_TOGGLE (LED_R_GPIO->PTOR = (1 << LED_R_PIN))
/* for compatability to other boards */
#define LED_GREEN_ON LED_G_ON
@ -90,8 +90,8 @@ extern "C"
@{
*/
#define KW2XRF_SPI (SPI_1)
#define KW2XRF_CS (GPIO_24)
#define KW2XRF_INT (GPIO_23)
#define KW2XRF_CS (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_PCS0_PIN))
#define KW2XRF_INT (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_IRQ_PIN))
#define KW2XRF_SPI_SPEED (SPI_SPEED_10MHZ)
#define KW2XRF_SHARED_SPI 0
/** @}*/

211
boards/pba-d-01-kw2x/include/periph_conf.h
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@ -247,7 +247,7 @@ extern "C"
#define SPI_1_FREQ (48e6)
/* SPI 1 pin1configuration */
#define SPI_1_PORT KW2XDRF_PORT
#define SPI_1_PORT KW2XDRF_PORT_DEV
#define SPI_1_PORT_CLKEN() KW2XDRF_PORT_CLKEN();
#define SPI_1_AF KW2XDRF_PIN_AF
@ -303,214 +303,7 @@ extern "C"
* @name GPIO configuration
* @{
*/
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 0
#define GPIO_7_EN 0
#define GPIO_8_EN 0 /* I2CSDA */
#define GPIO_9_EN 0 /* I2CSCL */
#define GPIO_10_EN 0
#define GPIO_11_EN 0
#define GPIO_12_EN 0
#define GPIO_13_EN 0 /* USB VOUT 3V3 */
#define GPIO_14_EN 0 /* USB VREGIN */
#define GPIO_15_EN 0
#define GPIO_16_EN 0
#define GPIO_17_EN 0
#define GPIO_18_EN 0
#define GPIO_19_EN 0 /* SPI0_CS0 */
#define GPIO_20_EN 0 /* SPI0_CLK */
#define GPIO_21_EN 0 /* SPI0_MOSI */
#define GPIO_22_EN 0 /* SPI0_MISO */
#define GPIO_23_EN 1 /* KW2XRF INT */
#define GPIO_24_EN 1 /* KW2XRF CS */
#define GPIO_IRQ_PRIO 1
#define ISR_PORT_A isr_porta
#define ISR_PORT_B isr_portb
#define ISR_PORT_C isr_portc
#define ISR_PORT_D isr_portd
/* GPIO channel 0 config */
#define GPIO_0_DEV GPIOD /* DIO9; extension connecotr D9; LED_G */
#define GPIO_0_PORT PORTD
#define GPIO_0_PORT_BASE PORTD_BASE
#define GPIO_0_PIN 4
#define GPIO_0_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_0_IRQ PORTD_IRQn
/* GPIO channel 1 config */
#define GPIO_1_DEV GPIOD /* DIO11; extension connecotr D5; LED_R */
#define GPIO_1_PORT PORTD
#define GPIO_1_PORT_BASE PORTD_BASE
#define GPIO_1_PIN 6
#define GPIO_1_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_1_IRQ PORTD_IRQn
/* GPIO channel 2 config */
#define GPIO_2_DEV GPIOA /* DIO27; extension connecotr D3; LED_B */
#define GPIO_2_PORT PORTA
#define GPIO_2_PORT_BASE PORTA_BASE
#define GPIO_2_PIN 4
#define GPIO_2_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
#define GPIO_2_IRQ PORTA_IRQn
/* GPIO channel 3 config */
#define GPIO_3_DEV GPIOD /* DIO06; extension connecotr --; User_Button */
#define GPIO_3_PORT PORTD
#define GPIO_3_PORT_BASE PORTD_BASE
#define GPIO_3_PIN 1
#define GPIO_3_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_3_IRQ PORTD_IRQn
/* GPIO channel 4 config */
#define GPIO_4_DEV GPIOE /* DIO17; extension connecotr D2 */
#define GPIO_4_PORT PORTE
#define GPIO_4_PORT_BASE PORTE_BASE
#define GPIO_4_PIN 4
#define GPIO_4_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_4_IRQ PORTE_IRQn
/* GPIO channel 5 config */
#define GPIO_5_DEV GPIOA /* DIO29; extension connecotr D4 */
#define GPIO_5_PORT PORTA
#define GPIO_5_PORT_BASE PORTA_BASE
#define GPIO_5_PIN 19
#define GPIO_5_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
#define GPIO_5_IRQ PORTA_IRQn
/* GPIO channel 6 config */
#define GPIO_6_DEV GPIOD /* DIO10; extension connecotr A3 */
#define GPIO_6_PORT PORTD
#define GPIO_6_PORT_BASE PORTD_BASE
#define GPIO_6_PIN 5
#define GPIO_6_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_6_IRQ PORTD_IRQn
/* GPIO channel 7 config */
#define GPIO_7_DEV GPIOD /* DIO12; extension connecotr A2 */
#define GPIO_7_PORT PORTD
#define GPIO_7_PORT_BASE PORTD_BASE
#define GPIO_7_PIN 7
#define GPIO_7_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_7_IRQ PORTD_IRQn
/* GPIO channel 8 config */
#define GPIO_8_DEV GPIOE /* DIO13; extension connecotr A4; I2CSDA */
#define GPIO_8_PORT PORTE
#define GPIO_8_PORT_BASE PORTE_BASE
#define GPIO_8_PIN 0
#define GPIO_8_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_8_IRQ PORTE_IRQn
/* GPIO channel 9 config */
#define GPIO_9_DEV GPIOE /* DIO14; extension connecotr A5; I2CSCL */
#define GPIO_9_PORT PORTE
#define GPIO_9_PORT_BASE PORTE_BASE
#define GPIO_9_PIN 1
#define GPIO_9_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_9_IRQ PORTE_IRQn
/* GPIO channel 10 config */
#define GPIO_10_DEV GPIOE /* DIO15; extension connecotr A0 */
#define GPIO_10_PORT PORTE
#define GPIO_10_PORT_BASE PORTE_BASE
#define GPIO_10_PIN 2
#define GPIO_10_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_10_IRQ PORTE_IRQn
/* GPIO channel 11 config */
#define GPIO_11_DEV GPIOE /* DIO16; extension connecotr A1 */
#define GPIO_11_PORT PORTE
#define GPIO_11_PORT_BASE PORTE_BASE
#define GPIO_11_PIN 3
#define GPIO_11_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_11_IRQ PORTE_IRQn
/* GPIO channel 12 config */
#define GPIO_12_DEV GPIOD /* DIO7; extension connecotr D0; UART2_RX */
#define GPIO_12_PORT PORTD
#define GPIO_12_PORT_BASE PORTD_BASE
#define GPIO_12_PIN 2
#define GPIO_12_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_12_IRQ PORTD_IRQn
/* GPIO channel 13 config */
#define GPIO_13_DEV GPIOE /* DIO20; extension connecotr D14, USB OUT3V3 */
#define GPIO_13_PORT PORTE
#define GPIO_13_PORT_BASE PORTE_BASE
#define GPIO_13_PIN 18
#define GPIO_13_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_13_IRQ PORTE_IRQn
/* GPIO channel 14 config */
#define GPIO_14_DEV GPIOE /* DIO21; extension connecotr D15, USB VREGIN */
#define GPIO_14_PORT PORTE
#define GPIO_14_PORT_BASE PORTE_BASE
#define GPIO_14_PIN 19
#define GPIO_14_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
#define GPIO_14_IRQ PORTE_IRQn
/* GPIO channel 15 config */
#define GPIO_15_DEV GPIOA /* DIO24; extension connecotr D7 */
#define GPIO_15_PORT PORTA
#define GPIO_15_PORT_BASE PORTA_BASE
#define GPIO_15_PIN 1
#define GPIO_15_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
#define GPIO_15_IRQ PORTA_IRQn
/* GPIO channel 16 config */
#define GPIO_16_DEV GPIOA /* DIO25; extension connecotr D6 */
#define GPIO_16_PORT PORTA
#define GPIO_16_PORT_BASE PORTA_BASE
#define GPIO_16_PIN 2
#define GPIO_16_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
#define GPIO_16_IRQ PORTA_IRQn
/* GPIO channel 17 config */
#define GPIO_17_DEV GPIOA /* DIO28; extension connecotr D8 */
#define GPIO_17_PORT PORTA
#define GPIO_17_PORT_BASE PORTA_BASE
#define GPIO_17_PIN 18
#define GPIO_17_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
#define GPIO_17_IRQ PORTA_IRQn
/* GPIO channel 18 config */
#define GPIO_18_DEV GPIOD /* DIO8; extension connecotr D1; UART2_TX */
#define GPIO_18_PORT PORTD
#define GPIO_18_PORT_BASE PORTD_BASE
#define GPIO_18_PIN 3
#define GPIO_18_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define GPIO_18_IRQ PORTD_IRQn
/* GPIO channel 19 config */
#define GPIO_19_DEV GPIOC /* DIO2; extension connecotr D10; SPI0_CS0 */
#define GPIO_19_PORT PORTC
#define GPIO_19_PORT_BASE PORTC_BASE
#define GPIO_19_PIN 4
#define GPIO_19_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define GPIO_19_IRQ PORTC_IRQn
/* GPIO channel 20 config */
#define GPIO_20_DEV GPIOC /* DIO3; extension connecotr D13; SPI0_CLK */
#define GPIO_20_PORT PORTC
#define GPIO_20_PORT_BASE PORTC_BASE
#define GPIO_20_PIN 5
#define GPIO_20_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define GPIO_20_IRQ PORTC_IRQn
/* GPIO channel 21 config */
#define GPIO_21_DEV GPIOC /* DIO4; extension connecotr D11; SPI0_MOSI */
#define GPIO_21_PORT PORTC
#define GPIO_21_PORT_BASE PORTC_BASE
#define GPIO_21_PIN 6
#define GPIO_21_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define GPIO_21_IRQ PORTC_IRQn
/* GPIO channel 22 config */
#define GPIO_22_DEV GPIOC /* DIO5; extension connecotr D12; SPI0_MISO */
#define GPIO_22_PORT PORTC
#define GPIO_22_PORT_BASE PORTC_BASE
#define GPIO_22_PIN 7
#define GPIO_22_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define GPIO_22_IRQ PORTC_IRQn
/* GPIO channel 23 config */
#define GPIO_23_DEV KW2XDRF_GPIO
#define GPIO_23_PORT KW2XDRF_PORT
#define GPIO_23_PORT_BASE KW2XDRF_PORT_BASE
#define GPIO_23_PIN KW2XDRF_IRQ_PIN
#define GPIO_23_CLKEN() KW2XDRF_PORT_CLKEN()
#define GPIO_23_IRQ KW2XDRF_PORT_IRQn
#define GPIO_KW2XDRF GPIO_23
/* GPIO channel 24 config */
#define GPIO_24_DEV KW2XDRF_GPIO
#define GPIO_24_PORT KW2XDRF_PORT
#define GPIO_24_PORT_BASE KW2XDRF_PORT_BASE
#define GPIO_24_PIN KW2XDRF_PCS0_PIN
#define GPIO_24_CLKEN() KW2XDRF_PORT_CLKEN()
#define GPIO_24_IRQ KW2XDRF_PORT_IRQn
#define KW2XRF_CS_GPIO GPIO_24
#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/** @} */
/**

30
cpu/k60/include/cpu_conf.h
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@ -70,6 +70,14 @@ extern "C"
#define CPU_FLASH_BASE (0x00000000)
/** @} */
/**
* @name Length and address for reading CPU_ID (named UID in Freescale documents)
* @{
*/
#define CPUID_ID_LEN (16)
#define CPUID_ID_PTR ((void *)(&(SIM->UIDH)))
/** @} */
/**
* @name GPIO pin mux function numbers
*/
@ -86,12 +94,13 @@ extern "C"
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */
/**
* @name Length and address for reading CPU_ID (named UID in Freescale documents)
* @{
*/
#define CPUID_ID_LEN (16)
#define CPUID_ID_PTR ((void *)(&(SIM->UIDH)))
/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */
/**
@ -245,15 +254,6 @@ typedef enum llwu_wakeup_pin {
/** @} */
/** @name K60 PORT ISR names
* @{ */
#define ISR_PORT_A isr_porta_pin_detect
#define ISR_PORT_B isr_portb_pin_detect
#define ISR_PORT_C isr_portc_pin_detect
#define ISR_PORT_D isr_portd_pin_detect
#define ISR_PORT_E isr_porte_pin_detect
/** @} */
/**
* @name Bit band macros
* @{

20
cpu/k60/vector.c
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@ -139,11 +139,11 @@ WEAK_DEFAULT void isr_tsi(void);
WEAK_DEFAULT void isr_mcg(void);
WEAK_DEFAULT void isr_lptmr0(void);
/* void dummy_handler(void); */
WEAK_DEFAULT void isr_porta_pin_detect(void);
WEAK_DEFAULT void isr_portb_pin_detect(void);
WEAK_DEFAULT void isr_portc_pin_detect(void);
WEAK_DEFAULT void isr_portd_pin_detect(void);
WEAK_DEFAULT void isr_porte_pin_detect(void);
WEAK_DEFAULT void isr_porta(void);
WEAK_DEFAULT void isr_portb(void);
WEAK_DEFAULT void isr_portc(void);
WEAK_DEFAULT void isr_portd(void);
WEAK_DEFAULT void isr_porte(void);
/* void dummy_handler(void); */
/* void dummy_handler(void); */
WEAK_DEFAULT void isr_software(void);
@ -261,11 +261,11 @@ const void *interrupt_vector[] = {
(void*) isr_mcg,
(void*) isr_lptmr0,
(void*) dummy_handler,
(void*) isr_porta_pin_detect,
(void*) isr_portb_pin_detect,
(void*) isr_portc_pin_detect,
(void*) isr_portd_pin_detect,
(void*) isr_porte_pin_detect,
(void*) isr_porta,
(void*) isr_portb,
(void*) isr_portc,
(void*) isr_portd,
(void*) isr_porte,
(void*) dummy_handler,
(void*) dummy_handler,
(void*) isr_software, /* Vector 110 */

24
cpu/k64f/include/cpu_conf.h
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@ -56,6 +56,30 @@ extern "C"
*/
#define CPUID_ID_PTR ((void *)(&(SIM_UIDH)))
/**
* @name GPIO pin mux function numbers
*/
/** @{ */
#define PIN_MUX_FUNCTION_ANALOG 0
#define PIN_MUX_FUNCTION_GPIO 1
/** @} */
/**
* @name GPIO interrupt flank settings
*/
/** @{ */
#define PIN_INTERRUPT_RISING 0b1001
#define PIN_INTERRUPT_FALLING 0b1010
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */
/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */
/**
* @brief MCU specific Low Power Timer settings.

1889
cpu/kinetis_common/gpio.c
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63
cpu/kinetis_common/include/periph_cpu.h
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@ -25,7 +25,68 @@
extern "C" {
#endif
/* nothing to do here, yet */
/**
* @brief Overwrite the default gpio_t type definition
* @{
*/
#define HAVE_GPIO_T
typedef uint16_t gpio_t;
/** @} */
/**
* @brief Definition of a fitting UNDEF value
*/
#define GPIO_UNDEF (0xffff)
#define GPIO_PORT_SHIFT (8)
#define GPIO_PORT_MASK (0xff << (GPIO_PORT_SHIFT))
#define GPIO_PIN_SHIFT (0)
#define GPIO_PIN_MASK (0xff << (GPIO_PIN_SHIFT))
/**
* @brief Define a CPU specific GPIO pin generator macro
*/
#define GPIO_PIN(port, pin) ((port << GPIO_PORT_SHIFT) | pin)
/**
* @brief Override values for pull register configuration
* @{
*/
#define HAVE_GPIO_PP_T
typedef enum {
GPIO_NOPULL = 4, /**< do not use internal pull resistors */
GPIO_PULLUP = 9, /**< enable internal pull-up resistor */
GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */
} gpio_pp_t;
/** @} */
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_LOGIC_ZERO = 0x8, /**< interrupt on logic zero */
GPIO_RISING = 0x9, /**< emit interrupt on rising flank */
GPIO_FALLING = 0xa, /**< emit interrupt on falling flank */
GPIO_BOTH = 0xb, /**< emit interrupt on both flanks */
GPIO_LOGIC_ONE = 0xc, /**< interrupt on logic one */
} gpio_flank_t;
/** @} */
/**
* @brief Available ports on the Kinetis family
*/
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
PORT_NUMOF
};
#ifdef __cplusplus
}

29
cpu/kw2x/cpu.c
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@ -40,27 +40,32 @@ void cpu_init(void)
static inline void modem_clock_init(void)
{
SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK);
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK);
/* Use the CLK_OUT of the modem as the clock source. */
/* Enable GPIO clock gates */
KW2XDRF_PORT_CLKEN();
KW2XDRF_CLK_CTRL_CLKEN();
/* Modem RST_B is connected to PTB19 and can be used to reset the modem. */
PORTB->PCR[19] = PORT_PCR_MUX(1);
GPIOB->PDDR |= (1 << 19);
GPIOB->PCOR |= (1 << 19);
KW2XDRF_PORT_DEV->PCR[KW2XDRF_RST_PIN] = PORT_PCR_MUX(1);
BITBAND_REG32(KW2XDRF_GPIO->PDDR, KW2XDRF_RST_PIN) = 1;
KW2XDRF_GPIO->PCOR = (1 << KW2XDRF_RST_PIN);
/* Modem GPIO5 is connected to PTC0 and can be used to select CLK_OUT frequency, */
/* set PTC0 high for CLK_OUT=32.787kHz and low for CLK_OUT=4MHz. */
PORTC->PCR[0] = PORT_PCR_MUX(1);
GPIOC->PDDR |= (1 << 0);
GPIOC->PCOR |= (1 << 0);
KW2XDRF_CLK_CTRL_PORT_DEV->PCR[KW2XDRF_CLK_CTRL_PIN] = PORT_PCR_MUX(1);
BITBAND_REG32(KW2XDRF_CLK_CTRL_GPIO->PDDR, KW2XDRF_CLK_CTRL_PIN) = 1;
KW2XDRF_CLK_CTRL_GPIO->PCOR = (1 << KW2XDRF_CLK_CTRL_PIN);
/* Modem IRQ_B is connected to PTB3, modem interrupt request to the MCU. */
PORTB->PCR[KW2XDRF_IRQ_PIN] = PORT_PCR_MUX(1);
GPIOB->PDDR &= ~(1 << KW2XDRF_IRQ_PIN);
KW2XDRF_PORT_DEV->PCR[KW2XDRF_IRQ_PIN] = PORT_PCR_MUX(1);
BITBAND_REG32(KW2XDRF_GPIO->PDDR, KW2XDRF_IRQ_PIN) = 0;
/* release the reset */
GPIOB->PSOR |= (1 << 19);
KW2XDRF_GPIO->PSOR = (1 << KW2XDRF_RST_PIN);
/* wait for modem IRQ_B interrupt request */
while (GPIOB->PDIR & (1 << KW2XDRF_IRQ_PIN));
while (KW2XDRF_GPIO->PDIR & (1 << KW2XDRF_IRQ_PIN));
}
/**

40
cpu/kw2x/include/cpu_conf.h
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@ -61,6 +61,31 @@ extern "C"
*/
#define CPUID_ID_PTR ((void *)(&(SIM_UIDH)))
/**
* @name GPIO pin mux function numbers
*/
/** @{ */
#define PIN_MUX_FUNCTION_ANALOG 0
#define PIN_MUX_FUNCTION_GPIO 1
/** @} */
/**
* @name GPIO interrupt flank settings
*/
/** @{ */
#define PIN_INTERRUPT_RISING 0b1001
#define PIN_INTERRUPT_FALLING 0b1010
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */
/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */
/**
* @brief MCU specific Low Power Timer settings.
*/
@ -75,18 +100,25 @@ extern "C"
*
* @{
*/
#define KW2XDRF_PORT_BASE PORTB_BASE /**< MCU Port connected to Modem*/
#define KW2XDRF_PORT PORTB /**< MCU Port connected to Modem*/
#define KW2XDRF_PORT_DEV PORTB /**< MCU Port connected to Modem*/
#define KW2XDRF_PORT PORT_B /**< MCU Port connected to Modem*/
#define KW2XDRF_GPIO GPIOB /**< GPIO Device connected to Modem */
#define KW2XDRF_PORT_IRQn PORTB_IRQn
#define KW2XDRF_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK)) /**< Clock Enable for PORTB*/
/** Clock Enable for PORTB*/
#define KW2XDRF_PORT_CLKEN() (PORTB_CLOCK_GATE = 1)
#define KW2XDRF_PIN_AF 2 /**< Pin Muxing Parameter for GPIO Device*/
#define KW2XDRF_PCS0_PIN 10 /**< SPI Slave Select Pin */
#define KW2XDRF_SCK_PIN 11 /**< SPI Clock Output Pin */
#define KW2XDRF_SOUT_PIN 16 /**< SPI Master Data Output Pin */
#define KW2XDRF_SIN_PIN 17 /**< SPI Master Data Input Pin */
#define KW2XDRF_RST_PIN 19 /**< Reset pin */
#define KW2XDRF_IRQ_PIN 3 /**< Modem's IRQ Output (activ low) */
#define KW2XDRF_CLK_CTRL_PORT PORT_C /**< CLK_OUT control pin port */
#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC /**< CLK_OUT control pin PORT device */
#define KW2XDRF_CLK_CTRL_GPIO GPIOC /**< CLK_OUT control pin GPIO device */
#define KW2XDRF_CLK_CTRL_CLKEN() (PORTC_CLOCK_GATE = 1)
#define KW2XDRF_CLK_CTRL_PIN 0 /**< CLK_OUT control pin */
/** @} */
#ifdef __cplusplus

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