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boards: added support for nucleo144-f746

master
Hauke Petersen 6 years ago
parent
commit
17fedc7f4d
  1. 3
      boards/nucleo144-f746/Makefile
  2. 1
      boards/nucleo144-f746/Makefile.dep
  3. 12
      boards/nucleo144-f746/Makefile.features
  4. 6
      boards/nucleo144-f746/Makefile.include
  5. 32
      boards/nucleo144-f746/board.c
  6. 5
      boards/nucleo144-f746/dist/openocd.cfg
  7. 35
      boards/nucleo144-f746/include/board.h
  8. 147
      boards/nucleo144-f746/include/periph_conf.h

3
boards/nucleo144-f746/Makefile

@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

1
boards/nucleo144-f746/Makefile.dep

@ -0,0 +1 @@
include $(RIOTBOARD)/nucleo-common/Makefile.dep

12
boards/nucleo144-f746/Makefile.features

@ -0,0 +1,12 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/nucleo144-common/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m7

6
boards/nucleo144-f746/Makefile.include

@ -0,0 +1,6 @@
## the cpu to build for
export CPU = stm32f7
export CPU_MODEL = stm32f746zg
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/nucleo144-common/Makefile.include

32
boards/nucleo144-f746/board.c

@ -0,0 +1,32 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo144-f746
* @{
*
* @file
* @brief Board specific implementations for the nucleo144-f746 board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
gpio_init(LED0_PIN, GPIO_OUT);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_init(LED2_PIN, GPIO_OUT);
}

5
boards/nucleo144-f746/dist/openocd.cfg vendored

@ -0,0 +1,5 @@
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32f7x.cfg]

35
boards/nucleo144-f746/include/board.h

@ -0,0 +1,35 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo144-f746 Nucleo144-F746
* @ingroup boards
* @brief Board specific files for the nucleo144-f746 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo144-f746 board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef BOARD_H
#define BOARD_H
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

147
boards/nucleo144-f746/include/periph_conf.h

@ -0,0 +1,147 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo144-f746
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo144-f746 board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_D, 9),
.tx_pin = GPIO_PIN(PORT_D, 8),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 6,
.dma_chan = 4
#endif
},
{
.dev = USART6,
.rcc_mask = RCC_APB2ENR_USART6EN,
.rx_pin = GPIO_PIN(PORT_G, 9),
.tx_pin = GPIO_PIN(PORT_G, 14),
.rx_af = GPIO_AF8,
.tx_af = GPIO_AF8,
.bus = APB2,
.irqn = USART6_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 5,
.dma_chan = 4
#endif
},
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_D, 6),
.tx_pin = GPIO_PIN(PORT_D, 5),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 4,
.dma_chan = 4
#endif
}
};
#define UART_0_ISR (isr_usart3)
#define UART_0_DMA_ISR (isr_dma1_stream6)
#define UART_1_ISR (isr_usart6)
#define UART_1_DMA_ISR (isr_dma1_stream5)
#define UART_2_ISR (isr_usart2)
#define UART_2_DMA_ISR (isr_dma1_stream4)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */
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