Oleg Hahm
10 years ago
commit
1cc2767bb4
@ -0,0 +1,28 @@
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SRC = $(wildcard *.c)
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BINDIR = $(RIOTBOARD)/$(BOARD)/bin/
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OBJ = $(SRC:%.c=$(BINDIR)%.o)## defines
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DEP = $(SRC:%.c=$(BINDIR)%.d)
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export ARCH = mbed_lpc1768_base.a
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INCLUDES += -Iinclude/
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INCLUDES += -I$(RIOTCPU)/$(CPU)/include
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INCLUDES += -I$(RIOTBASE)/core/include
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all: $(BINDIR)$(ARCH)
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$(BINDIR)$(ARCH): $(OBJ)
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$(AR) rcs $(BINDIR)$(ARCH) $(OBJ)
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# pull in dependency info for *existing* .o files
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-include $(OBJ:.o=.d)
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# compile and generate dependency info
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$(BINDIR)%.o: %.c
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mkdir -p $(BINDIR)
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$(CC) $(CFLAGS) $(INCLUDES) $(BOARDINCLUDE) $(PROJECTINCLUDE) $(CPUINCLUDE) -c $*.c -o $(BINDIR)$*.o
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$(CC) $(CFLAGS) $(INCLUDES) $(BOARDINCLUDE) $(PROJECTINCLUDE) $(CPUINCLUDE) -MM $*.c > $(BINDIR)$*.d
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@printf "$(BINDIR)"|cat - $(BINDIR)$*.d > /tmp/riot_out && mv /tmp/riot_out $(BINDIR)$*.d
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# remove compilation products
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clean:
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rm -f $(OBJ) $(DEP)
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@ -0,0 +1,28 @@
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## the cpu to build for
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export CPU = lpc1768
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# toolchain config
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export PREFIX = arm-none-eabi-
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export CC = @$(PREFIX)gcc
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export AR = @$(PREFIX)ar
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export CFLAGS = -DUSE_STDPERIPH_DRIVER -ggdb -g3 -std=gnu99 -O0 -Wall -Wstrict-prototypes -mcpu=cortex-m3 $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
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export ASFLAGS = -ggdb -g3 -mcpu=cortex-m3 $(FPU_USAGE) -mlittle-endian
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export AS = $(PREFIX)as
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export LINK = $(PREFIX)gcc
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export SIZE = $(PREFIX)size
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export OBJCOPY = $(PREFIX)objcopy
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#LINKFLAGS = -g3 -ggdb -mcpu=cortex-m3 $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles -T$(RIOTCPU)/$(CPU)/LPC1768.ld
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LINKFLAGS = -mcpu=cortex-m3 -mthumb -Wl,--gc-sections,--cref -lc -lgcc -lnosys -T$(RIOTCPU)/$(CPU)/LPC1768.ld -nostartfiles
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ifeq ($(strip $(PORT)),)
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export PORT = /dev/ttyUSB0
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endif
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export HEXFILE = bin/$(PROJECT).hex
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export FFLAGS = $(HEXFILE)
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export ELFFILE = bin/$(PROJECT).elf
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export DEBUGGER_FLAGS = $(ELFFILE)
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INCLUDES += -Iinclude/
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INCLUDES += -I$(RIOTCPU)/$(CPU)/include
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export OFLAGS = -O binary
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@ -0,0 +1,569 @@
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/**************************************************************************//**
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* @file boards_init.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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* for the NXP LPC17xx Device Series
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* @version V1.09
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* @date 09. November 2013
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*
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* @note Integrated, adopted, and renamed for RIOT by Oliver Hahm.
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include <stdint.h>
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#include "board.h"
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#include "LPC17xx.h"
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Controls and Status Register (SCS)
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// <o1.4> OSCRANGE: Main Oscillator Range Select
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// <0=> 1 MHz to 20 MHz
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// <1=> 15 MHz to 24 MHz
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// <e1.5> OSCEN: Main Oscillator Enable
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// </e>
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// </h>
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//
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// <h> Clock Source Select Register (CLKSRCSEL)
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// <o2.0..1> CLKSRC: PLL Clock Source Selection
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// <0=> Internal RC oscillator
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// <1=> Main oscillator
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// <2=> RTC oscillator
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// </h>
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//
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// <e3> PLL0 Configuration (Main PLL)
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// <h> PLL0 Configuration Register (PLL0CFG)
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// <i> F_cco0 = (2 * M * F_in) / N
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// <i> F_in must be in the range of 32 kHz to 50 MHz
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// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
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// <o4.0..14> MSEL: PLL Multiplier Selection
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// <6-32768><#-1>
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// <i> M Value
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// <o4.16..23> NSEL: PLL Divider Selection
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// <1-256><#-1>
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// <i> N Value
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// </h>
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// </e>
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//
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// <e5> PLL1 Configuration (USB PLL)
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// <h> PLL1 Configuration Register (PLL1CFG)
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// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
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// <i> F_cco1 = F_osc * M * 2 * P
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// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
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// <o6.0..4> MSEL: PLL Multiplier Selection
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// <1-32><#-1>
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// <i> M Value (for USB maximum value is 4)
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// <o6.5..6> PSEL: PLL Divider Selection
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// <0=> 1
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// <1=> 2
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// <2=> 4
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// <3=> 8
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// <i> P Value
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// </h>
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// </e>
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//
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// <h> CPU Clock Configuration Register (CCLKCFG)
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// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
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// <1-256><#-1>
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// </h>
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//
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// <h> USB Clock Configuration Register (USBCLKCFG)
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// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
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// <0-15>
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// <i> Divide is USBSEL + 1
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// </h>
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//
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// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
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// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 6
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// </h>
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//
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// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
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// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
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// <0=> Pclk = Cclk / 4
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// <1=> Pclk = Cclk
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// <2=> Pclk = Cclk / 2
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// <3=> Pclk = Hclk / 8
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// </h>
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//
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// <h> Power Control for Peripherals Register (PCONP)
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// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
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// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
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// <o11.3> PCUART0: UART 0 power/clock enable
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// <o11.4> PCUART1: UART 1 power/clock enable
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// <o11.6> PCPWM1: PWM 1 power/clock enable
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// <o11.7> PCI2C0: I2C interface 0 power/clock enable
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// <o11.8> PCSPI: SPI interface power/clock enable
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// <o11.9> PCRTC: RTC power/clock enable
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// <o11.10> PCSSP1: SSP interface 1 power/clock enable
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// <o11.12> PCAD: A/D converter power/clock enable
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// <o11.13> PCCAN1: CAN controller 1 power/clock enable
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// <o11.14> PCCAN2: CAN controller 2 power/clock enable
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// <o11.15> PCGPIO: GPIOs power/clock enable
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// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
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// <o11.17> PCMC: Motor control PWM power/clock enable
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// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
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// <o11.19> PCI2C1: I2C interface 1 power/clock enable
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// <o11.21> PCSSP0: SSP interface 0 power/clock enable
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// <o11.22> PCTIM2: Timer 2 power/clock enable
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// <o11.23> PCTIM3: Timer 3 power/clock enable
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// <o11.24> PCUART2: UART 2 power/clock enable
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// <o11.25> PCUART3: UART 3 power/clock enable
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// <o11.26> PCI2C2: I2C interface 2 power/clock enable
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// <o11.27> PCI2S: I2S interface power/clock enable
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// <o11.29> PCGPDMA: GP DMA function power/clock enable
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// <o11.30> PCENET: Ethernet block power/clock enable
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// <o11.31> PCUSB: USB interface power/clock enable
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// </h>
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//
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// <h> Clock Output Configuration Register (CLKOUTCFG)
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// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
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// <0=> CPU clock
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// <1=> Main oscillator
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// <2=> Internal RC oscillator
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// <3=> USB clock
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// <4=> RTC oscillator
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// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
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// <1-16><#-1>
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// <o12.8> CLKOUT_EN: CLKOUT enable control
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// </h>
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//
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SCS_Val 0x00000020
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#define CLKSRCSEL_Val 0x00000001
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#define PLL0_SETUP 1
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#define PLL0CFG_Val 0x00050063
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#define PLL1_SETUP 1
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#define PLL1CFG_Val 0x00000023
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#define CCLKCFG_Val 0x00000003
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#define USBCLKCFG_Val 0x00000000
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#define PCLKSEL0_Val 0x00000000
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#define PCLKSEL1_Val 0x00000000
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#define PCONP_Val 0x042887DE
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#define CLKOUTCFG_Val 0x00000000
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/*--------------------- Flash Accelerator Configuration ----------------------
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//
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// <e> Flash Accelerator Configuration
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// <o1.12..15> FLASHTIM: Flash Access Time
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// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
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// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
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// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
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// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
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// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
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// <5=> 6 CPU clocks (for any CPU clock)
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// </e>
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*/
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#define FLASH_SETUP 1
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#define FLASHCFG_Val 0x00004000
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/*
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//-------- <<< end of configuration section >>> ------------------------------
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*/
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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/* Clock Configuration -------------------------------------------------------*/
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#if (CHECK_RSVD((SCS_Val), ~0x00000030))
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#error "SCS: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
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#error "CLKSRCSEL: Value out of range!"
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#endif
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#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
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#error "PLL0CFG: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
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#error "PLL1CFG: Invalid values of reserved bits!"
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#endif
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|
||||
#if (PLL0_SETUP) /* if PLL0 is used */
|
||||
#if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
|
||||
#error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
|
||||
#error "CCLKCFG: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
/* F_cco0 = (2 * M * F_in) / N */
|
||||
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
|
||||
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
|
||||
#define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
|
||||
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
|
||||
|
||||
/* Determine core clock frequency according to settings */
|
||||
#if (PLL0_SETUP)
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
|
||||
#endif
|
||||
#else
|
||||
#if ((CLKSRCSEL_Val & 0x03) == 1)
|
||||
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
|
||||
#elif ((CLKSRCSEL_Val & 0x03) == 2)
|
||||
#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
|
||||
#else
|
||||
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define BLINK_DELAY (1000000)
|
||||
|
||||
void loop_delay(uint32_t t)
|
||||
{
|
||||
for (uint32_t delay = 0; delay < t; delay++) {
|
||||
__asm("NOP");
|
||||
}
|
||||
}
|
||||
|
||||
void bl_blink(void)
|
||||
{
|
||||
LED_ON(1);
|
||||
LED_ON(2);
|
||||
LED_ON(3);
|
||||
LED_ON(4);
|
||||
loop_delay(BLINK_DELAY);
|
||||
LED_OFF(1);
|
||||
LED_OFF(2);
|
||||
LED_OFF(3);
|
||||
LED_OFF(4);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t system_clock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
void clock_update(void) /* Get Core Clock Frequency */
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
system_clock = (IRC_OSC *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF) + 1));
|
||||
break;
|
||||
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
system_clock = (OSC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF) + 1));
|
||||
break;
|
||||
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
system_clock = (RTC_CLK *
|
||||
((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
|
||||
((LPC_SC->CCLKCFG & 0xFF) + 1));
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Int. RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Int. RC */
|
||||
system_clock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF) + 1);
|
||||
break;
|
||||
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
system_clock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF) + 1);
|
||||
break;
|
||||
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
system_clock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF) + 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System.
|
||||
*/
|
||||
void board_init(void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
LPC_SC->SCS = SCS_Val;
|
||||
|
||||
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
|
||||
while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
|
||||
}
|
||||
|
||||
LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
|
||||
|
||||
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
|
||||
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
||||
|
||||
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
|
||||
|
||||
#if (PLL0_SETUP)
|
||||
LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
|
||||
while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
|
||||
|
||||
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
|
||||
while (!(LPC_SC->PLL0STAT & ((1 << 25) | (1 << 24)))); /* Wait for PLLC0_STAT & PLLE0_STAT */
|
||||
|
||||
#endif
|
||||
|
||||
#if (PLL1_SETUP)
|
||||
LPC_SC->PLL1CFG = PLL1CFG_Val;
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
|
||||
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
|
||||
while (!(LPC_SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */
|
||||
|
||||
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
|
||||
while (!(LPC_SC->PLL1STAT & ((1 << 9) | (1 << 8)))); /* Wait for PLLC1_STAT & PLLE1_STAT */
|
||||
|
||||
#else
|
||||
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
|
||||
#endif
|
||||
|
||||
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
||||
|
||||
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
||||
#endif
|
||||
|
||||
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
||||
LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
|
||||
#endif
|
||||
|
||||
/* Initialize LED pins */
|
||||
LPC_GPIO1->FIODIR |= PIN_LED1;
|
||||
LPC_GPIO1->FIODIR |= PIN_LED2;
|
||||
LPC_GPIO1->FIODIR |= PIN_LED3;
|
||||
LPC_GPIO1->FIODIR |= PIN_LED4;
|
||||
|
||||
bl_blink();
|
||||
}
|
||||
@ -0,0 +1,35 @@
|
||||
#ifndef __BOARD_H
|
||||
#define __BOARD_H
|
||||
|
||||
/**
|
||||
* @file boards.h
|
||||
* @author Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* @defgroup mbed_lpc1768 mbed NXP LPC1768 development kit
|
||||
* @ingroup boards
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "bitarithm.h"
|
||||
|
||||
#define PIN_LED1 (BIT18)
|
||||
#define PIN_LED2 (BIT20)
|
||||
#define PIN_LED3 (BIT21)
|
||||
#define PIN_LED4 (BIT23)
|
||||
|
||||
#define LED_ON(led_nr) (LPC_GPIO1->FIOSET = PIN_LED##led_nr)
|
||||
#define LED_OFF(led_nr) (LPC_GPIO1->FIOCLR = PIN_LED##led_nr)
|
||||
#define LED_TOGGLE(led_nr) (LPC_GPIO1->FIOPIN ^= PIN_LED##led_nr)
|
||||
|
||||
typedef uint8_t radio_packet_length_t;
|
||||
|
||||
/**
|
||||
* @brief Busy waiting function (while hwtimer is not available at boot time)
|
||||
*
|
||||
* @param[in] t The waiting cycles
|
||||
*/
|
||||
void loop_delay(uint32_t t);
|
||||
|
||||
/** @} */
|
||||
#endif /* __BOARD_H */
|
||||
@ -0,0 +1,56 @@
|
||||
/******************************************************************************
|
||||
* @file: system_LPC17xx.h
|
||||
* @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC17xx Device Series
|
||||
* @version: V1.03
|
||||
* @date: 09. November 2013
|
||||
*
|
||||
* @note: Integrated and adopted for RIOT by Oliver Hahm.
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@fu-berlin.de>
|
||||
*
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC17xx_H
|
||||
#define __SYSTEM_LPC17xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t system_clock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void board_init(void);
|
||||
|
||||
/**
|
||||
* Update system_clock variable
|
||||
*
|
||||
* @brief Updates the system_clock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void clock_update(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC17xx_H */
|
||||
@ -0,0 +1,154 @@
|
||||
/* Linker script for mbed LPC1768 */
|
||||
|
||||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
|
||||
RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
|
||||
|
||||
USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
|
||||
ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
__sidata = __etext;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
__heap_size = ORIGIN(RAM) + LENGTH(RAM) - . ;/*- __stack_size;*/
|
||||
.heap :
|
||||
{
|
||||
PROVIDE(__heap_start = .);
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
. = . + __heap_size;
|
||||
PROVIDE(__heap_max = .);
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
@ -0,0 +1,30 @@
|
||||
MODULE =cpu
|
||||
|
||||
OBJECTS = system_LPC17xx.o startup_LPC17xx.o main.o
|
||||
|
||||
CC_SYMBOLS = -DTARGET_LPC1769 -DTOOLCHAIN_GCC_ARM -DNDEBUG -D__CORTEX_M3
|
||||
|
||||
LD_FLAGS = -mcpu=cortex-m3 -mthumb -Wl,--gc-sections,-Map=$(PROJECT).map,--cref --specs=nano.specs
|
||||
LD_SYS_LIBS = -lc -lgcc -lnosys
|
||||
|
||||
INCLUDES = -Iinclude
|
||||
INCLUDES += -I$(RIOTBASE)/core/include -I$(RIOTBASE)/sys/include -I$(RIOTBASE)/sys/lib
|
||||
|
||||
all: $(BINDIR)$(MODULE).a
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
|
||||
clean::
|
||||
@for i in $(DIRS) ; do "$(MAKE)" -C $$i clean ; done ;
|
||||
|
||||
# This is needed for NXP Cortex M devices
|
||||
nxpsum:
|
||||
$(CCLOCAL) nxpsum.c -std=c99 -o nxpsum
|
||||
|
||||
#$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
|
||||
# $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $(addprefix $(BUILD_DIR), $^) $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
|
||||
|
||||
$(PROJECT).bin: $(PROJECT).elf nxpsum
|
||||
$(OBJCOPY) -O binary $< $@
|
||||
# Compute nxp checksum on .bin file here
|
||||
./nxpsum $@
|
||||
@ -0,0 +1,167 @@
|
||||
/**
|
||||
* CPU speficic RIOT kernel function for NXP LPC1768
|
||||
*
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* This file subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*
|
||||
* @ingroup lpc1768
|
||||
* @{
|
||||
* @file atom.c
|
||||
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
|
||||
* @author Oliver Hahm <oliver.hahm@inria.fr>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "sched.h"
|
||||
#include "cpu.h"
|
||||
#include "irq.h"
|
||||
|
||||
extern void sched_task_exit(void);
|
||||
void sched_task_return(void);
|
||||
|
||||
unsigned int atomic_set_return(unsigned int* p, unsigned int uiVal) {
|
||||
//unsigned int cspr = disableIRQ(); //crashes
|
||||
dINT();
|
||||
unsigned int uiOldVal = *p;
|
||||
*p = uiVal;
|
||||
//restoreIRQ(cspr); //crashes
|
||||
eINT();
|
||||
return uiOldVal;
|
||||
}
|
||||
|
||||
void cpu_switch_context_exit(void){
|
||||
sched_run();
|
||||
sched_task_return();
|
||||
}
|
||||
|
||||
|
||||
void thread_yield(void) {
|
||||
asm("svc 0x01\n");
|
||||
}
|
||||
|
||||
|
||||
__attribute__((naked))
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
save_context();
|
||||
asm("bl sched_run");
|
||||
/* call scheduler update active_thread variable with pdc of next thread
|
||||
* the thread that has higest priority and is in PENDING state */
|
||||
restore_context();
|
||||
}
|
||||
|
||||
/* kernel functions */
|
||||
void ctx_switch(void)
|
||||
{
|
||||
/* Save return address on stack */
|
||||
/* stmfd sp!, {lr} */
|
||||
|
||||
/* disable interrupts */
|
||||
/* mov lr, #NOINT|SVCMODE */
|
||||
/* msr CPSR_c, lr */
|
||||
/* cpsid i */
|
||||
|
||||
/* save other register */
|
||||
asm("nop");
|
||||
|
||||
asm("mov r12, sp");
|
||||
asm("stmfd r12!, {r4-r11}");
|
||||
|
||||
/* save user mode stack pointer in *active_thread */
|
||||
asm("ldr r1, =active_thread"); /* r1 = &active_thread */
|
||||
asm("ldr r1, [r1]"); /* r1 = *r1 = active_thread */
|
||||
asm("str r12, [r1]"); /* store stack pointer in tasks pdc*/
|
||||
|
||||
sched_task_return();
|
||||
}
|
||||
/* call scheduler so active_thread points to the next task */
|
||||
void sched_task_return(void)
|
||||
{
|
||||
/* load pdc->stackpointer in r0 */
|
||||
asm("ldr r0, =active_thread"); /* r0 = &active_thread */
|
||||
asm("ldr r0, [r0]"); /* r0 = *r0 = active_thread */
|
||||
asm("ldr sp, [r0]"); /* sp = r0 restore stack pointer*/
|
||||
asm("pop {r4}"); /* skip exception return */
|
||||
asm(" pop {r4-r11}");
|
||||
asm(" pop {r0-r3,r12,lr}"); /* simulate register restor from stack */
|
||||
// asm("pop {r4}"); /*foo*/
|
||||
asm("pop {pc}");
|
||||
}
|
||||
/*
|
||||
* cortex m4 knows stacks and handles register backups
|
||||
*
|
||||
* so use different stack frame layout
|
||||
*
|
||||
*
|
||||
* with float storage
|
||||
* ------------------------------------------------------------------------------------------------------------------------------------
|
||||
* | R0 | R1 | R2 | R3 | LR | PC | xPSR | S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | S10 | S11 | S12 | S13 | S14 | S15 | FPSCR |
|
||||
* ------------------------------------------------------------------------------------------------------------------------------------
|
||||
*
|
||||
* without
|
||||
*
|
||||
* --------------------------------------
|
||||
* | R0 | R1 | R2 | R3 | LR | PC | xPSR |
|
||||
* --------------------------------------
|
||||
*
|
||||
*
|
||||
*/
|
||||
char * thread_stack_init(void * task_func, void * stack_start, int stack_size ) {
|
||||
unsigned int * stk;
|
||||
stk = (unsigned int *) (stack_start + stack_size);
|
||||
|
||||
/* marker */
|
||||
stk--;
|
||||
*stk = 0x77777777;
|
||||
|
||||
//FIXME FPSCR
|
||||
stk--;
|
||||
*stk = (unsigned int) 0;
|
||||
|
||||
//S0 - S15
|
||||
for (int i = 15; i >= 0; i--) {
|
||||
stk--;
|
||||
*stk = i;
|
||||
}
|
||||
|
||||
//FIXME xPSR
|
||||
stk--;
|
||||
*stk = (unsigned int) 0x01000200;
|
||||
|
||||
//program counter
|
||||
stk--;
|
||||
*stk = (unsigned int) task_func;
|
||||
|
||||
/* link register */
|
||||
stk--;
|
||||
*stk = (unsigned int) 0x0;
|
||||
|
||||
/* r12 */
|
||||
stk--;
|
||||
*stk = (unsigned int) 0;
|
||||
|
||||
/* r0 - r3 */
|
||||
for (int i = 3; i >= 0; i--) {
|
||||
stk--;
|
||||
*stk = i;
|
||||
}
|
||||
|
||||
/* r11 - r4 */
|
||||
for (int i = 11; i >= 4; i--) {
|
||||
stk--;
|
||||
*stk = i;
|
||||
}
|
||||
|
||||
/* foo */
|
||||
/*stk--;
|
||||
*stk = (unsigned int) 0xDEADBEEF;*/
|
||||
|
||||
/* lr means exception return code */
|
||||
stk--;
|
||||
*stk = (unsigned int) 0xfffffff9; // return to taskmode main stack pointer
|
||||
|
||||
return (char*) stk;
|
||||
}
|
||||
@ -0,0 +1,108 @@
|
||||
/**
|
||||
* CPU specific functions for the RIOT scheduler on NXP LPC1768
|
||||
*
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* This file subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*
|
||||
* @file cpu.c
|
||||
* @author Kaspar Schleiser <kaspar.schleiser@fu-berlin.de>
|
||||
* @author Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "cpu.h"
|
||||
|
||||
#define ENABLE_DEBUG (0)
|
||||
#include "debug.h"
|
||||
|
||||
int inISR(void)
|
||||
{
|
||||
return (__get_IPSR() & 0xFF);
|
||||
}
|
||||
|
||||
unsigned int disableIRQ(void)
|
||||
{
|
||||
// FIXME PRIMASK is the old CPSR (FAULTMASK ??? BASEPRI ???)
|
||||
//PRIMASK lesen
|
||||
unsigned int uiPriMask = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
return uiPriMask;
|
||||
}
|
||||
|
||||
void restoreIRQ(unsigned oldPRIMASK)
|
||||
{
|
||||
//PRIMASK lesen setzen
|
||||
__set_PRIMASK(oldPRIMASK);
|
||||
}
|
||||
|
||||
|
||||
__attribute__((naked))
|
||||
void HardFault_Handler(void) {
|
||||
DEBUG("HARD FAULT\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
__attribute__((naked))
|
||||
void BusFault_Handler(void) {
|
||||
DEBUG("BusFault_Handler\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
__attribute__((naked))
|
||||
void Usage_Handler(void) {
|
||||
DEBUG("Usage FAULT\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
__attribute__((naked))
|
||||
void WWDG_Handler(void) {
|
||||
DEBUG("WWDG FAULT\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void dINT(void)
|
||||
{
|
||||
__disable_irq();
|
||||
}
|
||||
|
||||
void eINT(void)
|
||||
{
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
void save_context(void)
|
||||
{
|
||||
/* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
|
||||
asm("push {r4-r11}");
|
||||
/* save unsaved registers */
|
||||
asm("push {LR}");
|
||||
/* save exception return value */
|
||||
|
||||
asm("ldr r1, =active_thread");
|
||||
/* load address of currend pdc */
|
||||
asm("ldr r1, [r1]");
|
||||
/* deref pdc */
|
||||
asm("str sp, [r1]");
|
||||
/* write sp to pdc->sp means current threads stack pointer */
|
||||
}
|
||||
|
||||
void restore_context(void)
|
||||
{
|
||||
asm("ldr r0, =active_thread");
|
||||
/* load address of currend pdc */
|
||||
asm("ldr r0, [r0]");
|
||||
/* deref pdc */
|
||||
asm("ldr sp, [r0]");
|
||||
/* load pdc->sp to sp register */
|
||||
|
||||
asm("pop {r0}");
|
||||
/* restore exception retrun value from stack */
|
||||
asm("pop {r4-r11}");
|
||||
/* load unloaded register */
|
||||
// asm("pop {r4}"); /*foo*/
|
||||
asm("bx r0"); /* load exception return value to pc causes end of exception*/
|
||||
/* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,13 @@
|
||||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC1768 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "LPC17xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,617 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V3.02
|
||||
* @date 24. May 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||