Merge pull request #2059 from jfischer-phytec-iot/wip@mkw2xd
RIOT port for the MKW22D512 SiP and Phytec PBA-D-01 PhyWave Evaluations-Boarddev/timer
Johann Fischer
8 years ago
commit
1d46291d49
@ -0,0 +1,4 @@
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# tell the Makefile.base which module to build
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MODULE = $(BOARD)_base
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include $(RIOTBASE)/Makefile.base
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@ -0,0 +1,10 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_random
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FEATURES_PROVIDED += periph_cpuid
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@ -0,0 +1,51 @@
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# define the cpu used by the phyWAVE-KW22 board
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export CPU = kw2x
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export CPU_MODEL = kw21d256
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#export CPU_MODEL = kw21d512
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#export CPU_MODEL = kw22d512
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#define the default port depending on the host OS
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OS := $(shell uname)
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ifeq ($(OS),Linux)
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PORT ?= /dev/ttyACM0
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else ifeq ($(OS),Darwin)
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PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
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else
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$(info CAUTION: No flash tool for your host system found!)
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endif
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export PORT
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# define tools used for building the project
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export PREFIX = arm-none-eabi-
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export CC = $(PREFIX)gcc
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export AR = $(PREFIX)ar
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export AS = $(PREFIX)as
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export LINK = $(PREFIX)gcc
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export SIZE = $(PREFIX)size
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export OBJCOPY = $(PREFIX)objcopy
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export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm
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export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/flash.sh
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export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
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export RESET = $(RIOTBOARD)/$(BOARD)/dist/reset.sh
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export DEBUGSERVER = openocd
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# define build specific options
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CPU_USAGE = -mcpu=cortex-m4
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FPU_USAGE =
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export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
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export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
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export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
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export LINKFLAGS += -g3 -ggdb -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
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export LINKFLAGS += -T$(LINKERSCRIPT)
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export OFLAGS = -O binary
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export FFLAGS = $(HEXFILE)
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export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(ELFFILE)
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export TERMFLAGS = -p $(PORT)
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# use newLib nano-specs if available
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ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
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export LINKFLAGS += -specs=nano.specs -lc -lnosys
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endif
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# export board specific includes to the global includes-listing
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export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include
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@ -0,0 +1,54 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2014 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_pba-d-01
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* @{
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*
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* @file
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* @brief Board specific implementations for the Phytec PBA-D-01
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* evaluation board for PWA-A-002 Module
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*
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* @author Johann Fischer <j.fischer@phytec.de>
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*
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* @}
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*/
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#include "board.h"
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static void leds_init(void);
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void board_init(void)
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{
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leds_init();
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cpu_init();
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}
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/**
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* @brief Initialize the boards on-board RGB-LED
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*
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*/
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static void leds_init(void)
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{
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/* enable clock */
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LED_B_PORT_CLKEN();
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LED_G_PORT_CLKEN();
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LED_R_PORT_CLKEN();
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/* configure pins as gpio */
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LED_B_PORT->PCR[LED_B_PIN] = PORT_PCR_MUX(1);
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LED_G_PORT->PCR[LED_G_PIN] = PORT_PCR_MUX(1);
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LED_R_PORT->PCR[LED_R_PIN] = PORT_PCR_MUX(1);
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LED_B_GPIO->PDDR |= (1 << LED_B_PIN);
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LED_G_GPIO->PDDR |= (1 << LED_G_PIN);
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LED_R_GPIO->PDDR |= (1 << LED_R_PIN);
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/* turn all LEDs off */
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LED_B_GPIO->PSOR |= (1 << LED_B_PIN);
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LED_G_GPIO->PSOR |= (1 << LED_G_PIN);
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LED_R_GPIO->PSOR |= (1 << LED_R_PIN);
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}
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@ -0,0 +1,38 @@
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#!/bin/bash
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# Based on iot-lab_M3 debug.sh script.
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# Author: Jonas Remmert j.remmert@phytec.de
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red='\033[0;31m'
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green='\033[0;32m'
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NC='\033[0m'
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openocd -f "$RIOTBASE/boards/pba-d-01-kw2x/dist/mkw22d512.cfg" \ #"${RIOTBOARD}/${BOARD}/dist/mkw22d512.cfg" \
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-c "tcl_port 6333" \
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-c "telnet_port 4444" \
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-c "init" \
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-c "targets" \
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-c "reset halt" \
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-l /dev/null &
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# save pid to terminate afterwards
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OCD_PID=$?
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# needed for openocd to set up
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sleep 1
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retval=$(arm-none-eabi-readelf -x .fcfield $2 | awk '/0x00000400/ {print $2 $3 $4 $5}')
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unlocked_fcfield="fffffffffffffffffffffffffeffffff"
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if [ "$retval" == "$unlocked_fcfield" ]; then
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echo -e "Flash configuration tested...${green} [OK]${NC}"
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arm-none-eabi-gdb -tui --command=${1} ${2}
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#cgdb -d arm-none-eabi-gdb --command=${1} ${2}
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else
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echo "Hexdump, .fcfield of $2"
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retval=$(arm-none-eabi-readelf -x .fcfield $2)
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echo $retval
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echo -e "Fcfield not fitting to MKW22Dxxx, danger of bricking the device during flash...${red} [ABORT]${NC}"
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fi
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kill ${OCD_PID}
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@ -0,0 +1,52 @@
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#!/bin/bash
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# Based on iot-lab_M3 debug.sh script.
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# Author: Jonas Remmert j.remmert@phytec.de
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elffile=`echo $1 | sed 's/.hex/.elf/'`
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red='\033[0;31m'
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green='\033[0;32m'
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NC='\033[0m'
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echo The file: $elffile will be flashed to the board: $BOARD .
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#echo Press y to proceed, v to proceed with verify or any other key to abort.
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#read x
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retval=$(arm-none-eabi-readelf -x .fcfield $elffile | awk '/0x00000400/ {print $2 $3 $4 $5}')
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unlocked_fcfield="fffffffffffffffffffffffffeffffff"
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if [ "$retval" != "$unlocked_fcfield" ]; then
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echo "Hexdump, .fcfield of $elffile"
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retval=$(arm-none-eabi-readelf -x .fcfield $elffile)
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echo $retval
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echo -e "Fcfield not fitting to MKW2xDxxx, danger of bricking the device during flash...${red} [ABORT]${NC}"
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exit 0
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fi
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echo -e "Flash configuration tested...${green} [OK]${NC}"
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# flash without verify
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#if [ $x = "y" ] || [ $x = "v" ];# -o $x -eq v ];
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#then
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echo -e "${red}Flashing device, do not disconnect or reset the target until this script exits!!!${NC}"
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openocd -f "$RIOTBASE/boards/pba-d-01-kw2x/dist/mkw22d512.cfg" \
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-c "init" \
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-c "reset halt" \
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-c "flash write_image erase $elffile" \
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-c "reset run" \
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-c "exit"
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#fi
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# verify
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#if [ "$x" = "v" ];
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#then
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#echo -e "${red}Flashing device, do not disconnect or reset the target until this script exits!!!${NC}"
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#openocd -f "$RIOTBASE/boards/pba-d-01-kw2x/dist/mkw22d512.cfg" \
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# -c "init" \
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# -c "reset halt" \
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# -c "verify_image $elffile" \
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# -c "reset run" \
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# -c "exit"
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#fi
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echo -e "${green}done...${NC}"
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@ -0,0 +1,4 @@
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target remote localhost:3333
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monitor reset halt
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set print pretty
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set arm force-mode thumb
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@ -0,0 +1,71 @@
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#
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# Freescale Kinetis kw2xdxxx devices
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#
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source [find interface/cmsis-dap.cfg]
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#
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# K21 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME kw22d512
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}
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# Work-area is a space in RAM used for flash programming
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set WORKAREASIZE 0x4000
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x2ba01477
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}
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set _TARGETNAME $_CHIPNAME.cpu
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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#swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
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$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
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# It is important that "kinetis mdm check_security" is called for
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# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
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# causes "kinetis mdm check_security" to fail the first time openocd
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# calls it when it tries to connect after the CPU has been power-cycled.
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$_CHIPNAME.cpu configure -event examine-end {
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kinetis mdm check_security
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}
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
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#reset_config srst_only srst_nogate connect_assert_srst
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adapter_khz 1000
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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adapter_khz 24000
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}
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@ -0,0 +1,74 @@
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1;
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# not a function file:
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F = [2405:5:2480];
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i = 1;
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PLL_INT0 = [];
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PLL_FRAC0 = [];
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tmp_frac = 0;
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tmp_int = 11;
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while (i <= length(F))
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tmp_frac = (F(i)./32 - tmp_int - 64).*65536;
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if tmp_frac >= 65536
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tmp_int++;
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else
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PLL_FRAC0 = [PLL_FRAC0 tmp_frac];
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PLL_INT0 = [PLL_INT0 tmp_int];
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i++;
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endif
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endwhile
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%F
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%Fcalc = ((PLL_INT0 + 64) + (PLL_FRAC0./65536)).*32
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%PLL_INT0
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%PLL_FRAC0
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printf("static const uint8_t pll_int_lt[%d] = {\n", length(F));
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for i = 1:4:length(F)
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printf(" ");
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printf("%d,", PLL_INT0(i:1:i+3));
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printf("\n");
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endfor
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printf("};\n");
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printf("\n");
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printf("static const uint16_t pll_frac_lt[%d] = {\n", length(F));
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for i = 1:4:length(F)
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printf(" ");
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printf("%d,", PLL_FRAC0(i:1:i+3));
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printf("\n");
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endfor
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printf("};\n\n");
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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POWER_MAX=8;
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POWER_MIN=-35;
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RANGE_MAX=31;
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RANGE_MIN=3;
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i = [0:1:abs(diff([POWER_MAX POWER_MIN]))];
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pow_lt = round(i .* (RANGE_MAX - RANGE_MIN) ./ length(i) + RANGE_MIN);
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printf("static const uint8_t pow_lt[%d] = {", length(pow_lt));
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printf(" ");
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for i = 0:1:length(pow_lt)-1
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if (rem(i,4) == 0)
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printf("\n ");
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endif
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printf("%d,", pow_lt(i+1));
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endfor
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printf("\n};\n\n");
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i = [0:1:abs(diff([RANGE_MAX RANGE_MIN]))];
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level_lt = round(i .* (POWER_MAX - POWER_MIN) ./ length(i) + POWER_MIN);
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length(level_lt)
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printf("static const int level_lt[%d] = {", length(level_lt));
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for i = 0:1:length(level_lt)-1
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if (rem(i,4) == 0)
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printf("\n ");
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endif
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printf("%d,", level_lt(i+1));
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endfor
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printf("\n};\n\n");
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@ -0,0 +1,6 @@
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#!/bin/bash
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openocd -f "$RIOTBASE/boards/pba-d-01-kw2x/dist/mkw22d512.cfg" \
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-c "init" \
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-c "reset run" \
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-c "shutdown"
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@ -0,0 +1,103 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
|
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* Public License v2.1. See the file LICENSE in the top level directory for more
|
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* details.
|
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*/
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/**
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* @defgroup board_phywave_eval phyWAVE-KW22 Board
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* @ingroup boards
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* @brief Board specific implementations for the phyWAVE evaluation board
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* @{
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*
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* @file
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* @brief Board specific definitions for the phyWAVE evaluation board
|
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*
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* @author Johann Fischer <j.fischer@phytec.de>
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*/
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#ifndef __BOARD_H
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#define __BOARD_H
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* Define the nominal CPU core clock in this board
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*/
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#define F_CPU CLOCK_CORECLOCK
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/**
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* @name Define UART device and baudrate for stdio
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* @{
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*/
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#define STDIO UART_0
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#define STDIO_RX_BUFSIZE (64U)
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#define STDIO_BAUDRATE (115200U)
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/** @} */
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/**
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* @name LED pin definitions
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* @{
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*/
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#define LED_R_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK)) /**< Clock Enable for PORTD*/
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#define LED_G_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK)) /**< Clock Enable for PORTD*/
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#define LED_B_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK)) /**< Clock Enable for PORTA*/
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#define LED_R_PORT PORTD /**< PORT for Red LED*/
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#define LED_R_GPIO GPIOD /**< GPIO-Device for Red LED*/
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#define LED_G_PORT PORTD /**< PORT for Green LED*/
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#define LED_G_GPIO GPIOD /**< GPIO-Device for Green LED*/
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#define LED_B_PORT PORTA /**< PORT for Blue LED*/
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#define LED_B_GPIO GPIOA /**< GPIO-Device for Blue LED*/
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#define LED_R_PIN 6 /**< Red LED connected to PINx*/
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#define LED_G_PIN 4 /**< Green LED connected to PINx*/
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#define LED_B_PIN 4 /**< Blue LED connected to PINx*/
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/** @} */
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LED_B_ON (LED_B_GPIO->PCOR |= (1 << LED_B_PIN))
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#define LED_B_OFF (LED_B_GPIO->PSOR |= (1 << LED_B_PIN))
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#define LED_B_TOGGLE (LED_B_GPIO->PTOR |= (1 << LED_B_PIN))
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#define LED_G_ON (LED_G_GPIO->PCOR |= (1 << LED_G_PIN))
|
||||
#define LED_G_OFF (LED_G_GPIO->PSOR |= (1 << LED_G_PIN))
|
||||
#define LED_G_TOGGLE (LED_G_GPIO->PTOR |= (1 << LED_G_PIN))
|
||||
#define LED_R_ON (LED_R_GPIO->PCOR |= (1 << LED_R_PIN))
|
||||
#define LED_R_OFF (LED_R_GPIO->PSOR |= (1 << LED_R_PIN))
|
||||
#define LED_R_TOGGLE (LED_R_GPIO->PTOR |= (1 << LED_R_PIN))
|
||||
|
||||
/* for compatability to other boards */
|
||||
#define LED_GREEN_ON LED_G_ON
|
||||
#define LED_GREEN_OFF LED_G_OFF
|
||||
#define LED_GREEN_TOGGLE LED_G_TOGGLE
|
||||
#define LED_RED_ON LED_R_ON
|
||||
#define LED_RED_OFF LED_R_OFF
|
||||
#define LED_RED_TOGGLE LED_R_TOGGLE
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Define the type for the radio packet length for the transceiver
|
||||
*/
|
||||
typedef uint8_t radio_packet_length_t;
|
||||
|
||||
/**
|
||||
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
|
||||
*/
|
||||
void board_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /** __BOARD_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,557 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freie Universität Berlin
|
||||
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup board_pba-d-01-kw2x
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @name Peripheral MCU configuration for the phyWAVE-KW22 Board
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Johann Fischer <j.fischer@phytec.de>
|
||||
* @author Jonas Remmert <j.remmert@phytec.de>
|
||||
*/
|
||||
|
||||
#ifndef __PERIPH_CONF_H
|
||||
#define __PERIPH_CONF_H
|
||||
|
||||
#include "cpu-conf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock system configuration
|
||||
* @{
|
||||
*/
|
||||
#define KINETIS_CPU_USE_MCG 1
|
||||
|
||||
#define KINETIS_MCG_USE_ERC 1
|
||||
#define KINETIS_MCG_USE_PLL 1
|
||||
#define KINETIS_MCG_DCO_RANGE (24000000U)
|
||||
#define KINETIS_MCG_ERC_OSCILLATOR 0
|
||||
#define KINETIS_MCG_ERC_FRDIV 2
|
||||
#define KINETIS_MCG_ERC_RANGE 1
|
||||
#define KINETIS_MCG_ERC_FREQ 4000000
|
||||
#define KINETIS_MCG_PLL_PRDIV 1
|
||||
#define KINETIS_MCG_PLL_VDIV0 0
|
||||
#define KINETIS_MCG_PLL_FREQ 48000000
|
||||
|
||||
#define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name Timer configuration
|
||||
* @{
|
||||
*/
|
||||
#define TIMER_NUMOF (1U)
|
||||
#define TIMER_0_EN 1
|
||||
#define TIMER_1_EN 0
|
||||
#define TIMER_IRQ_PRIO 1
|
||||
#define TIMER_DEV PIT
|
||||
#define TIMER_MAX_VALUE (0xffffffff)
|
||||
#define TIMER_CLOCK CLOCK_CORECLOCK
|
||||
#define TIMER_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_PIT_MASK))
|
||||
|
||||
/* Timer 0 configuration */
|
||||
#define TIMER_0_PRESCALER_CH 0
|
||||
#define TIMER_0_COUNTER_CH 1
|
||||
#define TIMER_0_ISR isr_pit1
|
||||
#define TIMER_0_IRQ_CHAN PIT1_IRQn
|
||||
|
||||
/* Timer 1 configuration */
|
||||
#define TIMER_1_PRESCALER_CH 2
|
||||
#define TIMER_1_COUNTER_CH 3
|
||||
#define TIMER_1_ISR isr_pit3
|
||||
#define TIMER_1_IRQ_CHAN PIT3_IRQn
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
*/
|
||||
#define UART_NUMOF (1U)
|
||||
#define UART_0_EN 1
|
||||
#define UART_1_EN 0
|
||||
#define UART_IRQ_PRIO 1
|
||||
#define UART_CLK (48e6)
|
||||
|
||||
/* UART 0 device configuration */
|
||||
#define KINETIS_UART UART_Type
|
||||
#define UART_0_DEV UART2
|
||||
#define UART_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART2_MASK))
|
||||
#define UART_0_CLK UART_CLK
|
||||
#define UART_0_IRQ_CHAN UART2_RX_TX_IRQn
|
||||
#define UART_0_ISR isr_uart2_rx_tx
|
||||
/* UART 0 pin configuration */
|
||||
#define UART_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define UART_0_PORT PORTD
|
||||
#define UART_0_RX_PIN 2
|
||||
#define UART_0_TX_PIN 3
|
||||
#define UART_0_AF 3
|
||||
|
||||
/* UART 1 device configuration */
|
||||
#define UART_1_DEV UART0
|
||||
#define UART_1_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART0_MASK))
|
||||
#define UART_1_CLK UART_CLK
|
||||
#define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
|
||||
#define UART_1_ISR isr_uart0_rx_tx
|
||||
/* UART 1 pin configuration */
|
||||
#define UART_1_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define UART_1_PORT PORTD
|
||||
#define UART_1_RX_PIN 6
|
||||
#define UART_1_TX_PIN 7
|
||||
#define UART_1_AF 3
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
* @{
|
||||
*/
|
||||
#define ADC_NUMOF (1U)
|
||||
#define ADC_0_EN 1
|
||||
#define ADC_MAX_CHANNELS 6
|
||||
|
||||
/* ADC 0 configuration */
|
||||
#define ADC_0_DEV ADC0
|
||||
#define ADC_0_MODULE_CLOCK CLOCK_CORECLOCK
|
||||
#define ADC_0_CHANNELS 6
|
||||
#define ADC_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_ADC0_MASK))
|
||||
#define ADC_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_ADC0_MASK))
|
||||
#define ADC_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK))
|
||||
/* ADC 0 channel 0 pin config */
|
||||
#define ADC_0_CH0 1
|
||||
#define ADC_0_CH0_PIN 2
|
||||
#define ADC_0_CH0_PIN_AF 0
|
||||
#define ADC_0_CH0_PORT PORTE
|
||||
/* ADC 0 channel 1 pin config */
|
||||
#define ADC_0_CH1 1 /* PTE3 uses the same ADC_CH as PTE2, in single channel mode only one of them can be selected */
|
||||
#define ADC_0_CH1_PIN 3
|
||||
#define ADC_0_CH1_PIN_AF 0
|
||||
#define ADC_0_CH1_PORT PORTE
|
||||
/* ADC 0 channel 2 pin config */
|
||||
#define ADC_0_CH2 22
|
||||
#define ADC_0_CH2_PIN 7
|
||||
#define ADC_0_CH2_PIN_AF 0
|
||||
#define ADC_0_CH2_PORT PORTD
|
||||
/* ADC 0 channel 3 pin config */
|
||||
#define ADC_0_CH3 6
|
||||
#define ADC_0_CH3_PIN 5
|
||||
#define ADC_0_CH3_PIN_AF 0
|
||||
#define ADC_0_CH3_PORT PORTD
|
||||
/* ADC 0 channel 4 pin config */
|
||||
#define ADC_0_CH4 10
|
||||
#define ADC_0_CH4_PIN 0
|
||||
#define ADC_0_CH4_PIN_AF 0
|
||||
#define ADC_0_CH4_PORT PORTE
|
||||
/* ADC 0 channel 5 pin config */
|
||||
#define ADC_0_CH5 11
|
||||
#define ADC_0_CH5_PIN 1
|
||||
#define ADC_0_CH5_PIN_AF 0
|
||||
#define ADC_0_CH5_PORT PORTE
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name PWM configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWM_NUMOF (1U)
|
||||
#define PWM_0_EN 1
|
||||
#define PWM_MAX_CHANNELS 4
|
||||
|
||||
/* PWM 0 device configuration */
|
||||
#define PWM_0_DEV FTM0
|
||||
#define PWM_0_CHANNELS 3
|
||||
#define PWM_0_CLK (48e6)
|
||||
#define PWM_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_FTM0_MASK))
|
||||
#define PWM_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_FTM0_MASK))
|
||||
/* PWM 0 pin configuration */
|
||||
#define PWM_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTA_MASK))
|
||||
|
||||
#define PWM_0_PIN_CH0 4
|
||||
#define PWM_0_FTMCHAN_CH0 1
|
||||
#define PWM_0_PORT_CH0 PORTA
|
||||
#define PWM_0_PIN_AF_CH0 3
|
||||
|
||||
#define PWM_0_PIN_CH1 4
|
||||
#define PWM_0_FTMCHAN_CH1 4
|
||||
#define PWM_0_PORT_CH1 PORTD
|
||||
#define PWM_0_PIN_AF_CH1 4
|
||||
|
||||
#define PWM_0_PIN_CH2 6
|
||||
#define PWM_0_FTMCHAN_CH2 6
|
||||
#define PWM_0_PORT_CH2 PORTD
|
||||
#define PWM_0_PIN_AF_CH2 4
|
||||
|
||||
#define PWM_0_PIN_CH3 1
|
||||
#define PWM_0_FTMCHAN_CH3 1
|
||||
#define PWM_0_PORT_CH3 PORTA
|
||||
#define PWM_0_PIN_AF_CH3 3
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NUMOF (2U)
|
||||
#define SPI_0_EN 1
|
||||
#define SPI_1_EN 1
|
||||
#define SPI_IRQ_PRIO 1
|
||||
#define KINETIS_SPI_USE_HW_CS 1
|
||||
|
||||
/* SPI 0 device config */
|
||||
#define SPI_0_DEV SPI0
|
||||
#define SPI_0_INDEX 0
|
||||
#define SPI_0_CTAS 0
|
||||
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
|
||||
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
|
||||
#define SPI_0_IRQ SPI0_IRQn
|
||||
#define SPI_0_IRQ_HANDLER isr_spi0
|
||||
#define SPI_0_FREQ (48e6)
|
||||
|
||||
/* SPI 0 pin configuration */
|
||||
#define SPI_0_PORT PORTC
|
||||
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
|
||||
#define SPI_0_AF 2
|
||||
|
||||
#define SPI_0_PCS0_PIN 4
|
||||
#define SPI_0_SCK_PIN 5
|
||||
#define SPI_0_SOUT_PIN 6
|
||||
#define SPI_0_SIN_PIN 7
|
||||
|
||||
#define SPI_0_PCS0_ACTIVE_LOW 1
|
||||
|
||||
/* SPI 1 device config */
|
||||
#define SPI_1_DEV SPI1
|
||||
#define SPI_1_INDEX 1
|
||||
#define SPI_1_CTAS 0
|
||||
#define SPI_1_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI1_MASK))
|
||||
#define SPI_1_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI1_MASK))
|
||||
#define SPI_1_IRQ SPI1_IRQn
|
||||
#define SPI_1_IRQ_HANDLER isr_spi1
|
||||
#define SPI_1_FREQ (48e6)
|
||||
|
||||
/* SPI 1 pin1configuration */
|
||||
#define SPI_1_PORT KW2XDRF_PORT
|
||||
#define SPI_1_PORT_CLKEN() KW2XDRF_PORT_CLKEN();
|
||||
#define SPI_1_AF KW2XDRF_PIN_AF
|
||||
|
||||
#define SPI_1_PCS0_PIN KW2XDRF_PCS0_PIN
|
||||
#define SPI_1_SCK_PIN KW2XDRF_SCK_PIN
|
||||
#define SPI_1_SOUT_PIN KW2XDRF_SOUT_PIN
|
||||
#define SPI_1_SIN_PIN KW2XDRF_SIN_PIN
|
||||
|
||||
#define SPI_1_PCS0_ACTIVE_LOW 1
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NUMOF (1U)
|
||||
#define I2C_CLK (48e6)
|
||||
#define I2C_0_EN 1
|
||||
#define I2C_IRQ_PRIO 1
|
||||
/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
|
||||
#define KINETIS_I2C_F_ICR_LOW (0x3D)
|
||||
#define KINETIS_I2C_F_MULT_LOW (2)
|
||||
/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
|
||||
#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
|
||||
#define KINETIS_I2C_F_MULT_NORMAL (1)
|
||||
/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
|
||||
#define KINETIS_I2C_F_ICR_FAST (0x17)
|
||||
#define KINETIS_I2C_F_MULT_FAST (0)
|
||||
/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
|
||||
#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
|
||||
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
|
||||
|
||||
/* I2C 0 device configuration */
|
||||
#define I2C_0_DEV I2C1
|
||||
#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
|
||||
#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
|
||||
#define I2C_0_IRQ I2C1_IRQn
|
||||
#define I2C_0_IRQ_HANDLER isr_i2c1
|
||||
/* I2C 0 pin configuration */
|
||||
#define I2C_0_PORT PORTE
|
||||
#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define I2C_0_PIN_AF 6
|
||||
#define I2C_0_SDA_PIN 0
|
||||
#define I2C_0_SCL_PIN 1
|
||||
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name GPIO configuration
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NUMOF 8
|
||||
#define GPIO_0_EN 1
|
||||
#define GPIO_1_EN 1
|
||||
#define GPIO_2_EN 1
|
||||
#define GPIO_3_EN 1
|
||||
#define GPIO_4_EN 1
|
||||
#define GPIO_5_EN 1
|
||||
#define GPIO_6_EN 0
|
||||
#define GPIO_7_EN 0
|
||||
#define GPIO_8_EN 0 /* I2CSDA */
|
||||
#define GPIO_9_EN 0 /* I2CSCL */
|
||||
#define GPIO_10_EN 0
|
||||
#define GPIO_11_EN 0
|
||||
#define GPIO_12_EN 0
|
||||
#define GPIO_13_EN 0 /* USB VOUT 3V3 */
|
||||
#define GPIO_14_EN 0 /* USB VREGIN */
|
||||
#define GPIO_15_EN 0
|
||||
#define GPIO_16_EN 0
|
||||
#define GPIO_17_EN 0
|
||||
#define GPIO_18_EN 0
|
||||
#define GPIO_19_EN 0 /* SPI0_CS0 */
|
||||
#define GPIO_20_EN 0 /* SPI0_CLK */
|
||||
#define GPIO_21_EN 0 /* SPI0_MOSI */
|
||||
#define GPIO_22_EN 0 /* SPI0_MISO */
|
||||
#define GPIO_23_EN 1 /* KW2XRF INT */
|
||||
#define GPIO_24_EN 1 /* KW2XRF CS */
|
||||
#define GPIO_IRQ_PRIO 1
|
||||
#define ISR_PORT_A isr_porta
|
||||
#define ISR_PORT_B isr_portb
|
||||
#define ISR_PORT_C isr_portc
|
||||
#define ISR_PORT_D isr_portd
|
||||
|
||||
/* GPIO channel 0 config */
|
||||
#define GPIO_0_DEV GPIOD /* DIO9; extension connecotr D9; LED_G */
|
||||
#define GPIO_0_PORT PORTD
|
||||
#define GPIO_0_PORT_BASE PORTD_BASE
|
||||
#define GPIO_0_PIN 4
|
||||
#define GPIO_0_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_0_IRQ PORTD_IRQn
|
||||
/* GPIO channel 1 config */
|
||||
#define GPIO_1_DEV GPIOD /* DIO11; extension connecotr D5; LED_R */
|
||||
#define GPIO_1_PORT PORTD
|
||||
#define GPIO_1_PORT_BASE PORTD_BASE
|
||||
#define GPIO_1_PIN 6
|
||||
#define GPIO_1_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_1_IRQ PORTD_IRQn
|
||||
/* GPIO channel 2 config */
|
||||
#define GPIO_2_DEV GPIOA /* DIO27; extension connecotr D3; LED_B */
|
||||
#define GPIO_2_PORT PORTA
|
||||
#define GPIO_2_PORT_BASE PORTA_BASE
|
||||
#define GPIO_2_PIN 4
|
||||
#define GPIO_2_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
|
||||
#define GPIO_2_IRQ PORTA_IRQn
|
||||
/* GPIO channel 3 config */
|
||||
#define GPIO_3_DEV GPIOD /* DIO06; extension connecotr --; User_Button */
|
||||
#define GPIO_3_PORT PORTD
|
||||
#define GPIO_3_PORT_BASE PORTD_BASE
|
||||
#define GPIO_3_PIN 1
|
||||
#define GPIO_3_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_3_IRQ PORTD_IRQn
|
||||
/* GPIO channel 4 config */
|
||||
#define GPIO_4_DEV GPIOE /* DIO17; extension connecotr D2 */
|
||||
#define GPIO_4_PORT PORTE
|
||||
#define GPIO_4_PORT_BASE PORTE_BASE
|
||||
#define GPIO_4_PIN 4
|
||||
#define GPIO_4_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_4_IRQ PORTE_IRQn
|
||||
/* GPIO channel 5 config */
|
||||
#define GPIO_5_DEV GPIOA /* DIO29; extension connecotr D4 */
|
||||
#define GPIO_5_PORT PORTA
|
||||
#define GPIO_5_PORT_BASE PORTA_BASE
|
||||
#define GPIO_5_PIN 19
|
||||
#define GPIO_5_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
|
||||
#define GPIO_5_IRQ PORTA_IRQn
|
||||
/* GPIO channel 6 config */
|
||||
#define GPIO_6_DEV GPIOD /* DIO10; extension connecotr A3 */
|
||||
#define GPIO_6_PORT PORTD
|
||||
#define GPIO_6_PORT_BASE PORTD_BASE
|
||||
#define GPIO_6_PIN 5
|
||||
#define GPIO_6_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_6_IRQ PORTD_IRQn
|
||||
/* GPIO channel 7 config */
|
||||
#define GPIO_7_DEV GPIOD /* DIO12; extension connecotr A2 */
|
||||
#define GPIO_7_PORT PORTD
|
||||
#define GPIO_7_PORT_BASE PORTD_BASE
|
||||
#define GPIO_7_PIN 7
|
||||
#define GPIO_7_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_7_IRQ PORTD_IRQn
|
||||
/* GPIO channel 8 config */
|
||||
#define GPIO_8_DEV GPIOE /* DIO13; extension connecotr A4; I2CSDA */
|
||||
#define GPIO_8_PORT PORTE
|
||||
#define GPIO_8_PORT_BASE PORTE_BASE
|
||||
#define GPIO_8_PIN 0
|
||||
#define GPIO_8_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_8_IRQ PORTE_IRQn
|
||||
/* GPIO channel 9 config */
|
||||
#define GPIO_9_DEV GPIOE /* DIO14; extension connecotr A5; I2CSCL */
|
||||
#define GPIO_9_PORT PORTE
|
||||
#define GPIO_9_PORT_BASE PORTE_BASE
|
||||
#define GPIO_9_PIN 1
|
||||
#define GPIO_9_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_9_IRQ PORTE_IRQn
|
||||
/* GPIO channel 10 config */
|
||||
#define GPIO_10_DEV GPIOE /* DIO15; extension connecotr A0 */
|
||||
#define GPIO_10_PORT PORTE
|
||||
#define GPIO_10_PORT_BASE PORTE_BASE
|
||||
#define GPIO_10_PIN 2
|
||||
#define GPIO_10_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_10_IRQ PORTE_IRQn
|
||||
/* GPIO channel 11 config */
|
||||
#define GPIO_11_DEV GPIOE /* DIO16; extension connecotr A1 */
|
||||
#define GPIO_11_PORT PORTE
|
||||
#define GPIO_11_PORT_BASE PORTE_BASE
|
||||
#define GPIO_11_PIN 3
|
||||
#define GPIO_11_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_11_IRQ PORTE_IRQn
|
||||
/* GPIO channel 12 config */
|
||||
#define GPIO_12_DEV GPIOD /* DIO7; extension connecotr D0; UART2_RX */
|
||||
#define GPIO_12_PORT PORTD
|
||||
#define GPIO_12_PORT_BASE PORTD_BASE
|
||||
#define GPIO_12_PIN 2
|
||||
#define GPIO_12_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_12_IRQ PORTD_IRQn
|
||||
/* GPIO channel 13 config */
|
||||
#define GPIO_13_DEV GPIOE /* DIO20; extension connecotr D14, USB OUT3V3 */
|
||||
#define GPIO_13_PORT PORTE
|
||||
#define GPIO_13_PORT_BASE PORTE_BASE
|
||||
#define GPIO_13_PIN 18
|
||||
#define GPIO_13_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_13_IRQ PORTE_IRQn
|
||||
/* GPIO channel 14 config */
|
||||
#define GPIO_14_DEV GPIOE /* DIO21; extension connecotr D15, USB VREGIN */
|
||||
#define GPIO_14_PORT PORTE
|
||||
#define GPIO_14_PORT_BASE PORTE_BASE
|
||||
#define GPIO_14_PIN 19
|
||||
#define GPIO_14_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define GPIO_14_IRQ PORTE_IRQn
|
||||
/* GPIO channel 15 config */
|
||||
#define GPIO_15_DEV GPIOA /* DIO24; extension connecotr D7 */
|
||||
#define GPIO_15_PORT PORTA
|
||||
#define GPIO_15_PORT_BASE PORTA_BASE
|
||||
#define GPIO_15_PIN 1
|
||||
#define GPIO_15_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
|
||||
#define GPIO_15_IRQ PORTA_IRQn
|
||||
/* GPIO channel 16 config */
|
||||
#define GPIO_16_DEV GPIOA /* DIO25; extension connecotr D6 */
|
||||
#define GPIO_16_PORT PORTA
|
||||
#define GPIO_16_PORT_BASE PORTA_BASE
|
||||
#define GPIO_16_PIN 2
|
||||
#define GPIO_16_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
|
||||
#define GPIO_16_IRQ PORTA_IRQn
|
||||
/* GPIO channel 17 config */
|
||||
#define GPIO_17_DEV GPIOA /* DIO28; extension connecotr D8 */
|
||||
#define GPIO_17_PORT PORTA
|
||||
#define GPIO_17_PORT_BASE PORTA_BASE
|
||||
#define GPIO_17_PIN 18
|
||||
#define GPIO_17_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
|
||||
#define GPIO_17_IRQ PORTA_IRQn
|
||||
/* GPIO channel 18 config */
|
||||
#define GPIO_18_DEV GPIOD /* DIO8; extension connecotr D1; UART2_TX */
|
||||
#define GPIO_18_PORT PORTD
|
||||
#define GPIO_18_PORT_BASE PORTD_BASE
|
||||
#define GPIO_18_PIN 3
|
||||
#define GPIO_18_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
|
||||
#define GPIO_18_IRQ PORTD_IRQn
|
||||
/* GPIO channel 19 config */
|
||||
#define GPIO_19_DEV GPIOC /* DIO2; extension connecotr D10; SPI0_CS0 */
|
||||
#define GPIO_19_PORT PORTC
|
||||
#define GPIO_19_PORT_BASE PORTC_BASE
|
||||
#define GPIO_19_PIN 4
|
||||
#define GPIO_19_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
|
||||
#define GPIO_19_IRQ PORTC_IRQn
|
||||
/* GPIO channel 20 config */
|
||||
#define GPIO_20_DEV GPIOC /* DIO3; extension connecotr D13; SPI0_CLK */
|
||||
#define GPIO_20_PORT PORTC
|
||||
#define GPIO_20_PORT_BASE PORTC_BASE
|
||||
#define GPIO_20_PIN 5
|
||||
#define GPIO_20_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
|
||||
#define GPIO_20_IRQ PORTC_IRQn
|
||||
/* GPIO channel 21 config */
|
||||
#define GPIO_21_DEV GPIOC /* DIO4; extension connecotr D11; SPI0_MOSI */
|
||||
#define GPIO_21_PORT PORTC
|
||||
#define GPIO_21_PORT_BASE PORTC_BASE
|
||||
#define GPIO_21_PIN 6
|
||||
#define GPIO_21_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
|
||||
#define GPIO_21_IRQ PORTC_IRQn
|
||||
/* GPIO channel 22 config */
|
||||
#define GPIO_22_DEV GPIOC /* DIO5; extension connecotr D12; SPI0_MISO */
|
||||
#define GPIO_22_PORT PORTC
|
||||
#define GPIO_22_PORT_BASE PORTC_BASE
|
||||
#define GPIO_22_PIN 7
|
||||
#define GPIO_22_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
|
||||
#define GPIO_22_IRQ PORTC_IRQn
|
||||
/* GPIO channel 23 config */
|
||||
#define GPIO_23_DEV KW2XDRF_GPIO
|
||||
#define GPIO_23_PORT KW2XDRF_PORT
|
||||
#define GPIO_23_PORT_BASE KW2XDRF_PORT_BASE
|
||||
#define GPIO_23_PIN KW2XDRF_IRQ_PIN
|
||||
#define GPIO_23_CLKEN() KW2XDRF_PORT_CLKEN()
|
||||
#define GPIO_23_IRQ KW2XDRF_PORT_IRQn
|
||||
#define GPIO_KW2XDRF GPIO_23
|
||||
/* GPIO channel 24 config */
|
||||
#define GPIO_24_DEV KW2XDRF_GPIO
|
||||
#define GPIO_24_PORT KW2XDRF_PORT
|
||||
#define GPIO_24_PORT_BASE KW2XDRF_PORT_BASE
|
||||
#define GPIO_24_PIN KW2XDRF_PCS0_PIN
|
||||
#define GPIO_24_CLKEN() KW2XDRF_PORT_CLKEN()
|
||||
#define GPIO_24_IRQ KW2XDRF_PORT_IRQn
|
||||
#define KW2XRF_CS_GPIO GPIO_24
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTT and RTC configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTT_NUMOF (1U)
|
||||
#define RTC_NUMOF (1U)
|
||||
#define RTT_DEV RTC
|
||||
#define RTT_IRQ RTC_IRQn
|
||||
#define RTT_IRQ_PRIO 10
|
||||
#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
|
||||
#define RTT_ISR isr_rtc
|
||||
#define RTT_FREQUENCY (1)
|
||||
#define RTT_MAX_VALUE (0xffffffff)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Random Number Generator configuration
|
||||
* @{
|
||||
*/
|
||||
#define RANDOM_NUMOF (1U)
|
||||
#define KINETIS_RNGA RNG
|
||||
#define RANDOM_CLKEN() (SIM->SCGC6 |= (1 << 9))
|
||||
#define RANDOM_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Radio configuration (kw2xrf)
|
||||
* @{
|
||||
*/
|
||||
#define KW2XRF_SHARED_SPI 0
|
||||
#define KW2XRF_SPI SPI_1
|
||||
#define KW2XRF_SPI_SPEED SPI_SPEED_10MHZ
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,257 @@
|
||||
/* RAM limits */
|
||||
__sram_start = ORIGIN(sram);
|
||||
__sram_length = LENGTH(sram);
|
||||
__sram_end = __sram_start + __sram_length;
|
||||
_ramcode_start = 0x0;
|
||||
_ramcode_end = 0x0;
|
||||
_ramcode_load = 0x0;
|
||||
|
||||
/* Define the default stack size for interrupt mode. As no context is
|
||||
saved on this stack and ISRs are supposed to be short, it can be fairly
|
||||
small. 512 byte should be a safe assumption here */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800;
|
||||
|
||||
RAMVECT_SIZE = DEFINED(RAMVECT_SIZE) ? RAMVECT_SIZE : 0;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Interrupt vectors 0x00-0x3ff. */
|
||||
.vector_table :
|
||||
{
|
||||
_vector_rom = .;
|
||||
KEEP(*(.isr_vector))
|
||||
KEEP(*(.vector_table))
|
||||
} > vectors
|
||||
ASSERT (SIZEOF(.vector_table) == 0x400, "Interrupt vector table of invalid size.")
|
||||
ASSERT (ADDR(.vector_table) == 0x00000000, "Interrupt vector table at invalid location (linker-script error?)")
|
||||
ASSERT (LOADADDR(.vector_table) == 0x00000000, "Interrupt vector table at invalid location (linker-script error?)")
|
||||
|
||||
/* Flash configuration field, very important in order to not accidentally lock the device */
|
||||
/* Flash configuration field 0x400-0x40f. */
|
||||
.fcfield :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fcfield))
|
||||
. = ALIGN(4);
|
||||
} > flashsec
|
||||
ASSERT (SIZEOF(.fcfield) == 0x10, "Flash configuration field of invalid size (linker-script error?)")
|
||||
ASSERT (ADDR(.fcfield) == 0x400, "Flash configuration field at invalid position (linker-script error?)")
|
||||
ASSERT (LOADADDR(.fcfield) == 0x400, "Flash configuration field at invalid position (linker-script error?)")
|
||||
|
||||
/* Program code 0x410-. */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_text_load = LOADADDR(.text);
|
||||
_text_start = .;
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(SORT(.preinit_array.*)))
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
|
||||
/* fini data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
KEEP (*(SORT_NONE(.fini)))
|
||||
/* Default ISR handlers */
|
||||
KEEP(*(.default_handlers))
|
||||
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
|
||||
*(.text.exit .text.exit.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
*(.text.hot .text.hot.*)
|
||||
*(.text .stub .text.* .gnu.linkonce.t.*)
|
||||
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
KEEP (*crtbeginTS.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*crtbeginTS.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
. = ALIGN(4);
|
||||
_rodata_start = .;
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
. = ALIGN(4);
|
||||
_rodata_end = .;
|
||||
_text_end = .;
|
||||
} > flash
|
||||
|
||||
/* The .extab, .exidx sections are used for C++ exception handling */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > flash
|
||||
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > flash
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > flash
|
||||
|
||||
.eh_frame : ONLY_IF_RO
|
||||
{
|
||||
KEEP (*(.eh_frame))
|
||||
} > flash
|
||||
|
||||
.gcc_except_table : ONLY_IF_RO
|
||||
{
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
} > flash
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
/*
|
||||
* Allocate space for interrupt vector in RAM
|
||||
* This can safely be removed to free up 0x100 bytes of RAM if the code does
|
||||
* not make use of this CPU feature.
|
||||
*/
|
||||
.ramvect :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_vector_ram_start = .;
|
||||
. = _vector_ram_start + RAMVECT_SIZE;
|
||||
. = ALIGN(4);
|
||||
_vector_ram_end = .;
|
||||
} > sram
|
||||
|
||||
/* Program data, values stored in flash and loaded upon init. */
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_data_load = LOADADDR(.relocate);
|
||||
_data_start = .;
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
_data_end = .;
|
||||
} > sram
|
||||
|
||||
/* .bss section, zeroed out during init. */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
__bss_start = .;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
__bss_end = .;
|
||||
_ezero = .;
|
||||
} > sram
|
||||
|
||||
/* Make sure we set _end, in case we want dynamic memory management... */
|
||||
_end = .;
|
||||
__end = .;
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
|
||||
. = ALIGN(8);
|
||||
HEAP_SIZE = ORIGIN(sram) + LENGTH(sram) - STACK_SIZE - .;
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
_heap_start = .;
|
||||
PROVIDE(__heap_start = .);
|
||||
. = . + HEAP_SIZE;
|
||||
_heap_end = .;
|
||||
PROVIDE(__heap_max = .);
|
||||
} > sram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
_estack = .;
|
||||
} > sram
|
||||
|
||||
/* Any debugging sections */
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* DWARF 3 */
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
/* DWARF Extension. */
|
||||
.debug_macro 0 : { *(.debug_macro) }
|
||||
|
||||
/* XXX: what is the purpose of these sections? */
|
||||
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }
|
||||
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
}
|
||||
@ -0,0 +1,7 @@
|
||||
# define the module that is build
|
||||
MODULE = cpu
|
||||
|
||||
# add a list of subdirectories, that should also be build
|
||||
DIRS = periph $(CORTEX_M4_COMMON) $(KINETIS_COMMON)
|
||||
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
@ -0,0 +1,38 @@
|
||||
# this CPU implementation is using the explicit core/CPU interface
|
||||
export CFLAGS += -DCOREIF_NG=1
|
||||
|
||||
# export the peripheral drivers to be linked into the final binary
|
||||
export USEMODULE += periph
|
||||
|
||||
# tell the build system that the CPU depends on the Cortex-M common files
|
||||
export USEMODULE += cortex-m4_common
|
||||
|
||||
# tell the build system that the CPU depends on the Kinetis common files
|
||||
export USEMODULE += kinetis_common
|
||||
|
||||
# define path to cortex-m common module, which is needed for this CPU
|
||||
export CORTEX_M4_COMMON = $(RIOTCPU)/cortex-m4_common/
|
||||
|
||||
# define path to kinetis module, which is needed for this CPU
|
||||
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
|
||||
|
||||
# CPU depends on the cortex-m common module, so include it
|
||||
include $(CORTEX_M4_COMMON)Makefile.include
|
||||
|
||||
# CPU depends on the kinetis module, so include it
|
||||
include $(KINETIS_COMMON)Makefile.include
|
||||
|
||||
export LINKFLAGS += -L$(RIOTCPU)/kinetis_common/ldscripts
|
||||
# define the linker script to use for this CPU
|
||||
export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/$(CPU_MODEL)_linkerscript.ld
|
||||
|
||||
#export the CPU model
|
||||
MODEL = $(shell echo $(CPU_MODEL)|tr 'a-z' 'A-Z')
|
||||
export CFLAGS += -DCPU_MODEL_$(MODEL)
|
||||
|
||||
# include CPU specific includes
|
||||
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include
|
||||
|
||||
# add the CPU specific system calls implementations for the linker
|
||||
export UNDEF += $(BINDIR)cpu/interrupt-vector.o
|
||||
export UNDEF += $(BINDIR)cpu/syscalls.o
|
||||
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freie Universität Berlin
|
||||
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_kw2x
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of the KW2xD CPU initialization
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Johann Fischer <j.fischer@phytec.de>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "cpu-conf.h"
|
||||
|
||||
#define FLASH_BASE (0x00000000)
|
||||
|
||||
static void cpu_clock_init(void);
|
||||
|
||||
/**
|
||||
* @brief Initialize the CPU, set IRQ priorities
|
||||
*/
|
||||
void cpu_init(void)
|
||||
{
|
||||
/* configure the vector table location to internal flash */
|
||||
SCB->VTOR = FLASH_BASE;
|
||||
|
||||
/* initialize the clock system */
|
||||
cpu_clock_init();
|
||||
|
||||
/* set pendSV interrupt to lowest possible priority */
|
||||
NVIC_SetPriority(PendSV_IRQn, 0xff);
|
||||
}
|
||||
|
||||
static inline void modem_clock_init(void)
|
||||
{
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK);
|
||||
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK);
|
||||
/* Use the CLK_OUT of the modem as the clock source. */
|
||||
/* Modem RST_B is connected to PTB19 and can be used to reset the modem. */
|
||||
PORTB->PCR[19] = PORT_PCR_MUX(1);
|
||||
GPIOB->PDDR |= (1 << 19);
|
||||
GPIOB->PCOR |= (1 << 19);
|
||||
/* Modem GPIO5 is connected to PTC0 and can be used to select CLK_OUT frequency, */
|
||||
/* set PTC0 high for CLK_OUT=32.787kHz and low for CLK_OUT=4MHz. */
|
||||
PORTC->PCR[0] = PORT_PCR_MUX(1);
|
||||
GPIOC->PDDR |= (1 << 0);
|
||||
GPIOC->PCOR |= (1 << 0);
|
||||
/* Modem IRQ_B is connected to PTB3, modem interrupt request to the MCU. */
|
||||
PORTB->PCR[KW2XDRF_IRQ_PIN] = PORT_PCR_MUX(1);
|
||||
GPIOB->PDDR &= ~(1 << KW2XDRF_IRQ_PIN);
|
||||
|
||||
/* release the reset */
|
||||
GPIOB->PSOR |= (1 << 19);
|
||||
|
||||
/* wait for modem IRQ_B interrupt request */
|
||||
while (GPIOB->PDIR & (1 << KW2XDRF_IRQ_PIN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the controllers clock system
|
||||
*/
|
||||
static void cpu_clock_init(void)
|
||||
{
|
||||
/* setup system prescalers */
|
||||
SIM->CLKDIV1 = (uint32_t)SIM_CLKDIV1_OUTDIV4(1);
|
||||
|
||||
modem_clock_init();
|
||||
kinetis_mcg_set_mode(KINETIS_MCG_PEE);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freie Universität Berlin
|
||||
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup cpu_kw2x KW2xD SiP
|
||||
* @ingroup cpu
|
||||
* @brief CPU specific implementations for the Freescale KW2xD SiP.
|
||||
* The SiP incorporates a low power 2.4 GHz transceiver and a
|
||||
* Kinetis Cortex-M4 MCU.
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation specific CPU configuration options
|
||||
*
|
||||
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
|
||||
* @author Johann Fischer <j.fischer@phytec.de>
|
||||
*/
|
||||
|
||||
#ifndef __CPU_CONF_H
|
||||
#define __CPU_CONF_H
|
||||
|
||||
#ifdef CPU_MODEL_KW21D256
|
||||
#include "MKW22D5.h"
|
||||
#elif CPU_MODEL_KW21D512
|
||||
#include "MKW22D5.h"
|
||||
#elif CPU_MODEL_KW22D512
|
||||
#include "MKW22D5.h"
|
||||
#else
|
||||
#error "undefined CPU_MODEL"
|
||||
#endif
|
||||
|
||||
#include "mcg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Kernel configuration
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define KERNEL_CONF_STACKSIZE_PRINTF (1024)
|
||||
|
||||
#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
|
||||
#define KERNEL_CONF_STACKSIZE_DEFAULT (1024)
|
||||
#endif
|
||||
|
||||
#define KERNEL_CONF_STACKSIZE_IDLE (256)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Length for reading CPU_ID in octets
|
||||
*/
|
||||
#define CPUID_ID_LEN (16)
|
||||
|
||||
/**
|
||||
* @brief Pointer to CPU_ID
|
||||
*/
|
||||
#define CPUID_ID_PTR ((void *)(&(SIM_UIDH)))
|
||||
|
||||
/**
|
||||
* @name UART0 buffer size definition for compatibility reasons.
|
||||
*
|
||||
* TODO: remove once the remodeling of the uart0 driver is done.
|
||||
* @{
|
||||
*/
|
||||
#ifndef UART0_BUFSIZE
|
||||
#define UART0_BUFSIZE (128)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#define TRANSCEIVER_BUFFER_SIZE (3) /**< Buffer Size for Transceiver Module */
|
||||
|
||||
/**
|
||||
* @brief MCU specific Low Power Timer settings.
|
||||
*/
|
||||
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
|
||||
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
|
||||
#define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK) /**< Enable LPTMR0 clock gate */
|
||||
#define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK) /**< Disable LPTMR0 clock gate */
|
||||
#define LPTIMER_CNR_NEEDS_LATCHING 1 /**< LPTMR.CNR register do not need latching */
|
||||
|
||||
/**
|
||||
* @name KW2XD SiP internal interconnects between MCU and Modem.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define KW2XDRF_PORT_BASE PORTB_BASE /**< MCU Port connected to Modem*/
|
||||
#define KW2XDRF_PORT PORTB /**< MCU Port connected to Modem*/
|
||||
#define KW2XDRF_GPIO GPIOB /**< GPIO Device connected to Modem */
|
||||
#define KW2XDRF_PORT_IRQn PORTB_IRQn
|
||||
#define KW2XDRF_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK)) /**< Clock Enable for PORTB*/
|
||||
#define KW2XDRF_PIN_AF 2 /**< Pin Muxing Parameter for GPIO Device*/
|
||||
#define KW2XDRF_PCS0_PIN 10 /**< SPI Slave Select Pin */
|
||||
#define KW2XDRF_SCK_PIN 11 /**< SPI Clock Output Pin */
|
||||
#define KW2XDRF_SOUT_PIN 16 /**< SPI Master Data Output Pin */
|
||||
#define KW2XDRF_SIN_PIN 17 /**< SPI Master Data Input Pin */
|
||||
|
||||
#define KW2XDRF_IRQ_PIN 3 /**< Modem's IRQ Output (activ low) */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CPU_CONF_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,370 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freie Universität Berlin
|
||||
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_kw2x
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Interrupt vector definition for MKW2XDXXX MCUs
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Johann Fischer <j.fischer@phytec.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "cpu-conf.h"
|
||||
#include "fault_handlers.h"
|
||||
|
||||
/**
|
||||
* memory markers as defined in the linker script
|
||||
*/
|
||||
extern uint32_t _estack;
|
||||
|
||||
extern void reset_handler(void);
|
||||
|
||||
void dummy_handler(void)
|
||||
{
|
||||
isr_unhandled();
|
||||
}
|
||||
|
||||
/* Cortex-M specific interrupt vectors */
|
||||
void isr_svc(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_pendsv(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_systick(void) __attribute__((weak, alias("dummy_handler")));
|
||||
|
||||
/* MKW22D512 specific interrupt vector */
|
||||
void isr_dma0(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma1(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma2(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma3(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma4(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma5(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma6(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma7(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma8(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma9(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma10(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma11(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma12(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma13(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma14(void) __attribute__((weak, alias("dummy_handler")));
|
||||
void isr_dma15(void) __attribute__((weak, alias("dummy_handler")));
|
||||