Browse Source

cpu: mips-pic32mz: Add support for PIC32MZ devices

specific support for the pic32mz2046efg100 is added along with code common to
all pic32 devices and all pic32mz devices.
pr/rotary
Neil Jones 6 years ago
parent
commit
241087fd76
  1. 2
      cpu/mips_pic32_common/Makefile
  2. 7
      cpu/mips_pic32_common/Makefile.include
  3. 3
      cpu/mips_pic32_common/periph/Makefile
  4. 77
      cpu/mips_pic32_common/periph/uart.c
  5. 244
      cpu/mips_pic32_common/reset_mod.S
  6. 8
      cpu/mips_pic32mz/Makefile
  7. 69
      cpu/mips_pic32mz/Makefile.include
  8. 52
      cpu/mips_pic32mz/eic_pic32mz.c
  9. 54
      cpu/mips_pic32mz/include/cpu.h
  10. 71
      cpu/mips_pic32mz/include/cpu_conf.h
  11. 51671
      cpu/mips_pic32mz/include/p32mz2048efg100.h
  12. 19
      cpu/mips_pic32mz/include/periph_cpu.h
  13. 409
      cpu/mips_pic32mz/ldscripts/pic32mz2048_uhi.ld
  14. 1
      cpu/mips_pic32mz/p32mz2048efg100/Makefile
  15. 6288
      cpu/mips_pic32mz/p32mz2048efg100/p32mz2048efg100.S

2
cpu/mips_pic32_common/Makefile

@ -0,0 +1,2 @@
DIRS += periph
include $(RIOTBASE)/Makefile.base

7
cpu/mips_pic32_common/Makefile.include

@ -0,0 +1,7 @@
# depends on mips32r2_common
USEMODULE += mips32r2_common
export MIPS32R2_COMMON = $(RIOTCPU)/mips32r2_common/
export INCLUDES = $(MIPS32R2_COMMON)include
include $(MIPS32R2_COMMON)Makefile.include

3
cpu/mips_pic32_common/periph/Makefile

@ -0,0 +1,3 @@
MODULE = periph
include $(RIOTBASE)/Makefile.base

77
cpu/mips_pic32_common/periph/uart.c

@ -0,0 +1,77 @@
/*
* Copyright(C) 2016,2017 Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <assert.h>
#include "periph/uart.h"
#include "board.h"
#define UxMODE(U) (U.regs[0x00/4])
#define UxMODECLR(U) (U.regs[0x04/4])
#define UxMODESET(U) (U.regs[0x08/4])
#define UxSTA(U) (U.regs[0x10/4])
#define UxSTACLR(U) (U.regs[0x14/4])
#define UxSTASET(U) (U.regs[0x18/4])
#define UxTXREG(U) (U.regs[0x20/4])
#define UxRXREG(U) (U.regs[0x30/4])
#define UxBRG(U) (U.regs[0x40/4])
#define REGS_SPACING (_UART2_BASE_ADDRESS - _UART1_BASE_ADDRESS)
/* PERIPHERAL_CLOCK must be defined in board file */
typedef struct PIC32_UART_tag {
volatile uint32_t *regs;
uint32_t clock;
} PIC32_UART_T;
/* pic uarts are numbered 1 to 6 */
static PIC32_UART_T pic_uart[UART_NUMOF + 1];
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
assert(uart <= UART_NUMOF && uart != 0); /*No uart 0 on pic32*/
/* Pin Mux should be setup in board file */
pic_uart[uart].regs =
(volatile uint32_t *)(_UART1_BASE_ADDRESS + (uart - 1) * REGS_SPACING);
pic_uart[uart].clock = PERIPHERAL_CLOCK;
UxBRG(pic_uart[uart])= (pic_uart[uart].clock / (16 * baudrate)) - 1;
UxSTA(pic_uart[uart])= 0;
UxMODE(pic_uart[uart])= _U1MODE_ON_MASK;
UxSTASET(pic_uart[uart])= _U1STA_URXEN_MASK;
UxSTASET(pic_uart[uart])= _U1STA_UTXEN_MASK;
return 0;
}
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
assert(uart <= UART_NUMOF && uart != 0);
while(len--) {
while(UxSTA(pic_uart[uart])& _U1STA_UTXBF_MASK) {}
UxTXREG(pic_uart[uart]) = *data++;
}
}
void uart_poweron(uart_t uart)
{
assert(uart <= UART_NUMOF && uart != 0);
UxMODESET(pic_uart[uart])= _U1MODE_ON_MASK;
}
void uart_poweroff(uart_t uart)
{
assert(uart <= UART_NUMOF && uart != 0);
UxMODECLR(pic_uart[uart])= _U1MODE_ON_MASK;
}

244
cpu/mips_pic32_common/reset_mod.S

@ -0,0 +1,244 @@
/*
* Copyright 2014-2015, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* ************ PLEASE READ ME !!!! ****************
This file is a copy of the reset_mod.S from $MIPS_ELF_ROOT/share/mips/boot
(from the 2016.05-03 version) with a couple of modifications:
#define SKIP_COPY_TO_RAM - prevents the bootloader copying the whole contents
of flash to ram (as we want to XIP from flash), we copy initialised data from
flash to ram in 'software_init_hook'.
move .org's to before the labels to make the vector labels appear at the vector
addresses.
In boot_debug_exception vector drop out of debug mode before spining, this allows
attachment of an external debug program to investigate a hung system.
Future toolchain versions will have these changes included and this file will
be no longer needed.
Note the above copyright/license is 3 Clause BSD and as such is compatible with LGPLv2.1
as such we grant licensing this file under LGPLv2.1 (See the file LICENSE in the top level
directory for more details) as well.
Thanks for reading.
*/
#define _RESETCODE
.set nomips16
#include <mips/regdef.h>
#include <mips/cpu.h>
#include <mips/asm.h>
.set push
.set nomicromips
LEAF(__reset_vector)
lui a2, %hi(__cpu_init)
addiu a2, %lo(__cpu_init)
mtc0 $0, C0_COUNT # Clear cp0 Count (Used to measure boot time.)
jr a2
.space 32 # Just to cope with a quirk of MIPS malta boards
# this can be deleted for anything else.
END(__reset_vector)
.set pop
LEAF(__cpu_init)
# Verify the code is here due to a reset and not NMI. If this is an NMI then trigger
# a debugger breakpoint using a sdbp instruction.
mfc0 s1, C0_STATUS # Read CP0 Status
ext s1, s1, SR_NMI_SHIFT, 1 # extract NMI
beqz s1, init_resources # Branch if this is NOT an NMI exception.
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
init_resources:
# Init CP0 Status, Count, Compare, Watch*, and Cause.
jal __init_cp0
# Initialise L2/L3 cache
# This could be done from cached code if there is a cca override or similar
# Determine L2/L3 cache config.
lui a2, %hi(__init_l23cache)
addiu a2, a2, %lo(__init_l23cache)
jal a2
init_ic:
# Initialize the L1 instruction cache.
jal __init_icache
# The changing of Kernel mode cacheability must be done from KSEG1
# Since the code is executing from KSEG0 It needs to do a jump to KSEG1 change K0
# and jump back to KSEG0
lui a2, %hi(__change_k0_cca)
addiu a2, a2, %lo(__change_k0_cca)
li a1, 0xf
ins a2, a1, 29, 1 # changed to KSEG1 address by setting bit 29
jalr a2
.weak __init_l23cache_cached
lui a2, %hi(__init_l23cache_cached)
addiu a2, a2, %lo(__init_l23cache_cached)
beqz a2, init_dc
jal a2
init_dc:
# Initialize the L1 data cache
jal __init_dcache
# Initialize the TLB.
jal __init_tlb
# Allow everything else to be initialized via a hook.
.weak __boot_init_hook
lui a2, %hi(__boot_init_hook)
addiu a2, a2, %lo(__boot_init_hook)
beqz a2, 1f
jalr a2
1:
#ifndef SKIP_COPY_TO_RAM
# Copy code and data to RAM
li s1, 0xffffffff
# Copy code and read-only/initialized data from FLASH to (uncached) RAM.
lui a1, %hi(__flash_app_start)
addiu a1, a1, %lo(__flash_app_start)
ins a1, s1, 29, 1 # Make it uncached (kseg1)
lui a2, %hi(__app_start)
addiu a2, a2, %lo(__app_start)
ins a2, s1, 29, 1 # Make it uncached (kseg1)
lui a3, %hi(_edata)
addiu a3, a3, %lo(_edata)
ins a3, s1, 29, 1 # Make it uncached (kseg1)
beq a2, a3, $Lcopy_to_ram_done
$Lnext_ram_word:
lw a0, 0(a1)
sw a0, 0(a2)
addiu a2, a2, 4
addiu a1, a1, 4
bne a3, a2, $Lnext_ram_word
$Lcopy_to_ram_done:
#endif
# Prepare for eret to _start
lui ra, %hi($Lall_done) # If main returns then go to all_done.
addiu ra, ra, %lo($Lall_done)
lui v0, %hi(_start) # Load the address of _start
addiu v0, v0, %lo(_start)
mtc0 v0, C0_ERRPC # Set ErrorEPC to _start
ehb # Clear hazards (makes sure write to ErrorPC has completed)
li a0, 0 # UHI compliant null argument setup
# Return from exception will now execute the application startup code
eret
$Lall_done:
# If _start returns it will return to this point.
# Just spin here reporting the exit.
li $25, 1 # UHI exit operation
move $4, v0 # Collect exit code for UHI exit
sdbbp 1 # Invoke UHI operation
b $Lall_done
END(__cpu_init)
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S (CP0 Status[BEV] = 1)
**************************************************************************************/
/* NOTE: the linker script must insure that this code starts at start + 0x200 so the exception */
/* vectors will be addressed properly. All .org assume this! */
/* TLB refill, 32 bit task. */
.org 0x200 # TLB refill, 32 bit task.
LEAF(__boot_tlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_tlb_refill)
.org 0x280 # XTLB refill, 64 bit task. BEV + 0x280
LEAF(__boot_xtlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_xtlb_refill)
.org 0x300 # Cache error exception. BEV + 0x300
LEAF(__boot_cache_error)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_cache_error)
.org 0x380 # General exception. BEV + 0x380
LEAF(__boot_general_exception)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_general_exception)
# If you want the above code to fit into 1k flash you will need to leave
# out the code below. This is the code that covers the debug exception
# which you normally will not get.
.org 0x480
LEAF(__boot_debug_exception)
# EJTAG Debug (with ProbEn = 0 in the EJTAG Control Register)
mfc0 k1, C0_DEPC # Save Debug exception point in DESAVE
mtc0 k1, C0_DESAVE
LA k1, 1f
# Drop out of debug mode before spinning (To allow a JTAG probe in).
mtc0 k1, C0_DEPC
ehb
deret
1:
b 1b #Spin indefinately
END(__boot_debug_exception)

8
cpu/mips_pic32mz/Makefile

@ -0,0 +1,8 @@
MODULE = cpu
USEMODULE += mips_pic32_common
USEMODULE += mips32r2_common
DIRS += $(RIOTCPU)/mips_pic32_common $(RIOTCPU)/mips32r2_common
include $(RIOTBASE)/Makefile.base

69
cpu/mips_pic32mz/Makefile.include

@ -0,0 +1,69 @@
ifndef MIPS_ELF_ROOT
$(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH")
endif
# Target triple for the build.
export TARGET_ARCH ?= mips-mti-elf
export ABI=32
export MEMORY_BASE=0x80000000
export MEMORY_SIZE=512K
export APP_START=0x80000000
export ROMABLE = 1
include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk
# define build specific options
export CFLAGS_CPU = -EL -march=m5101 -mmicromips -std=gnu99
export CFLAGS_LINK = -ffunction-sections -fno-builtin -fshort-enums
export CFLAGS_DBG = -O0 -g2
export CFLAGS_OPT = -Os -g2
export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT) -DSKIP_COPY_TO_RAM
#$(CFLAGS_DBG)
ifeq ($(USE_HARD_FLOAT),1)
export CFLAGS += -mhard-float
else
export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float
export LINKFLAGS += -msoft-float
endif
ifeq ($(USE_DSP),1)
export CFLAGS += -mdsp
endif
export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG)
export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI) -Wl,--defsym,__use_excpt_boot=0
export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mz2048_uhi.ld
export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) #$(CFLAGS_OPT)
export LINKFLAGS += -Wl,--gc-sections
# This CPU implementation is using the new core/CPU interface:
export CFLAGS += -DCOREIF_NG=1
# The M51xx supports micromips ISA for reduced code size.
export CFLAGS += -DMIPS_MICROMIPS
export USEMODULE += periph
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
export OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
export OFLAGS += -O ihex \
--change-section-lma .lowerbootflashalias-0xA0000000 \
--change-section-lma .bootflash1-0xA0000000 \
--change-section-lma .bootflash2-0xA0000000 \
--change-section-lma .exception_vector-0x80000000 \
--change-section-lma .text-0x80000000 \
--change-section-lma .init-0x80000000 \
--change-section-lma .fini-0x80000000 \
--change-section-lma .eh_frame-0x80000000 \
--change-section-lma .gcc_except_table-0x80000000 \
--change-section-lma .jcr-0x80000000 \
--change-section-lma .ctors-0x80000000 \
--change-section-lma .dtors-0x80000000 \
--change-section-lma .rodata-0x80000000 \
--change-section-lma .data-0x80000000 \
--change-section-lma .bss-0x80000000 \
--change-section-lma .startdata-0x80000000 \

52
cpu/mips_pic32mz/eic_pic32mz.c

@ -0,0 +1,52 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <assert.h>
#include "board.h"
#include "../mips32r2_common/include/eic_irq.h"
void eic_irq_configure(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Enable IRQ0 CPU Timer Interrupt */
IEC0SET = _IEC0_CTIE_MASK;
/* Set IRQ 0 to priority 1.0 */
IPC0SET = 1 << _IPC0_CTIP_POSITION | 0 << _IPC0_CTIS_POSITION;
}
void eic_irq_enable(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Enable IRQ0 CPU Timer Interrupt */
IEC0SET = _IEC0_CTIE_MASK;
}
void eic_irq_disable(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Disable IRQ0 CPU Timer Interrupt */
IEC0CLR = _IEC0_CTIE_MASK;
}
void eic_irq_ack(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Ack the timer interrupt */
IFS0CLR =_IFS0_CTIF_MASK;
}

54
cpu/mips_pic32mz/include/cpu.h

@ -0,0 +1,54 @@
/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mz MIPS PIC32MZ
* @ingroup cpu
* @{
*
* @file
* @brief main CPU definitions for pic32mz devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef CPU_H_
#define CPU_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdio.h>
#include <inttypes.h>
#include <assert.h>
#include "irq.h"
/**
* @brief We run from flash on PIC32
*/
#define FLASH_XIP (1)
/**
* @brief Print the last instruction's address
*
* @todo: Not supported
*/
static inline void cpu_print_last_instruction(void)
{
/* This function must exist else RIOT won't compile */
}
#ifdef __cplusplus
}
#endif
#endif
/** @} */

71
cpu/mips_pic32mz/include/cpu_conf.h

@ -0,0 +1,71 @@
/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mz MIPS PIC32MZ
* @ingroup cpu
* @{
*
* @file
* @brief CPU definitions for pic32mz devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef _CPU_CONF_H_
#define _CPU_CONF_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configuration of default stack sizes
*
* printf takes a pretty tortured route through the C lib
* then via UHI syscall exception to end up at the UART
* driver.
*
* When debugging timer code we get printfs on the idle threads
* stack which can easily blow its limits.
*
* Note code must be compiled at -Os with these values, using -O0
* you'll overflow these stacks.
*
* NO ISR stack is in use yet, interrupt use the current running stack
* hence the big-ish default stack size.
* @{
*/
#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
#define THREAD_EXTRA_STACKSIZE_PRINTF (1024)
#endif
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (2048)
#endif
#ifndef THREAD_STACKSIZE_IDLE
#ifdef NDEBUG
#define THREAD_STACKSIZE_IDLE (512)
#else
#define THREAD_STACKSIZE_IDLE (512 + THREAD_EXTRA_STACKSIZE_PRINTF)
#endif
#endif
#define ISR_STACKSIZE (0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif
/** @} */

51671
cpu/mips_pic32mz/include/p32mz2048efg100.h

File diff suppressed because it is too large Load Diff

19
cpu/mips_pic32mz/include/periph_cpu.h

@ -0,0 +1,19 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/* This file must exist to get timer code to build */
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif

409
cpu/mips_pic32mz/ldscripts/pic32mz2048_uhi.ld

@ -0,0 +1,409 @@
/*
* A platform and target independent link script to produce UHI
* compliant binaries with varying levels of system initialization
* support.
*/
__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;
ENTRY(__entry)
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
GROUP(-lc -luhi -lgcc -lhal)
SEARCH_DIR(.)
__DYNAMIC = 0;
STARTUP(crt0.o)
/* Force the exception handler to be registered */
EXTERN(__register_excpt_handler)
/* Force the exception handler to be included in the link */
EXTERN(__exception_entry)
/*
* Require verbose exceptions. This can be changed to pull in
* __exception_handle_quiet to reduce code size but be less
* informative
*/
EXTERN(__exception_handle_verbose)
/* Force the interrupt handlers to tbe included in the link */
EXTERN(__isr_vec)
/* Require the UHI getargs support */
EXTERN(__getargs)
/*
* Set the location of the top of the stack. A value of 0 means
* that it will be automatically placed at the highest address
* available as described by the __memory_* setttings
*/
PROVIDE (__stack = 0);
/* Size of the memory returned by _get_ram_range */
PROVIDE (__memory_size = 512K);
/* Base of the memory returned by _get_ram_range */
PROVIDE (__memory_base = 0x80000000);
/* Stride length for tlb software invalidate for tlbinvf
* (mipsXXr3+). Some MIPS implementations may layout the sets/ways
* differently in the index register. Either sets LSB or ways LSB.
*
* By setting this to 1 we presume that sets come first. The default boot
* code will decrement this value from the Number of TLB entries.
*/
PROVIDE (__tlb_stride_length = 1);
/* By default, XPA is not used even if available. To enable XPA,
* __enable_xpa should be 1.
*/
PROVIDE (__enable_xpa = 0);
/*
* 0 = Do not use exception handler present in boot for UHI
* 1 = Use exception handler present in boot for UHI if BEV is 0 at
* startup
* 2 = Always use exception handler present in boot for UHI
*/
PROVIDE (__use_excpt_boot = 0);
/*
* Include the code to be able to return to boot context. This is
* necessary if __use_excpt_boot != 0.
*/
EXTERN (__register_excpt_boot);
ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,
"Registration for boot context is required for UHI chaining")
/* Control if subnormal floating-point values are flushed to zero in
hardware. This applies to both FPU and MSA operations. */
PROVIDE (__flush_to_zero = 1);
/* Set up the public symbols depending on whether the user has chosen
quiet or verbose exception handling above */
EXTERN (__exception_handle);
PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)
? __exception_handle_quiet
: __exception_handle_verbose));
PROVIDE(_mips_handle_exception = __exception_handle);
/*
* Initalize some symbols to be zero so we can reference them in the
* crt0 without core dumping. These functions are all optional, but
* we do this so we can have our crt0 always use them if they exist.
* This is so BSPs work better when using the crt0 installed with gcc.
* We have to initalize them twice, so we multiple object file
* formats, as some prepend an underscore.
*/
PROVIDE (hardware_exit_hook = 0);
PROVIDE (hardware_hazard_hook = 0);
PROVIDE (hardware_init_hook = 0);
PROVIDE (software_init_hook = 0);
/* The default base address for application flash code is 0x9D001000 */
PROVIDE (__app_start = 0x9D001000) ;
/* Set default vector spacing to 32 bytes. */
PROVIDE (__isr_vec_space = 32);
/* Leave space for 9 vector entries by default. 8 entry points and one
fallback handler. */
PROVIDE (__isr_vec_count = 9);
/*
* The start of boot flash must be set if including boot code. By default
* the use of boot code will mean that application code is copied
* from flash to RAM at runtime before being executed.
*/
PROVIDE (__lower_boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);
PROVIDE (__boot_flash1_start = 0xbfc40000);
PROVIDE (__boot_flash2_start = 0xbfc60000);
PROVIDE (__bev_override = 0x9fc00000);
PROVIDE (__flash_vector_start = 0x9D000000);
PROVIDE (__flash_app_start = 0x9D001000);
SECTIONS
{
/* Start of bootrom */
.lowerbootflashalias __bev_override : /* Runs uncached (from 0xBfc00000) until I$ is
initialized. */
AT (__lower_boot_flash_start)
{
__base = .;
*(.reset) /* Reset entry point. */
*(.boot) /* Boot code. */
. = ALIGN(8);
. = __base + 0xff40; /*Alternate Config bits (lower Alias)*/
KEEP(*(.adevcfg3_la))
KEEP(*(.adevcfg2_la))
KEEP(*(.adevcfg1_la))
KEEP(*(.adevcfg0_la))
. = __base + 0xff5c;
KEEP(*(.adevcp0_la))
. = __base + 0xff6c;
KEEP(*(.adevsign_la))
. = __base + 0xffc0; /*Config bits (lower Alias)*/
KEEP(*(.devcfg3_la))
KEEP(*(.devcfg2_la))
KEEP(*(.devcfg1_la))
KEEP(*(.devcfg0_la))
. = __base + 0xffdc;
KEEP(*(.devcp0_la))
. = __base + 0xffec;
KEEP(*(.devsign_la))
. = __base + 0xfff0;
KEEP(*(.seq_la))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x40000 + 0xff40;
.bootflash1 :
AT(__boot_flash1_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b1))
KEEP(*(.adevcfg2_b1))
KEEP(*(.adevcfg1_b1))
KEEP(*(.adevcfg0_b1))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b1))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b1))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b1))
KEEP(*(.devcfg2_b1))
KEEP(*(.devcfg1_b1))
KEEP(*(.devcfg0_b1))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b1))
. = __altbase + 0xAc;
KEEP(*(.devsign_b1))
. = __altbase + 0xB0;
KEEP(*(.seq_b1))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x60000 + 0xff40;
.bootflash2 :
AT(__boot_flash2_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b2))
KEEP(*(.adevcfg2_b2))
KEEP(*(.adevcfg1_b2))
KEEP(*(.adevcfg0_b2))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b2))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b2))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b2))
KEEP(*(.devcfg2_b2))
KEEP(*(.devcfg1_b2))
KEEP(*(.devcfg0_b2))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b2))
. = __altbase + 0xAc;
KEEP(*(.devsign_b2))
. = __altbase + 0xB0;
KEEP(*(.seq_b2))
} = 0xFFFFFFFF
/* Start of the application */
.exception_vector ALIGN(__flash_vector_start, 0x1000) :
AT (__flash_vector_start)
{
PROVIDE (__excpt_ebase = ABSOLUTE(.));
__base = .;
KEEP(* (.text.__exception_entry))
. = __base + 0x200;
KEEP(* (SORT(.text.__isr_vec*)))
/* Leave space for all the vector entries */
. = __base + 0x200 + (__isr_vec_space * __isr_vec_count);
ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw1 - __isr_vec_sw0
: __isr_vec_space),
"Actual ISR vector spacing does not match __isr_vec_space");
ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),
"__isr_vec_sw0 is not placed at EBASE + 0x200");
. = ALIGN(8);
} = 0
. = __flash_app_start;
.text : {
_ftext = . ;
PROVIDE (eprol = .);
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.mips16.fn.*)
*(.mips16.call.*)
}
.init : {
KEEP (*(.init))
}
.fini : {
KEEP (*(.fini))
}
.rel.sdata : {
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
}
PROVIDE (etext = .);
_etext = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : { KEEP (*(.eh_frame)) }
.gcc_except_table : { *(.gcc_except_table*) }
.jcr : { KEEP (*(.jcr)) }
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
. = .;
.MIPS.abiflags : {
__MIPS_abiflags_start = .;
*(.MIPS.abiflags)
__MIPS_abiflags_end = .;
}
.rodata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
}
_rom_data_copy = .;
.data ALIGN(__memory_base + 0x1000, 16) :
AT (_rom_data_copy)
{
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_gp = . + 0x8000;
__global = _gp;
*(.lit8)
*(.lit4)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
PROVIDE (edata = .);
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
}
. = ALIGN(4);
PROVIDE (end = .);
_end = .;
/* Now place the data that is only needed within start.S and can be
overwritten by the heap. */
.startdata : {
*(.startdata)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Special sections generated by gcc */
/* Newer GNU linkers strip by default */
.mdebug.abi32 0 : { KEEP(*(.mdebug.abi32)) }
.mdebug.abiN32 0 : { KEEP(*(.mdebug.abiN32)) }
.mdebug.abi64 0 : { KEEP(*(.mdebug.abi64)) }
.mdebug.abiO64 0 : { KEEP(*(.mdebug.abiO64)) }
.mdebug.eabi32 0 : { KEEP(*(.mdebug.eabi32)) }
.mdebug.eabi64 0 : { KEEP(*(.mdebug.eabi64)) }
.gcc_compiled_long32 0 : { KEEP(*(.gcc_compiled_long32)) }
.gcc_compiled_long64 0 : { KEEP(*(.gcc_compiled_long64)) }
}

1
cpu/mips_pic32mz/p32mz2048efg100/Makefile

@ -0,0 +1 @@
include $(RIOTBASE)/Makefile.base

6288
cpu/mips_pic32mz/p32mz2048efg100/p32mz2048efg100.S

File diff suppressed because it is too large Load Diff
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