Merge pull request #6814 from haukepetersen/add_board_nucleo-l476
boards: added support for nucleo-l476 (stm32l4)pr/rotary
Alexandre Abadie
6 years ago
committed by
GitHub
commit
340ed33ca6
@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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@ -0,0 +1 @@
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include $(RIOTBOARD)/nucleo-common/Makefile.dep
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@ -0,0 +1,13 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# load the common Makefile.features for Nucleo boards
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include $(RIOTBOARD)/nucleo-common/Makefile.features
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m4_2
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@ -0,0 +1,6 @@
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## the cpu to build for
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export CPU = stm32l4
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export CPU_MODEL = stm32l476rg
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/nucleo-common/Makefile.include
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-l476
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo-l476 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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/* initialize the boards LED only if explicitly enabled (pin is already used
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* for SPI_DEV(0)) */
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#ifdef AUTO_INIT_LED0
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gpio_init(LED0_PIN, GPIO_OUT);
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#endif
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}
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@ -0,0 +1,5 @@
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source [find interface/stlink-v2-1.cfg]
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transport select hla_swd
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source [find target/stm32l4x.cfg]
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@ -0,0 +1,37 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-l476 Nucleo-L476
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* @ingroup boards
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* @brief Board specific files for the nucleo-l476 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo-l476 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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@ -0,0 +1,242 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-l476
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l476 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR1_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR1_USART3EN,
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.rx_pin = GPIO_PIN(PORT_C, 11),
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.tx_pin = GPIO_PIN(PORT_C, 10),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_1_ISR (isr_usart3)
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#define UART_2_ISR (isr_usart1)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @brief PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM2,
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
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{ .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} },
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.af = GPIO_AF1,
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.bus = APB1
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},
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR1_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF2,
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.bus = APB1
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},
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{
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.dev = TIM8,
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.rcc_mask = RCC_APB2ENR_TIM8EN,
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.chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
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{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
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.af = GPIO_AF3,
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.bus = APB2
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 20000000Hz */
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7, /* -> 78125Hz */
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5, /* -> 312500Hz */
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3, /* -> 1250000Hz */
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1, /* -> 5000000Hz */
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0 /* -> 10000000Hz */
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},
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{ /* for APB2 @ 40000000Hz */
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7, /* -> 156250Hz */
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6, /* -> 312500Hz */
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4, /* -> 1250000Hz */
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2, /* -> 5000000Hz */
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1 /* -> 10000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @brief ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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@ -0,0 +1,10 @@
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# define the module that is build
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MODULE = cpu
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# add a list of subdirectories, that should also be build
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DIRS += periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/stm32_common
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# (file triggers compiler bug. see #5775)
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SRC_NOLTO += vectors.c
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include $(RIOTBASE)/Makefile.base
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@ -0,0 +1,5 @@
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export CPU_ARCH = cortex-m4f
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export CPU_FAM = stm32l4
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTCPU)/Makefile.include.cortexm_common
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@ -0,0 +1,180 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32l4
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "irq.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
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#error "Please provide the PLL configuration in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (48000000) /* MSI @ 48MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#endif
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/**check configuration and get the corresponding bitfields */
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#elif (CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#else
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#error "PLL configuration: PLL R value is invalid"
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#endif
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#if (CLOCK_CORECLOCK <= 16000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
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#elif (CLOCK_CORECLOCK <= 32000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
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#elif (CLOCK_CORECLOCK <= 48000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
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#elif (CLOCK_CORECLOCK <= 64000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
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#else
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
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#endif
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/** @} */
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/**
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* @brief Configure the STM32L4's clock system
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*
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* We use the following configuration:
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* - we always enable the 32kHz low speed clock (LSI or LSE)
|
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* - we configure the MSI clock to 48MHz (for USB and RNG) and enable it
|
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* - if LSE present, we use it to stabilize the 48MHz MSI clock (MSIPLLEN)
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* - use either MSI @ 48MHz or HSE (4 to 48MHZ) as base clock
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* - we use the PLL as main clock provider
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* - we don't enable any ASI clock
|
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*
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* For the computation of the PLL configuration, see defines above.
|
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*/
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static void cpu_clock_init(void)
|
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{
|
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/* disable any interrupts. Global interrupts could be enabled if this is
|
||||
* called from some kind of bootloader... */
|
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unsigned is = irq_disable();
|
||||
RCC->CIER = 0;
|
||||
|
||||
/* for the duration of the configuration, we fall-back to the maximum number
|
||||
* of flash wait states */
|
||||
FLASH->ACR = (FLASH_ACR_LATENCY_4WS);
|
||||
|
||||
/* reset clock to MSI with 48MHz, disables all other clocks */
|
||||
RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
|
||||
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||
|
||||
/* use MSI as system clock while we do any further configuration and
|
||||
* configure the AHB and APB clock dividers as configure by the board */
|
||||
RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV |
|
||||
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_MSI) {}
|
||||
|
||||
/* configure the low speed clock domain (LSE vs LSI) */
|
||||
#if CLOCK_LSE
|
||||
/* allow write access to backup domain */
|
||||
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
|
||||
PWR->CR1 |= PWR_CR1_DBP;
|
||||
/* enable LSE */
|
||||
RCC->BDCR = RCC_BDCR_LSEON;
|
||||
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
|
||||
/* disable write access to back domain when done */
|
||||
PWR->CR1 &= ~(PWR_CR1_DBP);
|
||||
periph_clk_dis(APB1, RCC_APB1ENR1_PWREN);
|
||||
|
||||
/* now we can enable the MSI PLL mode */
|
||||
RCC->CR |= RCC_CR_MSIPLLEN;
|
||||
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
|
||||
#else
|
||||
RCC->CSR = RCC_CSR_LSION;
|
||||
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
|
||||
#endif
|
||||
|
||||
/* if configured: enable the HSE clock */
|
||||
#if CLOCK_HSE
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
#endif
|
||||
|
||||
/* next we configure and enable the PLL */
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
/* now tell the system to use the PLL as main clock */
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
|
||||
|
||||
/* finally we enable I+D cashes, pre-fetch, and we set the actual number of
|
||||
* needed flash wait states */
|
||||
FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN |
|
||||
FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
|
||||
|
||||
irq_restore(is);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the CPU, set IRQ priorities
|
||||
*/
|
||||
void cpu_init(void)
|
||||
{
|
||||
/* initialize the Cortex-M core */
|
||||
cortexm_init();
|
||||
/* initialize the clock system */
|
||||
cpu_clock_init();
|
||||
/* trigger static peripheral initialization */
|
||||
periph_init();
|
||||
}
|
||||
@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup cpu_stm32l4 STM32L4
|
||||
* @brief STM32L4 specific code
|
||||
* @ingroup cpu
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation specific CPU configuration options
|
||||
*
|
||||
* @author Hauke Petersen <hauke.pertersen@fu-berlin.de>
|
||||
*/
|
||||
|
||||
#ifndef STM32L4_CPU_CONF_H
|
||||
#define STM32L4_CPU_CONF_H
|
||||
|
||||
#include "cpu_conf_common.h"
|
||||
|
||||
#ifdef CPU_MODEL_STM32L476RG
|
||||
#include "vendor/stm32l476xx.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ARM Cortex-M specific CPU configuration
|
||||
* @{
|
||||
*/
|
||||
#define CPU_DEFAULT_IRQ_PRIO (1U)
|
||||
#define CPU_IRQ_NUMOF (82U)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32L4_CPU_CONF_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific definitions for internal peripheral handling
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PERIPH_CPU_H
|
||||
#define PERIPH_CPU_H
|
||||
|
||||
#include "periph_cpu_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Available ports
|
||||
*/
|
||||
enum {
|
||||
PORT_A = 0, /**< port A */
|
||||
PORT_B = 1, /**< port B */
|
||||
PORT_C = 2, /**< port C */
|
||||
PORT_D = 3, /**< port D */
|
||||
PORT_E = 4, /**< port E */
|
||||
PORT_F = 5, /**< port F */
|
||||
PORT_G = 6, /**< port G */
|
||||
PORT_H = 7, /**< port H */
|
||||
};
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override ADC resolution values
|
||||
* @{
|
||||
*/
|
||||
#define HAVE_ADC_RES_T
|
||||
typedef enum {
|
||||
ADC_RES_6BIT = (0x3 << 3), /**< ADC resolution: 6 bit */
|
||||
ADC_RES_8BIT = (0x2 << 3), /**< ADC resolution: 8 bit */
|
||||
ADC_RES_10BIT = (0x1 << 3), /**< ADC resolution: 10 bit */
|
||||
ADC_RES_12BIT = (0x0 << 3), /**< ADC resolution: 12 bit */
|
||||
ADC_RES_14BIT = (0xfe), /**< not applicable */
|
||||
ADC_RES_16BIT = (0xff) /**< not applicable */
|
||||
} adc_res_t;
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief ADC line configuration values
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin to use */
|
||||
uint8_t chan; /**< internal channel the pin is connected to */
|
||||
} adc_conf_t;
|
||||
|
||||
/**
|
||||
* @brief DAC line configuration data
|
||||
*/
|
||||
typedef struct {
|
||||
gpio_t pin; /**< pin connected to the line */
|
||||
uint8_t chan; /**< DAC device used for this line */
|
||||
} dac_conf_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H */
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L476RG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
|
||||
}
|
||||
|
||||
_cpuid_address = ORIGIN(cpuid);
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -0,0 +1,5 @@
|
||||
# define the module name
|
||||
MODULE = periph
|
||||
|
||||
# include RIOTs generic Makefile
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Interrupt vector definitions
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "vectors_cortexm.h"
|
||||
|
||||
/* get the start of the ISR stack as defined in the linkerscript */
|
||||
extern uint32_t _estack;
|
||||
|
||||
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||
* as the alias definition */
|
||||
void dummy_handler(void) {
|
||||
dummy_handler_default();
|
||||
}
|
||||
|
||||
/* Cortex-M common interrupt vectors */
|
||||
WEAK_DEFAULT void isr_svc(void);
|
||||
WEAK_DEFAULT void isr_pendsv(void);
|
||||
WEAK_DEFAULT void isr_systick(void);
|
||||
/* STM32L4 specific interrupt vectors */
|
||||
WEAK_DEFAULT void isr_wwdg(void);
|
||||
WEAK_DEFAULT void isr_pvd_pvm(void);
|
||||
WEAK_DEFAULT void isr_tamp_stamp(void);
|
||||
WEAK_DEFAULT void isr_rtc_wkup(void);
|
||||
WEAK_DEFAULT void isr_flash(void);
|
||||
WEAK_DEFAULT void isr_rcc(void);
|
||||
WEAK_DEFAULT void isr_exti(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel1(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel2(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel3(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel4(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel5(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel6(void);
|
||||
WEAK_DEFAULT void isr_dma1_channel7(void);
|
||||
WEAK_DEFAULT void isr_adc1_2(void);
|
||||
WEAK_DEFAULT void isr_can1_tx(void);
|
||||
WEAK_DEFAULT void isr_can1_rx0(void);
|
||||
WEAK_DEFAULT void isr_can1_rx1(void);
|
||||
WEAK_DEFAULT void isr_can1_sce(void);
|
||||
WEAK_DEFAULT void isr_tim1_brk_tim15(void);
|
||||
WEAK_DEFAULT void isr_tim1_up_tim16(void);
|
||||
WEAK_DEFAULT void isr_tim1_trg_com_tim17(void);
|
||||
WEAK_DEFAULT void isr_tim1_cc(void);
|
||||
WEAK_DEFAULT void isr_tim2(void);
|
||||
WEAK_DEFAULT void isr_tim3(void);
|
||||
WEAK_DEFAULT void isr_tim4(void);
|
||||
WEAK_DEFAULT void isr_i2c1_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c1_er(void);
|
||||
WEAK_DEFAULT void isr_i2c2_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c2_er(void);
|
||||
WEAK_DEFAULT void isr_spi1(void);
|
||||
WEAK_DEFAULT void isr_spi2(void);
|
||||
WEAK_DEFAULT void isr_usart1(void);
|
||||
WEAK_DEFAULT void isr_usart2(void);
|
||||
WEAK_DEFAULT void isr_usart3(void);
|
||||
WEAK_DEFAULT void isr_rtc_alarm(void);
|
||||
WEAK_DEFAULT void isr_dfsdm1_flt3(void);
|
||||
WEAK_DEFAULT void isr_tim8_brk(void);
|
||||
WEAK_DEFAULT void isr_tim8_up(void);
|
||||
WEAK_DEFAULT void isr_tim8_trg_com(void);
|
||||
WEAK_DEFAULT void isr_tim8_cc(void);
|
||||
WEAK_DEFAULT void isr_adc3(void);
|
||||
WEAK_DEFAULT void isr_fmc(void);
|
||||
WEAK_DEFAULT void isr_sdmmc1(void);
|
||||
WEAK_DEFAULT void isr_tim5(void);
|
||||
WEAK_DEFAULT void isr_spi3(void);
|
||||
WEAK_DEFAULT void isr_uart4(void);
|
||||
WEAK_DEFAULT void isr_uart5(void);
|
||||
WEAK_DEFAULT void isr_tim6_dac(void);
|
||||
WEAK_DEFAULT void isr_tim7(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel1(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel2(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel3(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel4(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel5(void);
|
||||
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
|
||||
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
|
||||
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
|
||||
WEAK_DEFAULT void isr_comp(void);
|
||||
WEAK_DEFAULT void isr_lptim1(void);
|
||||
WEAK_DEFAULT void isr_lptim2(void);
|
||||
WEAK_DEFAULT void isr_otg_fs(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel6(void);
|
||||
WEAK_DEFAULT void isr_dma2_channel7(void);
|
||||
WEAK_DEFAULT void isr_lpuart1(void);
|
||||
WEAK_DEFAULT void isr_quadspi(void);
|
||||
WEAK_DEFAULT void isr_i2c3_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c3_er(void);
|
||||
WEAK_DEFAULT void isr_sai1(void);
|
||||
WEAK_DEFAULT void isr_sai2(void);
|
||||
WEAK_DEFAULT void isr_swpmi1(void);
|
||||
WEAK_DEFAULT void isr_tsc(void);
|
||||
WEAK_DEFAULT void isr_lcd(void);
|
||||
WEAK_DEFAULT void isr_0(void);
|
||||
WEAK_DEFAULT void isr_rng(void);
|
||||
WEAK_DEFAULT void isr_fpu(void);
|
||||
|
||||
/* interrupt vector table */
|
||||
ISR_VECTORS const void *interrupt_vector[] = {
|
||||
/* Exception stack pointer */
|
||||
(void*) (&_estack), /* pointer to the top of the stack */
|
||||
/* Cortex-M4 handlers */
|
||||
(void*) reset_handler_default, /* entry point of the program */
|
||||
(void*) nmi_default, /* non maskable interrupt handler */
|
||||
(void*) hard_fault_default, /* hard fault exception */
|
||||
(void*) mem_manage_default, /* memory manage exception */
|
||||
(void*) bus_fault_default, /* bus fault exception */
|
||||
(void*) usage_fault_default, /* usage fault exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_svc, /* system call interrupt, in RIOT used for
|
||||
* switching into thread context on boot */
|
||||
(void*) debug_mon_default, /* debug monitor exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
|
||||
* context switching is happening here */
|
||||
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
|
||||
/* STM specific peripheral handlers */
|
||||
(void*) isr_wwdg,
|
||||
(void*) isr_pvd_pvm,
|
||||
(void*) isr_tamp_stamp,
|
||||
(void*) isr_rtc_wkup,
|
||||
(void*) isr_flash,
|
||||
(void*) isr_rcc,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_dma1_channel1,
|
||||
(void*) isr_dma1_channel2,
|
||||
(void*) isr_dma1_channel3,
|
||||
(void*) isr_dma1_channel4,
|
||||
(void*) isr_dma1_channel5,
|
||||
(void*) isr_dma1_channel6,
|
||||
(void*) isr_dma1_channel7,
|
||||
(void*) isr_adc1_2,
|
||||
(void*) isr_can1_tx,
|
||||
(void*) isr_can1_rx0,
|
||||
(void*) isr_can1_rx1,
|
||||
(void*) isr_can1_sce,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_tim1_brk_tim15,
|
||||
(void*) isr_tim1_up_tim16,
|
||||
(void*) isr_tim1_trg_com_tim17,
|
||||
(void*) isr_tim1_cc,
|
||||
(void*) isr_tim2,
|
||||
(void*) isr_tim3,
|
||||
(void*) isr_tim4,
|
||||
(void*) isr_i2c1_ev,
|
||||
(void*) isr_i2c1_er,
|
||||
(void*) isr_i2c2_ev,
|
||||
(void*) isr_i2c2_er,
|
||||
(void*) isr_spi1,
|
||||
(void*) isr_spi2,
|
||||
(void*) isr_usart1,
|
||||
(void*) isr_usart2,
|
||||
(void*) isr_usart3,
|
||||
(void*) isr_exti,
|
||||
(void*) isr_rtc_alarm,
|
||||
(void*) isr_dfsdm1_flt3,
|
||||
(void*) isr_tim8_brk,
|
||||
(void*) isr_tim8_up,
|
||||
(void*) isr_tim8_trg_com,
|
||||
(void*) isr_tim8_cc,
|
||||
(void*) isr_adc3,
|
||||
(void*) isr_fmc,
|
||||
(void*) isr_sdmmc1,
|
||||
(void*) isr_tim5,
|
||||
(void*) isr_spi3,
|
||||
(void*) isr_uart4,
|
||||
(void*) isr_uart5,
|
||||
(void*) isr_tim6_dac,
|
||||
(void*) isr_tim7,
|
||||
(void*) isr_dma2_channel1,
|
||||
(void*) isr_dma2_channel2,
|
||||
(void*) isr_dma2_channel3,
|
||||
(void*) isr_dma2_channel4,
|
||||
(void*) isr_dma2_channel5,
|
||||
(void*) isr_dfsdm1_flt0,
|
||||
(void*) isr_dfsdm1_flt1,
|
||||
(void*) isr_dfsdm1_flt2,
|
||||
(void*) isr_comp,
|
||||
(void*) isr_lptim1,
|
||||
(void*) isr_lptim2,
|
||||
(void*) isr_otg_fs,
|
||||
(void*) isr_dma2_channel6,
|
||||
(void*) isr_dma2_channel7,
|
||||
(void*) isr_lpuart1,
|
||||
(void*) isr_quadspi,
|
||||
(void*) isr_i2c3_ev,
|
||||
(void*) isr_i2c3_er,
|
||||
(void*) isr_sai1,
|
||||
(void*) isr_sai2,
|
||||
(void*) isr_swpmi1,
|
||||
(void*) isr_tsc,
|
||||
(void*) isr_lcd,
|
||||
(void*) (0UL),
|
||||
(void*) isr_rng,
|
||||
(void*) isr_fpu
|
||||
};
|
||||
Loading…
Reference in New Issue