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cpu/stm32f1: reworked timer driver

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pr/gpio
Hauke Petersen 7 years ago
parent 28976ec126
commit 360e392d69
3 changed files with 132 additions and 321 deletions
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8
cpu/stm32_common/include/periph_cpu_common.h
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@ -39,6 +39,14 @@ extern "C" {
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/**
* @brief Available peripheral buses
*/
enum {
APB1,
APB2
};
#ifdef __cplusplus
}
#endif

20
cpu/stm32f1/include/periph_cpu.h
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@ -43,6 +43,16 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief All timers for the STM32F1 have 4 CC channels
*/
#define TIMER_CHANNELS (4U)
/**
* @brief All timers have a width of 16-bit
*/
#define TIMER_MAXVAL (0xffff)
/**
* @brief Override values for pull register configuration
* @{
@ -91,6 +101,16 @@ typedef enum {
GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */
} gpio_af_out_t;
/**
* @brief Timer configuration
*/
typedef struct {
TIM_TypeDef *dev; /**< timer device */
uint8_t bus; /**< APBx bus the timer is clock from */
uint8_t rcc_bit; /**< corresponding bit in the RCC register */
uint8_t irqn; /**< global IRQ channel */
} timer_conf_t;
/**
* @brief Configure the alternate function for the given pin
*

425
cpu/stm32f1/periph/timer.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -19,386 +19,169 @@
* @}
*/
#include <stdlib.h>
#include "cpu.h"
#include "board.h"
#include "periph_conf.h"
#include "periph/timer.h"
#include "sched.h"
#include "thread.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/* guard file in case no TIMER device is defined */
#if TIMER_0_EN || TIMER_1_EN
static inline void irq_handler(tim_t timer, TIM_TypeDef *dev0, TIM_TypeDef *dev1);
#include "periph/timer.h"
/**
* Timer state memory
* @brief Interrupt context for each configured timer
*/
static timer_isr_ctx_t config[TIMER_NUMOF];
static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
/**
* @brief Get the timer device
*/
static inline TIM_TypeDef *dev(tim_t tim)
{
TIM_TypeDef *timer0;
TIM_TypeDef *timer1;
uint8_t trigger_selector;
return timer_config[tim].dev;
}
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* enable timer peripheral clock */
TIMER_0_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_0_IRQ_CHAN_0, TIMER_0_IRQ_PRIO);
NVIC_SetPriority(TIMER_0_IRQ_CHAN_1, TIMER_0_IRQ_PRIO);
/* select timer */
timer0 = TIMER_0_DEV_0;
timer1 = TIMER_0_DEV_1;
trigger_selector = TIMER_0_TRIG_SEL;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* enable timer peripheral clock */
TIMER_1_CLKEN();
/* set timer's IRQ priority */
NVIC_SetPriority(TIMER_1_IRQ_CHAN_0, TIMER_1_IRQ_PRIO);
NVIC_SetPriority(TIMER_1_IRQ_CHAN_1, TIMER_1_IRQ_PRIO);
/* select timer */
timer0 = TIMER_1_DEV_0;
timer1 = TIMER_1_DEV_1;
trigger_selector = TIMER_1_TRIG_SEL;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
/**
* @brief Enable the peripheral clock for the given timer
*/
static void clk_en(tim_t tim)
{
if (timer_config[tim].bus == APB1) {
RCC->APB1ENR |= timer_config[tim].rcc_bit;
}
else {
RCC->APB2ENR |= timer_config[tim].rcc_bit;
}
}
/* set callback function */
config[dev].cb = cb;
config[dev].arg = arg;
int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
{
/* check if device is valid */
if (tim >= TIMER_NUMOF) {
return -1;
}
/* set timer to run in counter mode */
timer0->CR1 = (TIM_CR1_ARPE | TIM_CR1_URS);
timer1->CR1 = TIM_CR1_URS;
/* remember the interrupt context */
isr_ctx[tim].cb = cb;
isr_ctx[tim].arg = arg;
/* configure master timer0 */
/* send update event as trigger output */
timer0->CR2 |= TIM_CR2_MMS_1;
/* set auto-reload and prescaler values and load new values */
timer0->ARR = 0xFFFF;
timer0->PSC = (TIMER_0_FREQ / freq) - 1;
// timer->EGR |= TIM_EGR_UG;
/* enable the peripheral clock */
clk_en(tim);
/* configure slave timer1 */
/* get input trigger */
timer1->SMCR |= trigger_selector;
/* external clock mode 1 */
timer1->SMCR |= TIM_SMCR_SMS;
/* configure the timer as upcounter in continuous mode */
dev(tim)->CR1 = 0;
dev(tim)->CR2 = 0;
dev(tim)->ARR = TIMER_MAXVAL;
/* set prescaler */
dev(tim)->PSC = ((CLOCK_CORECLOCK / freq) - 1);
/* generate an update event to apply our configuration */
dev(tim)->EGR = TIM_EGR_UG;
/* enable the timer's interrupt */
timer_irq_enable(dev);
/* start the timer */
timer_start(dev);
timer_irq_enable(tim);
/* reset the counter and start the timer */
timer_start(tim);
return 0;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
int timer_set(tim_t tim, int channel, unsigned int timeout)
{
int now = timer_read(dev);
return timer_set_absolute(dev, channel, now + timeout - 1);
int now = timer_read(tim);
return timer_set_absolute(tim, channel, now + timeout);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
int timer_set_absolute(tim_t tim, int channel, unsigned int value)
{
TIM_TypeDef *timer0;
TIM_TypeDef *timer1;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* select timer */
timer0 = TIMER_0_DEV_0;
timer1 = TIMER_0_DEV_1;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* select timer */
timer0 = TIMER_1_DEV_0;
timer1 = TIMER_1_DEV_1;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
if (channel >= TIMER_CHANNELS) {
return -1;
}
timer0->DIER &= ~TIM_DIER_UIE;
dev(tim)->CCR[channel] = (value & TIMER_MAXVAL);
dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
switch (channel) {
case 0:
timer0->CCR1 = (0xffff & value);
timer1->CCR1 = (value >> 16);
timer0->SR &= ~TIM_SR_CC1IF;
timer0->DIER |= TIM_DIER_CC1IE;
DEBUG("Channel 1 set to %x\n", value);
break;
case 1:
timer0->CCR2 = (0xffff & value);
timer1->CCR2 = (value >> 16);
timer0->SR &= ~TIM_SR_CC2IF;
timer0->DIER |= TIM_DIER_CC2IE;
DEBUG("Channel 2 set to %x\n", value);
break;
case 2:
timer0->CCR3 = (0xffff & value);
timer1->CCR3 = (value >> 16);
timer0->SR &= ~TIM_SR_CC3IF;
timer0->DIER |= TIM_DIER_CC3IE;
DEBUG("Channel 3 set to %x\n", value);
break;
case 3:
timer0->CCR4 = (0xffff & value);
timer1->CCR4 = (value >> 16);
timer0->SR &= ~TIM_SR_CC4IF;
timer0->DIER |= TIM_DIER_CC4IE;
DEBUG("Channel 4 set to %x\n", value);
break;
default:
return -1;
}
return 0;
}
int timer_clear(tim_t dev, int channel)
int timer_clear(tim_t tim, int channel)
{
TIM_TypeDef *timer0;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
timer0 = TIMER_0_DEV_0;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
timer0 = TIMER_1_DEV_0;
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
switch (channel) {
case 0:
timer0->DIER &= ~TIM_DIER_CC1IE;
break;
case 1:
timer0->DIER &= ~TIM_DIER_CC2IE;
break;
case 2:
timer0->DIER &= ~TIM_DIER_CC3IE;
break;
case 3:
timer0->DIER &= ~TIM_DIER_CC4IE;
break;
default:
return -1;
if (channel >= TIMER_CHANNELS) {
return -1;
}
dev(tim)->DIER &= ~(TIM_DIER_CC1IE << channel);
return 0;
}
unsigned int timer_read(tim_t dev)
unsigned int timer_read(tim_t tim)
{
unsigned a, b;
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* do OR'ing two times and only use value if results are equal.
* otherwise, the lower 16bit counter could overflow while the
* upper counter is read, leading to an incorrect result. */
do {
a = (((unsigned int)(0xffff & TIMER_0_DEV_0->CNT)) |
(TIMER_0_DEV_1->CNT<<16));
b = (((unsigned int)(0xffff & TIMER_0_DEV_0->CNT)) |
(TIMER_0_DEV_1->CNT<<16));
} while (a!=b);
return (unsigned int)dev(tim)->CNT;
}
return a;
#endif
#if TIMER_1_EN
case TIMER_1:
/* see above about why loop is needed */
do {
a = (((unsigned int)(0xffff & TIMER_1_DEV_0->CNT)) |
(TIMER_1_DEV_1->CNT<<16));
b = (((unsigned int)(0xffff & TIMER_1_DEV_0->CNT)) |
(TIMER_1_DEV_1->CNT<<16));
} while (a!=b);
void timer_start(tim_t tim)
{
dev(tim)->CR1 |= TIM_CR1_CEN;
}
return a;
#endif
case TIMER_UNDEFINED:
default:
return 0;
}
void timer_stop(tim_t tim)
{
dev(tim)->CR1 &= ~(TIM_CR1_CEN);
}
void timer_start(tim_t dev)
void timer_irq_enable(tim_t tim)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
/* slave has to be enabled first */
TIMER_0_DEV_1->CR1 |= TIM_CR1_CEN;
TIMER_0_DEV_0->CR1 |= TIM_CR1_CEN;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* slave has to be enabled first */
TIMER_1_DEV_1->CR1 |= TIM_CR1_CEN;
TIMER_1_DEV_0->CR1 |= TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
NVIC_EnableIRQ(timer_config[tim].irqn);
}
void timer_stop(tim_t dev)
void timer_irq_disable(tim_t tim)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV_0->CR1 &= ~TIM_CR1_CEN;
TIMER_0_DEV_1->CR1 &= ~TIM_CR1_CEN;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER_1_DEV_0->CR1 &= ~TIM_CR1_CEN;
TIMER_1_DEV_1->CR1 &= ~TIM_CR1_CEN;
break;
#endif
case TIMER_UNDEFINED:
break;
}
NVIC_DisableIRQ(timer_config[tim].irqn);
}
void timer_irq_enable(tim_t dev)
static inline void irq_handler(tim_t tim)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_EnableIRQ(TIMER_0_IRQ_CHAN_0);
NVIC_EnableIRQ(TIMER_0_IRQ_CHAN_1);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
NVIC_EnableIRQ(TIMER_1_IRQ_CHAN_0);
NVIC_EnableIRQ(TIMER_1_IRQ_CHAN_1);
break;
#endif
case TIMER_UNDEFINED:
break;
uint32_t status = (dev(tim)->SR & dev(tim)->DIER);
for (unsigned int i = 0; i < TIMER_CHANNELS; i++) {
if (status & (TIM_SR_CC1IF << i)) {
dev(tim)->DIER &= ~(TIM_DIER_CC1IE << i);
isr_ctx[tim].cb(isr_ctx[tim].arg, i);
}
}
if (sched_context_switch_request) {
thread_yield();
}
}
void timer_irq_disable(tim_t dev)
#ifdef TIMER_0_ISR
void TIMER_0_ISR(void)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
NVIC_DisableIRQ(TIMER_0_IRQ_CHAN_0);
NVIC_DisableIRQ(TIMER_0_IRQ_CHAN_1);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
NVIC_DisableIRQ(TIMER_1_IRQ_CHAN_0);
NVIC_DisableIRQ(TIMER_1_IRQ_CHAN_1);
break;
#endif
case TIMER_UNDEFINED:
break;
}
irq_handler(0);
}
#endif
#if TIMER_0_EN
void TIMER_0_ISR_0(void)
#ifdef TIMER_1_ISR
void TIMER_1_ISR(void)
{
DEBUG("\nenter ISR\n");
irq_handler(TIMER_0, TIMER_0_DEV_0, TIMER_0_DEV_1);
DEBUG("leave ISR\n\n");
irq_handler(1);
}
#endif
#if TIMER_1_EN
void TIMER_1_ISR_0(void)
#ifdef TIMER_2_ISR
void TIMER_2_ISR(void)
{
irq_handler(TIMER_1, TIMER_1_DEV_0, TIMER_1_DEV_1);
irq_handler(2);
}
#endif
static inline void irq_handler(tim_t timer, TIM_TypeDef *dev0, TIM_TypeDef *dev1)
#ifdef TIMER_3_ISR
void TIMER_3_ISR(void)
{
DEBUG("CNT: %08x SR/DIER: %08x\n", ((dev1->CNT<<16) | (0xffff & dev0->CNT)),
((dev0->SR<<16) | (0xffff & dev0->DIER)));
irq_handler(3);
}
#endif
if ((dev0->SR & TIM_SR_CC1IF) && (dev0->DIER & TIM_DIER_CC1IE)) {
/* clear interrupt anyway */
dev0->SR &= ~TIM_SR_CC1IF;
/* if higher 16bit also match */
if (dev1->CNT >= dev1->CCR1) {
dev0->DIER &= ~TIM_DIER_CC1IE;
config[timer].cb(config[timer].arg, 0);
}
DEBUG("channel 1 CCR: %08x\n", ((dev1->CCR1<<16) | (0xffff & dev0->CCR1)));
}
else if ((dev0->SR & TIM_SR_CC2IF) && (dev0->DIER & TIM_DIER_CC2IE)) {
/* clear interrupt anyway */
dev0->SR &= ~TIM_SR_CC2IF;
/* if higher 16bit also match */
if (dev1->CNT >= dev1->CCR2) {
dev0->DIER &= ~TIM_DIER_CC2IE;
config[timer].cb(config[timer].arg, 1);
}
DEBUG("channel 2 CCR: %08x\n", ((dev1->CCR2<<16) | (0xffff & dev0->CCR2)));
}
else if ((dev0->SR & TIM_SR_CC3IF) && (dev0->DIER & TIM_DIER_CC3IE)) {
/* clear interrupt anyway */
dev0->SR &= ~TIM_SR_CC3IF;
/* if higher 16bit also match */
if (dev1->CNT >= dev1->CCR3) {
dev0->DIER &= ~TIM_DIER_CC3IE;
config[timer].cb(config[timer].arg, 2);
}
DEBUG("channel 3 CCR: %08x\n", ((dev1->CCR3<<16) | (0xffff & dev0->CCR3)));
}
else if ((dev0->SR & TIM_SR_CC4IF) && (dev0->DIER & TIM_DIER_CC4IE)) {
/* clear interrupt anyway */
dev0->SR &= ~TIM_SR_CC4IF;
/* if higher 16bit also match */
if (dev1->CNT >= dev1->CCR4) {
dev0->DIER &= ~TIM_DIER_CC4IE;
config[timer].cb(config[timer].arg, 3);
}
DEBUG("channel 4 CCR: %08x\n", ((dev1->CCR4<<16) | (0xffff & dev0->CCR4)));
}
else {
dev0->SR = 0;
}
if (sched_context_switch_request) {
thread_yield();
}
#ifdef TIMER_4_ISR
void TIMER_4_ISR(void)
{
irq_handler(4);
}
#endif /* TIMER_0_EN || TIMER_1_EN */
#endif

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