Merge pull request #3530 from kaspar030/update_msba2
cpu: lpc2387: provide periph/* implementations, update to use newlib module.dev/timer
Hauke Petersen
8 years ago
commit
3922b6c852
@ -1,2 +1,4 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_MCU_GROUP = arm7
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@ -1,3 +0,0 @@
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ifneq (,$(filter ltc4150,$(USEMODULE)))
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USEMODULE += gpioint
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endif
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@ -1,50 +0,0 @@
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/*
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* Copyright (C) 2008-2009, Freie Universitaet Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup msba2
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* @ingroup ltc4150
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* @{
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*/
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/**
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* @file
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* @brief LTC4150 MSB-A2 specific implemetation
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*
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* @author Heiko Will
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* @author Michael Baar
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#include <stdio.h>
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#include "lpc2387.h"
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#include "ltc4150_arch.h"
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#include "gpioint.h"
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void __attribute__((__no_instrument_function__)) ltc4150_disable_int(void)
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{
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gpioint_set(0, BIT4, GPIOINT_DISABLE, NULL);
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}
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void __attribute__((__no_instrument_function__)) ltc4150_enable_int(void)
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{
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gpioint_set(0, BIT4, GPIOINT_FALLING_EDGE, <c4150_interrupt);
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}
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void __attribute__((__no_instrument_function__)) ltc4150_sync_blocking(void)
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{
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while (!(FIO0PIN & BIT4)) {};
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}
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void __attribute__((__no_instrument_function__)) ltc4150_arch_init(void)
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{
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FIO0DIR |= BIT5;
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FIO0SET = BIT5;
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}
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/** @} */
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@ -1,205 +0,0 @@
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/*
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* Copyright (C) 2008-2009, Freie Universitaet Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/*
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* debug_uart.c: provides initial serial debug output
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Heiko Will <hwill@inf.fu-berlin.de>
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include "lpc23xx.h"
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#include "VIC.h"
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#include "kernel.h"
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#include "board_uart0.h"
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/**
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* @file
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* @ingroup lpc2387
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*
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* @version $Revision$
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*
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* @note $Id$
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*/
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typedef struct toprint_t {
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unsigned int len;
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char content[];
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} toprint_t;
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#define QUEUESIZE 255
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static volatile toprint_t *queue[QUEUESIZE];
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static volatile unsigned char queue_head = 0;
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static volatile unsigned char queue_tail = 0;
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static volatile unsigned char queue_items = 0;
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static volatile unsigned int actual_pos = 0;
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static volatile unsigned int running = 0;
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static volatile unsigned int fifo = 0;
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static volatile toprint_t *actual = NULL;
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static inline void enqueue(void)
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{
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queue_items++;
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queue_tail++;
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}
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static inline void dequeue(void)
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{
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actual = (queue[queue_head]);
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queue_items--;
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queue_head++;
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}
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static void push_queue(void)
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{
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running = 1;
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lpm_prevent_sleep |= LPM_PREVENT_SLEEP_UART;
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start:
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if (!actual) {
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if (queue_items) {
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dequeue();
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}
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else {
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running = 0;
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lpm_prevent_sleep &= ~LPM_PREVENT_SLEEP_UART;
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if (!fifo)
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while (!(U0LSR & BIT6)) {};
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return;
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}
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}
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while ((actual_pos < actual->len) && (fifo++ < 16)) {
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U0THR = actual->content[actual_pos++];
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}
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if (actual_pos == actual->len) {
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free((void *)actual);
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actual = NULL;
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actual_pos = 0;
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goto start;
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}
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}
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int uart_active(void)
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{
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return (running || fifo);
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}
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void stdio_flush(void)
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{
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U0IER &= ~BIT1; // disable THRE interrupt
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while (running) {
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while (!(U0LSR & (BIT5 | BIT6))) {}; // transmit fifo
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fifo = 0;
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push_queue(); // dequeue to fifo
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}
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U0IER |= BIT1; // enable THRE interrupt
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}
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void UART0_IRQHandler(void) __attribute__((interrupt("IRQ")));
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void UART0_IRQHandler(void)
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{
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int iir;
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iir = U0IIR;
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switch (iir & UIIR_ID_MASK) {
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case UIIR_THRE_INT: // Transmit Holding Register Empty
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fifo = 0;
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push_queue();
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break;
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case UIIR_CTI_INT: // Character Timeout Indicator
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case UIIR_RDA_INT: // Receive Data Available
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#ifdef MODULE_UART0
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if (uart0_handler_pid != KERNEL_PID_UNDEF) {
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do {
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int c = U0RBR;
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uart0_handle_incoming(c);
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}
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while (U0LSR & ULSR_RDR);
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uart0_notify_thread();
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}
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#endif
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break;
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default:
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U0LSR;
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U0RBR;
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break;
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} // switch
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VICVectAddr = 0; // Acknowledge Interrupt
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}
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int uart0_puts(char *astring, int length)
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{
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/* while (queue_items == (QUEUESIZE-1)) {} ;
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U0IER = 0;
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queue[queue_tail] = malloc(length+sizeof(unsigned int));
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queue[queue_tail]->len = length;
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memcpy(&queue[queue_tail]->content,astring,length);
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enqueue();
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if (!running)
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push_queue();
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U0IER |= BIT0 | BIT1; // enable RX irq
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*/
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/* alternative without queue:*/
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int i;
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for (i = 0; i < length; i++) {
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while (!(U0LSR & BIT5));
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U0THR = astring[i];
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}
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/* */
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return length;
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}
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int
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bl_uart_init(void)
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{
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PCONP |= PCUART0; // power on
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// UART0 clock divider is CCLK/8
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PCLKSEL0 |= BIT6 + BIT7;
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U0LCR = 0x83; // 8 bits, no Parity, 1 Stop bit
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// TODO: UART Baudrate calculation using uart->config->speed
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/*
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* Baudrate calculation
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* BR = PCLK (9 MHz) / (16 x 256 x DLM + DLL) x (1/(DIVADDVAL/MULVAL))
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*/
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U0FDR = 0x92; // DIVADDVAL = 0010 = 2, MULVAL = 1001 = 9
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U0DLM = 0x00;
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U0DLL = 0x04;
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U0LCR = 0x03; // DLAB = 0
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U0FCR = 0x07; // Enable and reset TX and RX FIFO
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/* irq */
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install_irq(UART0_INT, UART0_IRQHandler, 6);
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U0IER |= BIT0; // enable only RX irq
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return 1;
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}
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@ -1,5 +1,7 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += config
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FEATURES_MCU_GROUP = arm7
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@ -1,2 +1,4 @@
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_MCU_GROUP = arm7
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@ -1 +0,0 @@
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include $(RIOTBASE)/Makefile.base
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@ -1,164 +0,0 @@
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/*
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* Copyright 2009, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup lpc2387
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* @{
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*/
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/**
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* @file
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* @brief LPC2387 GPIO Interrupt Multiplexer implementation
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*
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* @author Michael Baar <michael.baar@fu-berlin.de>
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* @version $Revision: 1508 $
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*
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* @note $Id: lpc2387-gpioint.c 1508 2009-10-26 15:10:02Z baar $
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* @see dev_gpioint
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*/
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#include <stdio.h>
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#include "lpc2387.h"
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#include "gpioint.h"
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#include "cpu.h"
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#include "irq.h"
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struct irq_callback_t {
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fp_irqcb callback;
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};
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static struct irq_callback_t gpioint0[32];
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static struct irq_callback_t gpioint2[32];
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void gpioint_init(void)
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{
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extern void GPIO_IRQHandler(void);
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/* GPIO Init */
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INTWAKE |= GPIO0WAKE | GPIO2WAKE; /* allow GPIO to wake up from power down */
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install_irq(GPIO_INT, &GPIO_IRQHandler, IRQP_GPIO); /* install irq handler */
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}
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/*---------------------------------------------------------------------------*/
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bool
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gpioint_set(int port, uint32_t bitmask, int flags, fp_irqcb callback)
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{
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struct irq_callback_t *cbdata;
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unsigned long bit;
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volatile unsigned long *en_f;
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volatile unsigned long *en_r;
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volatile unsigned long *en_clr;
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/* lookup registers */
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bit = bitarithm_msb(bitmask); /* get irq mapping table index */
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switch(port) {
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case 0: /* PORT0 */
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cbdata = gpioint0;
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en_f = &IO0_INT_EN_F;
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en_r = &IO0_INT_EN_R;
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en_clr = &IO0_INT_CLR;
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break;
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case 2: /* PORT2 */
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cbdata = gpioint2;
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en_f = &IO2_INT_EN_F;
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en_r = &IO2_INT_EN_R;
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en_clr = &IO2_INT_CLR;
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break;
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default: /* unsupported */
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return false; /* fail */
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}
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/* reconfigure irq */
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unsigned long cpsr = disableIRQ();
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*en_clr |= bitmask; /* clear interrupt */
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if ((flags & GPIOINT_FALLING_EDGE) != 0) {
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*en_f |= bitmask; /* enable falling edge */
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}
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else {
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*en_f &= ~bitmask; /* disable falling edge */
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}
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if ((flags & GPIOINT_RISING_EDGE) != 0) {
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*en_r |= bitmask; /* enable rising edge */
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}
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else {
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*en_r &= ~bitmask; /* disable rising edge */
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}
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if (((flags & (GPIOINT_FALLING_EDGE | GPIOINT_RISING_EDGE)) != 0)) {
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cbdata[bit].callback = callback;
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}
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else {
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cbdata[bit].callback = NULL; /* remove from interrupt mapping table */
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}
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restoreIRQ(cpsr);
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return true; /* success */
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}
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/*---------------------------------------------------------------------------*/
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static void __attribute__((__no_instrument_function__)) test_irq(int port, unsigned long f_mask, unsigned long r_mask, struct irq_callback_t *pcb)
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{
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(void) port;
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/* Test each bit of rising and falling masks, if set trigger interrupt
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* on corresponding device */
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do {
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if ((pcb->callback != NULL)) {
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if ((r_mask & 1) | (f_mask & 1)) {
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pcb->callback(); /* pass to handler */
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}
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}
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f_mask >>= 1UL;
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r_mask >>= 1UL;
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pcb++;
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}
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while ((f_mask != 0) || (r_mask != 0));
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}
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/*---------------------------------------------------------------------------*/
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void GPIO_IRQHandler(void) __attribute__((interrupt("IRQ")));
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/**
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* @brief GPIO Interrupt handler function
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* @internal
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*
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* Invoked whenever an activated gpio interrupt is triggered by a rising
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* or falling edge.
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*/
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void __attribute__((__no_instrument_function__)) GPIO_IRQHandler(void)
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{
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if (IO_INT_STAT & BIT0) { /* interrupt(s) on PORT0 pending */
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unsigned long int_stat_f = IO0_INT_STAT_F; /* save content */
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unsigned long int_stat_r = IO0_INT_STAT_R; /* save content */
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IO0_INT_CLR = int_stat_f; /* clear flags of fallen pins */
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IO0_INT_CLR = int_stat_r; /* clear flags of risen pins */
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test_irq(0, int_stat_f, int_stat_r, gpioint0);
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}
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if (IO_INT_STAT & BIT2) { /* interrupt(s) on PORT2 pending */
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unsigned long int_stat_f = IO2_INT_STAT_F; /* save content */
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unsigned long int_stat_r = IO2_INT_STAT_R; /* save content */
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IO2_INT_CLR = int_stat_f; /* clear flags of fallen pins */
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IO2_INT_CLR = int_stat_r; /* clear flags of risen pins */
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test_irq(2, int_stat_f, int_stat_r, gpioint2);
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}
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VICVectAddr = 0; /* Acknowledge Interrupt */
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}
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/*---------------------------------------------------------------------------*/
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/** @} */
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@ -0,0 +1,88 @@
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/*
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* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
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/**
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* @ingroup cpu_lpc2387
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#ifndef PERIPH_CPU_H_
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#define PERIPH_CPU_H_
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#include "cpu.h"
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#include "periph/dev_enums.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "cpu.h"
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/**
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* @brief LPC2387 MCU defines
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* @{
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*/
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#define __IO volatile
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/**
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* @brief Fast GPIO register definition struct
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*/
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typedef struct {
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__IO uint32_t DIR; /**< he */
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uint32_t _reserved[3]; /**< really */
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__IO uint32_t MASK; /**< wants */
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__IO uint32_t PIN; /**< to */
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__IO uint32_t SET; /**< know */
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__IO uint32_t CLR; /**< everything */
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} FIO_PORT_t;
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#define FIO_PORTS ((FIO_PORT_t*)FIO_BASE_ADDR)
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#define PINSEL ((__IO uint32_t *)(PINSEL_BASE_ADDR))
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#define PINMODE ((__IO uint32_t *)(PINSEL_BASE_ADDR + 0x40))
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int gpio_init_mux(unsigned pin, unsigned mux);
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void gpio_init_states(void);
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#define GPIO(port, pin) (port*32 + pin)
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#define HAVE_GPIO_PP_T
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typedef enum {
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GPIO_PULLUP = 0, /**< enable internal pull-up resistor */
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GPIO_NOPULL = 2, /**< do not use internal pull resistors */
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GPIO_PULLDOWN = 3 /**< enable internal pull-down resistor */
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} gpio_pp_t;
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|
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_FALLING = 1, /**< emit interrupt on falling flank */
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GPIO_RISING = 2, /**< emit interrupt on rising flank */
|
||||
GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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||||
} gpio_flank_t;
|
||||
|
||||
/**
|
||||
* @brief declare needed generic SPI functions
|
||||
* @{
|
||||
*/
|
||||
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
|
||||
#define PERIPH_SPI_NEEDS_TRANSFER_REG
|
||||
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
|
||||
/* @} */
|
||||
|
||||
/* @} */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CPU_H_ */
|
||||
/** @} */
|
||||
@ -1,68 +0,0 @@
|
||||
/*
|
||||
* syscalls.c - MCU dependent syscall implementation for LPCXXXX
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <sys/unistd.h>
|
||||
#include <stdio.h>
|
||||
#include "irq.h"
|
||||
|
||||
/**
|
||||
* @name Heaps (defined in linker script)
|
||||
* @{
|
||||
*/
|
||||
#define NUM_HEAPS 3
|
||||
|
||||
extern uintptr_t __heap1_start; ///< start of heap memory space
|
||||
extern uintptr_t __heap1_max; ///< maximum for end of heap memory space
|
||||
extern uintptr_t __heap2_start; ///< start of heap memory space
|
||||
extern uintptr_t __heap2_max; ///< maximum for end of heap memory space
|
||||
extern uintptr_t __heap3_start; ///< start of heap memory space
|
||||
extern uintptr_t __heap3_max; ///< maximum for end of heap memory space
|
||||
|
||||
/// current position in heap
|
||||
static caddr_t heap[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start}; // add heap3 before heap2 cause Heap3 address is lower then addr of heap2
|
||||
/// maximum position in heap
|
||||
static const caddr_t heap_max[NUM_HEAPS] = {(caddr_t)&__heap1_max,(caddr_t)&__heap3_max,(caddr_t)&__heap2_max};
|
||||
// start position in heap
|
||||
static const caddr_t heap_start[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start};
|
||||
|
||||
/** @} */
|
||||
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
void heap_stats(void)
|
||||
{
|
||||
for(int i = 0; i < NUM_HEAPS; i++)
|
||||
printf("# heap %i: %p -- %p -> %p (%li of %li free)\n", i, heap_start[i], heap[i], heap_max[i],
|
||||
(uint32_t)heap_max[i] - (uint32_t)heap[i], (uint32_t)heap_max[i] - (uint32_t)heap_start[i]);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
caddr_t _sbrk_r(struct _reent *r, ptrdiff_t incr)
|
||||
{
|
||||
uint32_t cpsr = disableIRQ();
|
||||
|
||||
/* check all heaps for a chunk of the requested size */
|
||||
for (volatile uint8_t iUsedHeap = 0; iUsedHeap < NUM_HEAPS; iUsedHeap++ ) {
|
||||
caddr_t new_heap = heap[iUsedHeap] + incr;
|
||||
|
||||
if( new_heap <= heap_max[iUsedHeap] ) {
|
||||
caddr_t prev_heap = heap[iUsedHeap];
|
||||
heap[iUsedHeap] = new_heap;
|
||||
|
||||
r->_errno = 0;
|
||||
restoreIRQ(cpsr);
|
||||
return prev_heap;
|
||||
}
|
||||
}
|
||||
restoreIRQ(cpsr);
|
||||
|
||||
r->_errno = ENOMEM;
|
||||
return NULL;
|
||||
}
|
||||
@ -0,0 +1,311 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup lpc2387
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CPU specific low-level GPIO driver implementation for the LPC2387
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "irq.h"
|
||||
#include "periph/gpio.h"
|
||||
#include "bitfield.h"
|
||||
|
||||
#define ENABLE_DEBUG (0)
|
||||
#include "debug.h"
|
||||
|
||||
#define GPIO_NUM_ISR (16)
|
||||
|
||||
static BITFIELD(_gpio_config_bitfield, GPIO_NUM_ISR);
|
||||
|
||||
typedef struct {
|
||||
gpio_cb_t cb; /**< callback called from GPIO interrupt */
|
||||
void *arg; /**< argument passed to the callback */
|
||||
} gpio_state_t;
|
||||
|
||||
static gpio_state_t _gpio_states[GPIO_NUM_ISR];
|
||||
static BITFIELD(_gpio_rising, GPIO_NUM_ISR);
|
||||
static BITFIELD(_gpio_falling, GPIO_NUM_ISR);
|
||||
static uint8_t _gpio_isr_map[64]; /* only ports 0+2 can have ISRs */
|
||||
|
||||
static void _gpio_configure(gpio_t pin, unsigned rising, unsigned falling);
|
||||
|
||||
void gpio_init_ports(void) {
|
||||
SCS |= 0x1; /* set GPIO ports 0 and 1 to FIO mode (3.7.2) */
|
||||
memset(&_gpio_isr_map[0], 0xff, 64);
|
||||
}
|
||||
|
||||
static int _isr_map_entry(gpio_t pin) {
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
|
||||
/* lpc2387 can only interrupt in pins of port 0 and 2 */
|
||||
if (port && port != 2) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (port) {
|
||||
_pin += 32;
|
||||
}
|
||||
|
||||
return _pin;
|
||||
}
|
||||
|
||||
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
|
||||
{
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
|
||||
FIO_PORT_t *_port = &FIO_PORTS[port];
|
||||
|
||||
/* set mask */
|
||||
_port->MASK = ~(0x1<<_pin);
|
||||
|
||||
/* set direction */
|
||||
_port->DIR = ~0;
|
||||
|
||||
/* set pullup/pulldown **/
|
||||
PINMODE[pin>>4] |= pullup << (_pin*2);
|
||||
|
||||
gpio_init_mux(pin, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gpio_init_mux(unsigned pin, unsigned mux) {
|
||||
unsigned _pin = pin & 31;
|
||||
PINSEL[pin>>4] &= ~(0x1 << (_pin*2));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
|
||||
gpio_cb_t cb, void *arg)
|
||||
{
|
||||
DEBUG("gpio_init_int(): pin %u\n", pin);
|
||||
int isr_map_entry;
|
||||
|
||||
/* check if interrupt is possible for this pin */
|
||||
if ((isr_map_entry = _isr_map_entry(pin)) == -1) {
|
||||
DEBUG("gpio_init_int(): pin %u cannot be used to generate interrupts.\n", pin);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* find free isr state entry */
|
||||
int _state_index = _gpio_isr_map[isr_map_entry];
|
||||
|
||||
if (_state_index == 0xff) {
|
||||
_state_index = bf_get_unset(_gpio_config_bitfield, GPIO_NUM_ISR);
|
||||
_gpio_isr_map[isr_map_entry] = _state_index;
|
||||
DEBUG("gpio_init_int(): pin has state_index=%i isr_map_entry=%i\n", _state_index, isr_map_entry);
|
||||
}
|
||||
|
||||
if (_state_index == 0xff) {
|
||||
#if DEVELHELP
|
||||
puts("lpc2387: gpio: warning: no free gpio callback state!");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* store callback */
|
||||
_gpio_states[_state_index].cb = cb;
|
||||
_gpio_states[_state_index].arg = arg;
|
||||
|
||||
extern void GPIO_IRQHandler(void);
|
||||
gpio_init(pin, GPIO_DIR_IN, pullup);
|
||||
|
||||
if (flank & GPIO_FALLING) {
|
||||
bf_set(_gpio_falling, _state_index);
|
||||
}
|
||||
else {
|
||||
bf_unset(_gpio_falling, _state_index);
|
||||
}
|
||||
|
||||
if (flank & GPIO_RISING) {
|
||||
bf_set(_gpio_rising, _state_index);
|
||||
}
|
||||
else {
|
||||
bf_unset(_gpio_rising, _state_index);
|
||||
}
|
||||
|
||||
_gpio_configure(pin, flank & GPIO_RISING, flank & GPIO_FALLING);
|
||||
|
||||
/* activate irq */
|
||||
INTWAKE |= GPIO0WAKE | GPIO2WAKE; /* allow GPIO to wake up from power down */
|
||||
install_irq(GPIO_INT, &GPIO_IRQHandler, IRQP_GPIO); /* install irq handler */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void _gpio_configure(gpio_t pin, unsigned rising, unsigned falling)
|
||||
{
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
|
||||
/* set irq settings */
|
||||
volatile unsigned long *en_f;
|
||||
volatile unsigned long *en_r;
|
||||
volatile unsigned long *en_clr;
|
||||
|
||||
if (!port) {
|
||||
en_f = &IO0_INT_EN_F;
|
||||
en_r = &IO0_INT_EN_R;
|
||||
en_clr = &IO0_INT_CLR;
|
||||
}
|
||||
else {
|
||||
en_f = &IO2_INT_EN_F;
|
||||
en_r = &IO2_INT_EN_R;
|
||||
en_clr = &IO2_INT_CLR;
|
||||
}
|
||||
|
||||
/* configure irq */
|
||||
unsigned int bit = 0x1 << _pin;
|
||||
|
||||
unsigned state = disableIRQ();
|
||||
|
||||
*en_clr |= bit; /* clear interrupt */
|
||||
|
||||
if (falling) {
|
||||
*en_f |= bit; /* enable falling edge */
|
||||
}
|
||||
else {
|
||||
*en_f &= ~bit; /* disable falling edge */
|
||||
}
|
||||
|
||||
if (rising) {
|
||||
*en_r |= bit; /* enable rising edge */
|
||||
}
|
||||
else {
|
||||
*en_r &= ~bit; /* disable rising edge */
|
||||
}
|
||||
|
||||
restoreIRQ(state);
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_t pin)
|
||||
{
|
||||
int isr_map_entry =_isr_map_entry(pin);
|
||||
int _state_index = _gpio_isr_map[isr_map_entry];
|
||||
|
||||
if (_state_index == 0xff) {
|
||||
DEBUG("gpio_irq_enable(): trying to enable unconfigured pin.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
_gpio_configure(pin,
|
||||
bf_isset(_gpio_rising, _state_index),
|
||||
bf_isset(_gpio_falling, _state_index));
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_t dev)
|
||||
{
|
||||
_gpio_configure(dev, 0, 0);
|
||||
}
|
||||
|
||||
int gpio_read(gpio_t pin)
|
||||
{
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
FIO_PORT_t *_port = &FIO_PORTS[port];
|
||||
_port->MASK = ~(1<<_pin);
|
||||
return _port->PIN != 0;
|
||||
}
|
||||
|
||||
void gpio_set(gpio_t pin)
|
||||
{
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
FIO_PORT_t *_port = &FIO_PORTS[port];
|
||||
_port->MASK = ~(1<<_pin);
|
||||
_port->SET = ~0;
|
||||
}
|
||||
|
||||
void gpio_clear(gpio_t pin)
|
||||
{
|
||||
unsigned _pin = pin & 31;
|
||||
unsigned port = pin >> 5;
|
||||
FIO_PORT_t *_port = &FIO_PORTS[port];
|
||||
_port->MASK = ~(1<<_pin);
|
||||
_port->CLR = ~0;
|
||||
}
|
||||
|
||||
void gpio_toggle(gpio_t dev)
|
||||
{
|
||||
if (gpio_read(dev)) {
|
||||
gpio_clear(dev);
|
||||
}
|
||||
else {
|
||||
gpio_set(dev);
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_write(gpio_t dev, int value)
|
||||
{
|
||||
if (value) {
|
||||
gpio_set(dev);
|
||||
}
|
||||
else {
|
||||
gpio_clear(dev);
|
||||
}
|
||||
}
|
||||
|
||||
static void test_irq(int port, unsigned long f_mask, unsigned long r_mask)
|
||||
{
|
||||
/* Test each bit of rising and falling masks, if set trigger interrupt
|
||||
* on corresponding device */
|
||||
unsigned bit = 0x1;
|
||||
int n = 0;
|
||||
while (bit) {
|
||||
if ((r_mask & bit) | (f_mask & bit)) {
|
||||
int _state_index = _gpio_isr_map[n + (port<<1)];
|
||||
if (_state_index != 0xff) {
|
||||
_gpio_states[_state_index].cb(_gpio_states[_state_index].arg);
|
||||
}
|
||||
}
|
||||
|
||||
bit <<= 1;
|
||||
n++;
|
||||
}
|
||||
}
|
||||
|
||||
void GPIO_IRQHandler(void) __attribute__((interrupt("IRQ")));
|
||||
|
||||
void GPIO_IRQHandler(void)
|
||||
{
|
||||
if (IO_INT_STAT & BIT0) { /* interrupt(s) on PORT0 pending */
|
||||
unsigned long int_stat_f = IO0_INT_STAT_F; /* save content */
|
||||
unsigned long int_stat_r = IO0_INT_STAT_R; /* save content */
|
||||
|
||||
IO0_INT_CLR = int_stat_f; /* clear flags of fallen pins */
|
||||
IO0_INT_CLR = int_stat_r; /* clear flags of risen pins */
|
||||
|
||||
test_irq(0, int_stat_f, int_stat_r);
|
||||
}
|
||||
|
||||
if (IO_INT_STAT & BIT2) { /* interrupt(s) on PORT2 pending */
|
||||
unsigned long int_stat_f = IO2_INT_STAT_F; /* save content */
|
||||
unsigned long int_stat_r = IO2_INT_STAT_R; /* save content */
|
||||
|
||||
IO2_INT_CLR = int_stat_f; /* clear flags of fallen pins */
|
||||
IO2_INT_CLR = int_stat_r; /* clear flags of risen pins */
|
||||
|
||||
test_irq(2, int_stat_f, int_stat_r);
|
||||
}
|
||||
|
||||
VICVectAddr = 0; /* Acknowledge Interrupt */
|
||||
}
|
||||
@ -0,0 +1,197 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lpc2387
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Low-level SPI driver implementation
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "mutex.h"
|
||||
#include "periph/gpio.h"
|
||||
#include "periph/spi.h"
|
||||
#include "periph_conf.h"
|
||||
#include "board.h"
|
||||
#define ENABLE_DEBUG (0)
|
||||
#include "debug.h"
|
||||
|
||||
#if SPI_0_EN
|
||||
|
||||
#define SPI_TX_EMPTY (SSP0SR & SSPSR_TFE)
|
||||
#define SPI_BUSY (SSP0SR & SSPSR_BSY)
|
||||
#define SPI_RX_AVAIL (SSP0SR & SSPSR_RNE)
|
||||
|
||||
/**
|
||||
* @brief Array holding one pre-initialized mutex for each SPI device
|
||||
*/
|
||||
static mutex_t locks[] = {
|
||||
#if SPI_0_EN
|
||||
[SPI_0] = MUTEX_INIT,
|
||||
#endif
|
||||
#if SPI_1_EN
|
||||
[SPI_1] = MUTEX_INIT,
|
||||
#endif
|
||||
#if SPI_2_EN
|
||||
[SPI_2] = MUTEX_INIT
|
||||
#endif
|
||||
};
|
||||
|
||||
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
|
||||
{
|
||||
if (dev) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
uint32_t f_baud = 0;
|
||||
switch(speed)
|
||||
{
|
||||
case SPI_SPEED_100KHZ:
|
||||
f_baud = 100;
|
||||
break;
|
||||
case SPI_SPEED_400KHZ:
|
||||
f_baud = 400;
|
||||
break;
|
||||
case SPI_SPEED_1MHZ:
|
||||
f_baud = 1000;
|
||||
break;
|
||||
case SPI_SPEED_5MHZ:
|
||||
f_baud = 5000;
|
||||
break;
|
||||
case SPI_SPEED_10MHZ:
|
||||
f_baud = 10000;
|
||||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* TODO */
|
||||
switch(conf)
|
||||
{
|
||||
case SPI_CONF_FIRST_RISING:
|
||||
/**< first data bit is transacted on the first rising SCK edge */
|
||||
cpha = 0;
|
||||
cpol = 0;
|
||||
break;
|
||||
case SPI_CONF_SECOND_RISING:
|
||||
/**< first data bit is transacted on the second rising SCK edge */
|
||||
cpha = 1;
|
||||
cpol = 0;
|
||||
break;
|
||||
case SPI_CONF_FIRST_FALLING:
|
||||
/**< first data bit is transacted on the first falling SCK edge */
|
||||
cpha = 0;
|
||||
cpol = 1;
|
||||
break;
|
||||
case SPI_CONF_SECOND_FALLING:
|
||||
/**< first data bit is transacted on the second falling SCK edge */
|
||||
cpha = 1;
|
||||
cpol = 1;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Power*/
|
||||
PCONP |= PCSSP0; /* Enable power for SSP0 (default is on)*/
|
||||
|
||||
/* PIN Setup*/
|
||||
PINSEL3 |= BIT8 + BIT9; /* Set CLK function to SPI*/
|
||||
PINSEL3 |= BIT14 + BIT15; /* Set MISO function to SPI*/
|
||||
PINSEL3 |= BIT16 + BIT17; /* Set MOSI function to SPI*/
|
||||
|
||||
/* Interface Setup*/
|
||||
SSP0CR0 = 7;
|
||||
|
||||
/* Clock Setup*/
|
||||
uint32_t pclksel;
|
||||
uint32_t cpsr;
|
||||
lpc2387_pclk_scale(F_CPU / 1000, f_baud, &pclksel, &cpsr);
|
||||
PCLKSEL1 &= ~(BIT10 | BIT11); /* CCLK to PCLK divider*/
|
||||
PCLKSEL1 |= pclksel << 10;
|
||||
SSP0CPSR = cpsr;
|
||||
|
||||
/* Enable*/
|
||||
SSP0CR1 |= BIT1; /* SSP-Enable*/
|
||||
int dummy;
|
||||
|
||||
/* Clear RxFIFO:*/
|
||||
while (SPI_RX_AVAIL) { /* while RNE (Receive FIFO Not Empty)...*/
|
||||
dummy = SSP0DR; /* read data*/
|
||||
}
|
||||
|
||||
/* to suppress unused-but-set-variable */
|
||||
(void) dummy;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
|
||||
{
|
||||
(void)dev;
|
||||
(void)conf;
|
||||
(void)cb;
|
||||
printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
|
||||
/* TODO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_transmission_begin(spi_t dev, char reset_val)
|
||||
{
|
||||
(void)dev;
|
||||
(void)reset_val;
|
||||
printf("%s:%s(): stub\n", RIOT_FILE_RELATIVE, __func__);
|
||||
/* TODO*/
|
||||
}
|
||||
|
||||
int spi_acquire(spi_t dev)
|
||||
{
|
||||
if (dev >= SPI_NUMOF) {
|
||||
return -1;
|
||||
}
|
||||
mutex_lock(&locks[dev]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_release(spi_t dev)
|
||||
{
|
||||
if (dev >= SPI_NUMOF) {
|
||||
return -1;
|
||||
}
|
||||
mutex_unlock(&locks[dev]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_transfer_byte(spi_t dev, char out, char *in)
|
||||
{
|
||||
while (!SPI_TX_EMPTY);
|
||||
SSP0DR = out;
|
||||
while (SPI_BUSY);
|
||||
while (!SPI_RX_AVAIL);
|
||||
|
||||
char tmp = (char)SSP0DR;
|
||||
|
||||
if (in != NULL) {
|
||||
*in = tmp;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void spi_poweron(spi_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
void spi_poweroff(spi_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* SPI_0_EN */
|
||||
@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2008-2015, Freie Universitaet Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_lpc2387
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Peripheral UART driver implementation
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
* @author Heiko Will <hwill@inf.fu-berlin.de>
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||