boards/nucleo-f103: add support for nucleo-f103
Victor Arino
7 years ago
parent
82796f9aea
commit
3a8a932b27
@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m3_1
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@ -0,0 +1,16 @@
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## the cpu to build for
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export CPU = stm32f1
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export CPU_MODEL = stm32f103rb
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#define the default port depending on the host OS
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(shell ls -1 /dev/tty.usbmodem* | head -n 1)
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# setup serial terminal
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include $(RIOTBOARD)/Makefile.include.serial
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# this board uses openocd
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include $(RIOTBOARD)/Makefile.include.openocd
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# include cortex defaults
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include $(RIOTBOARD)/Makefile.include.cortexm_common
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@ -0,0 +1,52 @@
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/*
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* Copyright (C) 2015 TriaGnoSys GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f103
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo-f103 board
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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*
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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#include "periph/gpio.h"
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static void leds_init(void);
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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/* initialize the boards LEDs */
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leds_init();
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/* pin remapping: in order to use the MCU peripherals with the Arduino
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* compatible connectors. Some peripherals need to be remapped here. */
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RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
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AFIO->MAPR |= AFIO_MAPR_I2C1_REMAP;
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}
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/**
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* @brief Initialize the boards on-board LEDs
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*
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* The green LED is connected to pin PA5
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*/
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static void leds_init(void)
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{
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
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GPIOA->CR[0] &= ~(0x0f << 20);
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GPIOA->CR[0] |= (0x03 << 20);
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GPIOA->BRR = (1 << 5);
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}
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@ -0,0 +1 @@
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source [find board/st_nucleo_f1.cfg]
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@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2015 TriaGnoSys GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-f103 Nucleo-F103
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* @ingroup boards
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* @brief Board specific files for the nucleo-f103 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo-f103 board
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Define the nominal CPU core clock in this board
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*/
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#define F_CPU CLOCK_CORECLOCK
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/**
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* @name Define the UART to be used as stdio and its baudrate
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* @{
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*/
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#define STDIO UART_1
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#define STDIO_BAUDRATE (115200U)
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#define STDIO_RX_BUFSIZE (64U)
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/** @} */
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/**
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* @name LED pin definitions
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* @{
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*/
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#define LED_GREEN_GPIO GPIO_PIN(PORT_A, 5)
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/** @} */
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LED_RED_ON
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#define LED_RED_OFF
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#define LED_RED_TOGGLE
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#define LED_GREEN_ON (GPIOA->BSRR = (1 << 5))
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#define LED_GREEN_OFF (GPIOA->BRR = (1 << 5))
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#define LED_GREEN_TOGGLE (GPIOA->ODR ^= (1 << 5))
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#define LED_ORANGE_ON
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#define LED_ORANGE_OFF
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#define LED_ORANGE_TOGGLE
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/** @} */
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/**
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* @name Buttons
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* @{
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*/
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#define BUTTON_USER_GPIO GPIO_PIN(PORT_C, 13)
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/** @} */
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER TIMER_0
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#define XTIMER_CHAN 0
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#define XTIMER_SHIFT 0
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#define XTIMER_MASK 0 /* llt 32-bit since combined */
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#define XTIMER_BACKOFF 5
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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/** @} */
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@ -0,0 +1,196 @@
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/*
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* Copyright (C) 2015 TriaGnoSys GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f103
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-f103 board
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE /* not divided */
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
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/* AHB, APB1, APB2 dividers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36 MHz (!) */
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/* Flash latency */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 0
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_PRESCALER (CLOCK_CORECLOCK / 1000000U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/* Timer 1 configuration */
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#define TIMER_1_DEV_0 TIM4
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#define TIMER_1_DEV_1 TIM5
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#define TIMER_1_PRESCALER (36000U)
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#define TIMER_1_MAX_VALUE (0xffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
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#define TIMER_1_ISR_0 isr_tim4
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#define TIMER_1_ISR_1 isr_tim5
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#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
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#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
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#define TIMER_1_IRQ_PRIO 1
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#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (3U)
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#define UART_0_EN 0
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#define UART_1_EN 1
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#define UART_2_EN 0
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART1
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#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_0_IRQ USART1_IRQn
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#define UART_0_ISR isr_usart1
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#define UART_0_BUS_FREQ CLOCK_CORECLOCK
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/* UART 0 pin configuration */
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#define UART_0_RX_PIN GPIO_PIN(PORT_A, 10)
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#define UART_0_TX_PIN GPIO_PIN(PORT_A, 9)
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/* UART 1 device configuration */
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#define UART_1_DEV USART2
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#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_1_IRQ USART2_IRQn
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#define UART_1_ISR isr_usart2
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#define UART_1_BUS_FREQ CLOCK_CORECLOCK / 2
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/* UART 1 pin configuration */
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#define UART_1_RX_PIN GPIO_PIN(PORT_A, 3)
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#define UART_1_TX_PIN GPIO_PIN(PORT_A, 2)
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/* UART 2 device configuration */
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#define UART_2_DEV USART3
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#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_2_IRQ USART3_IRQn
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#define UART_2_ISR isr_usart3
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#define UART_2_BUS_FREQ CLOCK_CORECLOCK / 2
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/* UART 2 pin configuration */
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#define UART_2_RX_PIN GPIO_PIN(PORT_B, 11)
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#define UART_2_TX_PIN GPIO_PIN(PORT_B, 10)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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#define I2C_1_EN 0
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
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#define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C2
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#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
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#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define I2C_1_EVT_IRQ I2C2_EV_IRQn
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_IRQ I2C2_ER_IRQn
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#define I2C_1_ERR_ISR isr_i2c2_er
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/* I2C 1 pin configuration */
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#define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
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#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 0
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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#define SPI_0_BUS_DIV 1
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/* SPI 0 pin configuration */
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#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5)
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#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6)
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#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7)
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/* SPI 1 device config */
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#define SPI_1_DEV SPI2
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#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
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#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
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#define SPI_1_IRQ SPI2_IRQn
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#define SPI_1_IRQ_HANDLER isr_spi2
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#define SPI_1_BUS_DIV 1
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/* SPI 1 pin configuration */
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#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13)
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#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14)
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#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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