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@ -31,7 +31,7 @@ extern "C" {
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_Div2
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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