Merge branch 'mc1322x' of github.com:RIOT-OS/RIOT into mc1322x
Thomas Eichinger
11 years ago
commit
3dba62afa6
@ -0,0 +1,21 @@
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### Minimal setup
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ifeq ($(CPU),lpc2387)
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export USEMODULE += arm_common lpc_common
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export UNDEF += $(BINDIR)syscalls.o
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export INCLUDES += -I$(RIOTCPU)/arm_common/include
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export INCLUDES += -I$(RIOTCPU)/lpc_common/include
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endif
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ifeq ($(CPU),lpc214x)
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export USEMODULE += arm_common lpc_common
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export UNDEF += $(BINDIR)syscalls.o
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export INCLUDES += -I$(RIOTCPU)/arm_common/include
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export INCLUDES += -I$(RIOTCPU)/lpc_common/include
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endif
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ifeq ($(CPU),mc1322x)
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export USEMODULE += arm_common
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export UNDEF += $(BINDIR)syscalls.o
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export INCLUDES += -I$(RIOTBASE)/cpu/arm_common/include
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endif
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ifeq ($(CPU),native)
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export INCLUDES += -I$(RIOTBASE)/cpu/native/include
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endif
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@ -0,0 +1,4 @@
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MODULE =lpc_common
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include $(RIOTBASE)/Makefile.base
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@ -1,13 +1,13 @@
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/* iap driver
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*
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* based on iap driver for LPC2148 Controller made by Andreas Weschenfelder, 2008
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* see:
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*
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*/
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#include <irq.h>
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#include <flashrom.h>
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#include <iap.h>
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/* TODO: replace by a lpc generic header */
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#include <lpc2387.h>
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//#define ENABLE_DEBUG
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@ -0,0 +1,20 @@
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/*
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* lpc_cpu.c - LPC architecture common support functions
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*
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*/
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__attribute__((naked,noreturn)) void arm_reset(void)
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{
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dINT();
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WDTC = 0x00FFF;
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WDMOD = 0x03;
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WDFEED= 0xAA;
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WDFEED= 0x55;
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while(1);
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}
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@ -0,0 +1,75 @@
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/*
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* syscalls.c - MCU dependent syscall implementation for LPCXXXX
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*
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*/
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#include <errno.h>
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/**
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* @name Heaps (defined in linker script)
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* @{
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*/
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#define NUM_HEAPS 3
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extern uintptr_t __heap1_start; ///< start of heap memory space
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extern uintptr_t __heap1_max; ///< maximum for end of heap memory space
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extern uintptr_t __heap2_start; ///< start of heap memory space
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extern uintptr_t __heap2_max; ///< maximum for end of heap memory space
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extern uintptr_t __heap3_start; ///< start of heap memory space
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extern uintptr_t __heap3_max; ///< maximum for end of heap memory space
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/// current position in heap
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static caddr_t heap[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start}; // add heap3 before heap2 cause Heap3 address is lower then addr of heap2
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/// maximum position in heap
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static const caddr_t heap_max[NUM_HEAPS] = {(caddr_t)&__heap1_max,(caddr_t)&__heap3_max,(caddr_t)&__heap2_max};
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// start position in heap
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static const caddr_t heap_start[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start};
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/** @} */
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/*-----------------------------------------------------------------------------------*/
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void heap_stats(void)
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{
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for(int i = 0; i < NUM_HEAPS; i++)
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printf("# heap %i: %p -- %p -> %p (%li of %li free)\n", i, heap_start[i], heap[i], heap_max[i],
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(uint32_t)heap_max[i] - (uint32_t)heap[i], (uint32_t)heap_max[i] - (uint32_t)heap_start[i]);
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}
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/*-----------------------------------------------------------------------------------*/
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caddr_t _sbrk_r(struct _reent *r, size_t incr)
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{
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uint32_t cpsr = disableIRQ();
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/* check all heaps for a chunk of the requested size */
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for (volatile uint8_t iUsedHeap = 0; iUsedHeap < NUM_HEAPS; iUsedHeap++ ) {
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caddr_t new_heap = heap[iUsedHeap] + incr;
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#ifdef MODULE_TRACELOG
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trace_pointer(TRACELOG_EV_MEMORY, heap[iUsedHeap]);
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#endif
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if( new_heap <= heap_max[iUsedHeap] ) {
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caddr_t prev_heap = heap[iUsedHeap];
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#ifdef MODULE_TRACELOG
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trace_pointer(TRACELOG_EV_MEMORY, new_heap);
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#endif
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heap[iUsedHeap] = new_heap;
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r->_errno = 0;
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restoreIRQ(cpsr);
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return prev_heap;
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}
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}
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restoreIRQ(cpsr);
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#ifdef MODULE_TRACELOG
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trace_string(TRACELOG_EV_MEMORY, "heap!"); // heap full
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#endif
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r->_errno = ENOMEM;
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return NULL;
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}
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@ -0,0 +1,12 @@
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MODULE =cpu
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DIRS =
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all: $(BINDIR)$(MODULE).a
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@for i in $(DIRS) ; do $(MAKE) -C $$i ; done ;
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include $(RIOTBASE)/Makefile.base
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clean::
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@for i in $(DIRS) ; do $(MAKE) -C $$i clean ; done ;
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@ -0,0 +1,19 @@
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/*
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* cpu.c - MC1322X architecture common support functions
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*
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*/
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#include "mc1322x.h"
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__attribute__((naked,noreturn)) void arm_reset(void)
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{
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dINT();
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CRM->SW_RST = SW_RST_VAL;
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while(1);
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}
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@ -0,0 +1,51 @@
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/*
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* hwtimer_cpu.c - architecture dependent hardware timer functionality
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#include <stdint.h>
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#include "mc1322x.h"
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/* TODO: do scaling voodoo */
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#define COUNT_MODE 1 /* use rising edge of primary source */
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#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
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#define SEC_SRC 0 /* don't need this */
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#define ONCE 0 /* keep counting */
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#define LEN 0 /* continue counting */
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#define DIR 0 /* count up */
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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/* High level interrupt handler */
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static void (*int_handler)(int);
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
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int_handler = handler;
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/* Reset the timer */
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TMR0->ENBL = 0;
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/* Clear status */
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TMR0->SCTRL = 0;
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/* disable interrupt */
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TMR0->CSCTRL =0x0000;
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/* Reload/initialize to zero */
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TMR0->LOAD = 0;
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/* disable comparison */
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TMR0->COMP1 = 0;
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TMR0->CMPLD1 = 0;
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/* set counter to zero */
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TMR0->CNTR = 0;
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/* TODO: do scaling voodoo */
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(void) fcpu;
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/* TODO: use struct */
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TMR0->CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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TMR0->ENBL = 0xf; /* enable all the timers --- why not? */
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}
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@ -0,0 +1,61 @@
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/*
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* cpu.h - mc1322x specific definitions
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT
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*/
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#ifndef CPUCONF_H_
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#define CPUCONF_H_
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/**
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* @ingroup conf
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* @ingroup mc1322x
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*
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* @{
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*/
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/**
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* @file
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* @brief MC1322X CPUconfiguration
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*
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* @author Oleg Hahm
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*/
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/**
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* @name Stdlib configuration
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* @{
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*/
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#define __FOPEN_MAX__ 4
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#define __FILENAME_MAX__ 12
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/** @} */
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/**
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* @name Kernel configuration
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* @{
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*/
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#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
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#define KERNEL_CONF_STACKSIZE_DEFAULT 4500
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#endif
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#define KERNEL_CONF_STACKSIZE_IDLE 500
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/** @} */
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/**
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* @name Compiler specifics
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* @{
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*/
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#define CC_CONF_INLINE inline
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#define CC_CONF_USED __attribute__((used))
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#define CC_CONF_NONNULL(...) __attribute__((nonnull(__VA_ARGS__)))
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#define CC_CONF_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
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/** @} */
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#define TRANSCEIVER_BUFFER_SIZE (10)
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#define RX_BUF_SIZE (10)
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/** @} */
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#endif /* CPUCONF_H_ */
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@ -0,0 +1,18 @@
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/*
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* cpu.h - mc1322x specific definitions
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*/
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#ifndef CPU_H
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#define CPU_H
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#include <stdint.h>
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#include "arm_cpu.h"
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#include "mc1322x.h"
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extern uintptr_t __stack_start; ///< end of user stack memory space
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#endif /* CPU_H */
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@ -0,0 +1,386 @@
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/*
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* mc1322x.h - mc1322x specific definitions
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||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
|
||||
* This source code is licensed under the GNU General Public License,
|
||||
* Version 3. See the file LICENSE for more details.
|
||||
*
|
||||
* This file is part of RIOT.
|
||||
*/
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|
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#ifndef MC1322X_H
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#define MC1322X_H
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#include <stdint.h>
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/*-----------------------------------------------------------------*/
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/* System Management */
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#define SW_RST_VAL (0x87651234)
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#define CRM_BASE (0x80003000)
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/* Structure-based CRM access */
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struct CRM_struct {
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union {
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uint32_t SYS_CNTL;
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struct CRM_SYS_CNTL {
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uint32_t PWR_SOURCE:2;
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uint32_t PADS_1P8V_SEL:1;
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uint32_t :1;
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uint32_t JTAG_SECU_OFF:1;
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uint32_t XTAL32_EXISTS:1;
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uint32_t :2;
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uint32_t XTAL_CLKDIV:6;
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uint32_t :18;
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} SYS_CNTLbits;
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};
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union {
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uint32_t WU_CNTL;
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struct CRM_WU_CNTL {
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uint32_t TIMER_WU_EN:1;
|
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uint32_t RTC_WU_EN:1;
|
||||
uint32_t HOST_WAKE:1;
|
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uint32_t AUTO_ADC:1;
|
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uint32_t EXT_WU_EN:4;
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uint32_t EXT_WU_EDGE:4;
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uint32_t EXT_WU_POL:4;
|
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uint32_t TIMER_WU_IEN:1;
|
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uint32_t RTC_WU_IEN:1;
|
||||
uint32_t :2;
|
||||
uint32_t EXT_WU_IEN:4;
|
||||
uint32_t :4;
|
||||
uint32_t EXT_OUT_POL:4;
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} WU_CNTLbits;
|
||||
};
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||||
union {
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||||
uint32_t SLEEP_CNTL;
|
||||
struct CRM_SLEEP_CNTL {
|
||||
uint32_t HIB:1;
|
||||
uint32_t DOZE:1;
|
||||
uint32_t :2;
|
||||
uint32_t RAM_RET:2;
|
||||
uint32_t MCU_RET:1;
|
||||
uint32_t DIG_PAD_EN:1;
|
||||
uint32_t :24;
|
||||
} SLEEP_CNTLbits;
|
||||
};
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union {
|
||||
uint32_t BS_CNTL;
|
||||
struct CRM_BS_CNTL {
|
||||
uint32_t BS_EN:1;
|
||||
uint32_t WAIT4IRQ:1;
|
||||
uint32_t BS_MAN_EN:1;
|
||||
uint32_t :2;
|
||||
uint32_t ARM_OFF_TIME:6;
|
||||
uint32_t :18;
|
||||
} BS_CNTLbits;
|
||||
};
|
||||
union {
|
||||
uint32_t COP_CNTL;
|
||||
struct CRM_COP_CNTL {
|
||||
uint32_t COP_EN:1;
|
||||
uint32_t COP_OUT:1;
|
||||
uint32_t COP_WP:1;
|
||||
uint32_t :5;
|
||||
uint32_t COP_TIMEOUT:7;
|
||||
uint32_t :1;
|
||||
uint32_t COP_COUNT:7;
|
||||
uint32_t :9;
|
||||
} COP_CNTLbits;
|
||||
};
|
||||
uint32_t COP_SERVICE;
|
||||
union {
|
||||
uint32_t STATUS;
|
||||
struct CRM_STATUS {
|
||||
uint32_t SLEEP_SYNC:1;
|
||||
uint32_t HIB_WU_EVT:1;
|
||||
uint32_t DOZE_WU_EVT:1;
|
||||
uint32_t RTC_WU_EVT:1;
|
||||
uint32_t EXT_WU_EVT:4;
|
||||
uint32_t :1;
|
||||
uint32_t CAL_DONE:1;
|
||||
uint32_t COP_EVT:1;
|
||||
uint32_t :6;
|
||||
uint32_t VREG_BUCK_RDY:1;
|
||||
uint32_t VREG_1P8V_RDY:1;
|
||||
uint32_t VREG_1P5V_RDY:1;
|
||||
uint32_t :12;
|
||||
} STATUSbits;
|
||||
};
|
||||
union {
|
||||
uint32_t MOD_STATUS;
|
||||
struct CRM_MOD_STATUS {
|
||||
uint32_t ARM_EN:1;
|
||||
uint32_t MACA_EN:1;
|
||||
uint32_t ASM_EN:1;
|
||||
uint32_t SPI_EN:1;
|
||||
uint32_t GPIO_EN:1;
|
||||
uint32_t UART1_EN:1;
|
||||
uint32_t UART2_EN:1;
|
||||
uint32_t TMR_EN:1;
|
||||
uint32_t RIF_EN:1;
|
||||
uint32_t I2C_EN:1;
|
||||
uint32_t SSI_EN:1;
|
||||
uint32_t SPIF_EN:1;
|
||||
uint32_t ADC_EN:1;
|
||||
uint32_t :1;
|
||||
uint32_t JTA_EN:1;
|
||||
uint32_t NEX_EN:1;
|
||||
uint32_t :1;
|
||||
uint32_t AIM_EN:1;
|
||||
uint32_t :14;
|
||||
} MOD_STATUSbits;
|
||||
};
|
||||
uint32_t WU_COUNT;
|
||||
uint32_t WU_TIMEOUT;
|
||||
uint32_t RTC_COUNT;
|
||||
uint32_t RTC_TIMEOUT;
|
||||
uint32_t reserved1;
|
||||
union {
|
||||
uint32_t CAL_CNTL;
|
||||
struct CRM_CAL_CNTL {
|
||||
uint32_t CAL_TIMEOUT:16;
|
||||
uint32_t CAL_EN:1;
|
||||
uint32_t CAL_IEN:1;
|
||||
uint32_t :14;
|
||||
} CAL_CNTLbits;
|
||||
};
|
||||
uint32_t CAL_COUNT;
|
||||
union {
|
||||
uint32_t RINGOSC_CNTL;
|
||||
struct CRM_RINGOSC_CNTL {
|
||||
uint32_t ROSC_EN:1;
|
||||
uint32_t :3;
|
||||
uint32_t ROSC_FTUNE:5;
|
||||
uint32_t ROSC_CTUNE:4;
|
||||
uint32_t :19;
|
||||
} RINGOSC_CNTLbits;
|
||||
};
|
||||
union {
|
||||
uint32_t XTAL_CNTL;
|
||||
struct CRM_XTAL_CNTL {
|
||||
uint32_t :8;
|
||||
uint32_t XTAL_IBIAS_SEL:4;
|
||||
uint32_t :4;
|
||||
uint32_t XTAL_FTUNE:5;
|
||||
uint32_t XTAL_CTUNE:5;
|
||||
uint32_t :6;
|
||||
} XTAL_CNTLbits;
|
||||
};
|
||||
union {
|
||||
uint32_t XTAL32_CNTL;
|
||||
struct CRM_XTAL32_CNTL {
|
||||
uint32_t XTAL32_EN:1;
|
||||
uint32_t :3;
|
||||
uint32_t XTAL32_GAIN:2;
|
||||
uint32_t :26;
|
||||
} XTAL32_CNTLbits;
|
||||
};
|
||||
union {
|
||||
uint32_t VREG_CNTL;
|
||||
struct CRM_VREG_CNTL {
|
||||
uint32_t BUCK_EN:1;
|
||||
uint32_t BUCK_SYNC_REC_EN:1;
|
||||
uint32_t BUCK_BYPASS_EN:1;
|
||||
uint32_t VREG_1P5V_EN:2;
|
||||
uint32_t VREG_1P5V_SEL:2;
|
||||
uint32_t VREG_1P8V_EN:1;
|
||||
uint32_t BUCK_CLKDIV:4;
|
||||
uint32_t :20;
|
||||
} VREG_CNTLbits;
|
||||
};
|
||||
uint32_t reserved2;
|
||||
uint32_t SW_RST;
|
||||
uint32_t reserved3;
|
||||
uint32_t reserved4;
|
||||
uint32_t reserved5;
|
||||
uint32_t reserved6;
|
||||
};
|
||||
|
||||
static volatile struct CRM_struct * const CRM = (void*) (CRM_BASE);
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* TIMERS */
|
||||
|
||||
#define F_CPU (24000000) ///< CPU target speed in Hz
|
||||
|
||||
/* Timer registers are all 16-bit wide with 16-bit access only */
|
||||
#define TMR_OFFSET (0x20)
|
||||
#define TMR_BASE (0x80007000)
|
||||
#define TMR0_BASE (TMR_BASE)
|
||||
#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
|
||||
#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
|
||||
#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
|
||||
|
||||
struct TMR_struct {
|
||||
uint16_t COMP1;
|
||||
uint16_t COMP2;
|
||||
uint16_t CAPT;
|
||||
uint16_t LOAD;
|
||||
uint16_t HOLD;
|
||||
uint16_t CNTR;
|
||||
union {
|
||||
uint16_t CTRL;
|
||||
struct TMR_CTRL {
|
||||
uint16_t OUTPUT_MODE:3;
|
||||
uint16_t CO_INIT:1;
|
||||
uint16_t DIR:1;
|
||||
uint16_t LENGTH:1;
|
||||
uint16_t ONCE:1;
|
||||
uint16_t SECONDARY_CNT_SOURCE:2;
|
||||
uint16_t PRIMARY_CNT_SOURCE:4;
|
||||
uint16_t COUNT_MODE:3;
|
||||
} CTRLbits;
|
||||
};
|
||||
union {
|
||||
uint16_t SCTRL;
|
||||
struct TMR_SCTRL {
|
||||
uint16_t OEN:1;
|
||||
uint16_t OPS:1;
|
||||
uint16_t FORCE:1;
|
||||
uint16_t VAL:1;
|
||||
uint16_t EEOF:1;
|
||||
uint16_t MSTR:1;
|
||||
uint16_t CAPTURE_MODE:2;
|
||||
uint16_t INPUT:1;
|
||||
uint16_t IPS:1;
|
||||
uint16_t IEFIE:1;
|
||||
uint16_t IEF:1;
|
||||
uint16_t TOFIE:1;
|
||||
uint16_t TOF:1;
|
||||
uint16_t TCFIE:1;
|
||||
uint16_t TCF:1;
|
||||
} SCTRLbits;
|
||||
};
|
||||
uint16_t CMPLD1;
|
||||
uint16_t CMPLD2;
|
||||
union {
|
||||
uint16_t CSCTRL;
|
||||
struct TMR_CSCTRL {
|
||||
uint16_t CL1:2;
|
||||
uint16_t CL2:2;
|
||||
uint16_t TCF1:1;
|
||||
uint16_t TCF2:1;
|
||||
uint16_t TCF1EN:1;
|
||||
uint16_t TCF2EN:1;
|
||||
uint16_t :5;
|
||||
uint16_t FILT_EN:1;
|
||||
uint16_t DBG_EN:2;
|
||||
} CSCTRLbits;
|
||||
};
|
||||
|
||||
uint16_t reserved[4];
|
||||
|
||||
union {
|
||||
uint16_t ENBL;
|
||||
struct TMR_ENBL {
|
||||
union {
|
||||
struct {
|
||||
uint16_t ENBL:4;
|
||||
};
|
||||
struct {
|
||||
uint16_t ENBL3:1;
|
||||
uint16_t ENBL2:1;
|
||||
uint16_t ENBL1:1;
|
||||
uint16_t ENBL0:1;
|
||||
};
|
||||
};
|
||||
uint16_t :12;
|
||||
} ENBLbits;
|
||||
};
|
||||
};
|
||||
|
||||
static volatile struct TMR_struct * const TMR0 = (void *) (TMR0_BASE);
|
||||
static volatile struct TMR_struct * const TMR1 = (void *) (TMR1_BASE);
|
||||
static volatile struct TMR_struct * const TMR2 = (void *) (TMR2_BASE);
|
||||
static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
|
||||
|
||||
/* Get timer pointer from timer number */
|
||||
#define TMR_ADDR(x) (*(volatile struct TMR_struct *)(((uint32_t)(x) * TMR_OFFSET) + TMR_BASE))
|
||||
|
||||
/* Get timer number from the timer pointer. */
|
||||
#define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* UART */
|
||||
#define UART1_BASE (0x80005000)
|
||||
#define UART2_BASE (0x8000B000)
|
||||
|
||||
struct UART_struct {
|
||||
union {
|
||||
uint32_t CON;
|
||||
struct UART_CON {
|
||||
uint32_t :16;
|
||||
uint32_t TST:1;
|
||||
uint32_t MRXR:1;
|
||||
uint32_t MTXR:1;
|
||||
uint32_t FCE:1;
|
||||
uint32_t FCP:1;
|
||||
uint32_t XTIM:1;
|
||||
uint32_t :2;
|
||||
uint32_t TXOENB:1;
|
||||
uint32_t CONTX:1;
|
||||
uint32_t SB:1;
|
||||
uint32_t ST2:1;
|
||||
uint32_t EP:1;
|
||||
uint32_t PEN:1;
|
||||
uint32_t RXE:1;
|
||||
uint32_t TXE:1;
|
||||
} CONbits;
|
||||
};
|
||||
union {
|
||||
uint32_t STAT;
|
||||
struct UART_STAT {
|
||||
uint32_t :24;
|
||||
uint32_t TXRDY:1;
|
||||
uint32_t RXRDY:1;
|
||||
uint32_t RUE:1;
|
||||
uint32_t ROE:1;
|
||||
uint32_t TOE:1;
|
||||
uint32_t FE:1;
|
||||
uint32_t PE:1;
|
||||
uint32_t SE:1;
|
||||
} USTATbits;
|
||||
};
|
||||
union {
|
||||
uint32_t DATA;
|
||||
struct UART_DATA {
|
||||
uint32_t :24;
|
||||
uint32_t DATA:8;
|
||||
} DATAbits;
|
||||
};
|
||||
union {
|
||||
uint32_t RXCON;
|
||||
struct UART_URXCON {
|
||||
uint32_t :26;
|
||||
uint32_t LVL:6;
|
||||
} RXCONbits;
|
||||
};
|
||||
union {
|
||||
uint32_t TXCON;
|
||||
struct UART_TXCON {
|
||||
uint32_t :26;
|
||||
uint32_t LVL:6;
|
||||
} TXCONbits;
|
||||
};
|
||||
union {
|
||||
uint32_t CTS;
|
||||
struct UART_CTS {
|
||||
uint32_t :27;
|
||||
uint32_t LVL:5;
|
||||
} CTSbits;
|
||||
};
|
||||
union {
|
||||
uint32_t BR;
|
||||
struct UART_BR {
|
||||
uint32_t INC:16;
|
||||
uint32_t MOD:16;
|
||||
} BRbits;
|
||||
};
|
||||
};
|
||||
|
||||
static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE);
|
||||
static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE);
|
||||
|
||||
#endif /* MC1322X_H */
|
||||
@ -0,0 +1,270 @@
|
||||
/* vim: set syntax=rpcgen : */
|
||||
/* Script for -z combreloc: combine and sort reloc sections */
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
|
||||
"elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_startup)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : org = 0x00400000, l = 96K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
SYS_STACK_SIZE = 1024;
|
||||
IRQ_STACK_SIZE = 256;
|
||||
FIQ_STACK_SIZE = 256;
|
||||
SVC_STACK_SIZE = 256;
|
||||
ABT_STACK_SIZE = 16;
|
||||
UND_STACK_SIZE = 16;
|
||||
HEAP_SIZE = 4096;
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
PROVIDE (__executable_start = 0x00400000); . = 0x00400000;
|
||||
.text :
|
||||
{
|
||||
*(.startup)
|
||||
*(.irq)
|
||||
*(.text .stub .text.* .gnu.linkonce.t.*)
|
||||
/* .gnu.warning sections are handled specially by elf32.em. */
|
||||
*(.gnu.warning)
|
||||
*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
|
||||
} =0
|
||||
|
||||
.interp : { *(.interp) }
|
||||
.note.gnu.build-id : { *(.note.gnu.build-id) }
|
||||
.hash : { *(.hash) }
|
||||
.gnu.hash : { *(.gnu.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.gnu.version : { *(.gnu.version) }
|
||||
.gnu.version_d : { *(.gnu.version_d) }
|
||||
.gnu.version_r : { *(.gnu.version_r) }
|
||||
.rel.dyn :
|
||||
{
|
||||
*(.rel.init)
|
||||
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
|
||||
*(.rel.fini)
|
||||
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
|
||||
*(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
|
||||
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
|
||||
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
|
||||
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
|
||||
*(.rel.ctors)
|
||||
*(.rel.dtors)
|
||||
*(.rel.got)
|
||||
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
|
||||
}
|
||||
.rela.dyn :
|
||||
{
|
||||
*(.rela.init)
|
||||
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
|
||||
*(.rela.fini)
|
||||
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
|
||||
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
|
||||
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
|
||||
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
|
||||
*(.rela.ctors)
|
||||
*(.rela.dtors)
|
||||
*(.rela.got)
|
||||
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
|
||||
}
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init :
|
||||
{
|
||||
KEEP (*(.init))
|
||||
} =0
|
||||
.plt : { *(.plt) }
|
||||
.fini :
|
||||
{
|
||||
KEEP (*(.fini))
|
||||
} =0
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
|
||||
.rodata1 : { *(.rodata1) }
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
|
||||
/* Adjust the address for the data segment. We want to adjust up to
|
||||
the same address within the page on the next page up. */
|
||||
|
||||
/* . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); */
|
||||
|
||||
. = ALIGN(4);
|
||||
. = DATA_SEGMENT_ALIGN(4,4);
|
||||
|
||||
/* Exception handling */
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
|
||||
/* Thread Local Storage sections */
|
||||
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
|
||||
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
}
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
}
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
}
|
||||
.jcr : { KEEP (*(.jcr)) }
|
||||
.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }
|
||||
.dynamic : { *(.dynamic) }
|
||||
. = DATA_SEGMENT_RELRO_END (0, .);
|
||||
.got : { *(.got.plt) *(.got) }
|
||||
.data :
|
||||
{
|
||||
__data_start = . ;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
SORT(CONSTRUCTORS)
|
||||
}
|
||||
.data1 : { *(.data1) }
|
||||
_edata = .; PROVIDE (edata = .);
|
||||
|
||||
.stack : {
|
||||
__stack_start__ = . ;
|
||||
|
||||
. += IRQ_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__irq_stack_top__ = . ;
|
||||
|
||||
. += FIQ_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__fiq_stack_top__ = . ;
|
||||
|
||||
. += SVC_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__svc_stack_top__ = . ;
|
||||
|
||||
. += ABT_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__abt_stack_top__ = . ;
|
||||
|
||||
. += UND_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__und_stack_top__ = . ;
|
||||
|
||||
. += SYS_STACK_SIZE;
|
||||
. = ALIGN (4);
|
||||
__sys_stack_top__ = . ;
|
||||
|
||||
__stack_end__ = .;
|
||||
}
|
||||
|
||||
|
||||
__bss_start = .;
|
||||
__bss_start__ = .;
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
/* Align here to ensure that the .bss section occupies space up to
|
||||
_end. Align after .bss to ensure correct alignment even if the
|
||||
.bss section disappears because there are no input sections.
|
||||
FIXME: Why do we need it? When there is no .bss section, we don't
|
||||
pad the .data section. */
|
||||
. = ALIGN(. != 0 ? 32 / 8 : 1);
|
||||
}
|
||||
_bss_end__ = . ; __bss_end__ = . ;
|
||||
. = ALIGN(32 / 8);
|
||||
|
||||
.heap : {
|
||||
__heap_start__ = . ; PROVIDE(__HEAP_START = .);
|
||||
*(.heap);
|
||||
. += HEAP_SIZE;
|
||||
. = ALIGN (4);
|
||||
__heap_end__ = . ; PROVIDE(__HEAP_END = .);
|
||||
}
|
||||
|
||||
|
||||
. = ALIGN(32 / 8);
|
||||
__end__ = . ;
|
||||
_end = .; PROVIDE (end = .);
|
||||
. = DATA_SEGMENT_END (.);
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* DWARF 3 */
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
|
||||
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) }
|
||||
}
|
||||
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* mc1322x_syscalls.c - MCU dependent syscall implementation
|
||||
* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
|
||||
*
|
||||
* This source code is licensed under the GNU General Public License,
|
||||
* Version 3. See the file LICENSE for more details.
|
||||
*
|
||||
* This file is part of RIOT.
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <sys/types.h>
|
||||
#include "irq.h"
|
||||
|
||||
extern uintptr_t __heap_start; ///< start of heap memory space
|
||||
extern uintptr_t __heap_end; ///< maximum for end of heap memory space
|
||||
|
||||
/// current position in heap
|
||||
static caddr_t heap = (caddr_t)&__heap_start;
|
||||
/// maximum position in heap
|
||||
static const caddr_t heap_max = (caddr_t)&__heap_end;
|
||||
// start position in heap
|
||||
static const caddr_t heap_start = (caddr_t)&__heap_start;
|
||||
|
||||
/*-----------------------------------------------------------------------------------*/
|
||||
caddr_t _sbrk_r(struct _reent *r, size_t incr)
|
||||
{
|
||||
uint32_t cpsr = disableIRQ();
|
||||
|
||||
/* check all heaps for a chunk of the requested size */
|
||||
caddr_t new_heap = heap + incr;
|
||||
|
||||
#ifdef MODULE_TRACELOG
|
||||
trace_pointer(TRACELOG_EV_MEMORY, heap);
|
||||
#endif
|
||||
if( new_heap <= heap_max ) {
|
||||
caddr_t prev_heap = heap;
|
||||
#ifdef MODULE_TRACELOG
|
||||
trace_pointer(TRACELOG_EV_MEMORY, new_heap);
|
||||
#endif
|
||||
heap = new_heap;
|
||||
|
||||
r->_errno = 0;
|
||||
restoreIRQ(cpsr);
|
||||
return prev_heap;
|
||||
}
|
||||
restoreIRQ(cpsr);
|
||||
#ifdef MODULE_TRACELOG
|
||||
trace_string(TRACELOG_EV_MEMORY, "heap!"); // heap full
|
||||
#endif
|
||||
|
||||
r->_errno = ENOMEM;
|
||||
return NULL;
|
||||
}
|
||||
@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
|
||||
* to the MC1322x project (http:/*mc1322x.devl.org) and Contiki.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the Contiki OS.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
The following lincence is for all parts of this code done by | ||||