boards/nucleo-f030: initial support
Alexandre Abadie
7 years ago
parent
88d03aebfe
commit
3f29e77a4c
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m0_1
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## the cpu to build for
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export CPU = stm32f0
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export CPU_MODEL = stm32f030r8
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/nucleo-common/Makefile.include
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f030
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo-f030 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author José Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the boards LED */
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gpio_init(LED0_PIN, GPIO_OUT);
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/* initialize the CPU */
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cpu_init();
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}
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source [find board/st_nucleo_f0.cfg]
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-f030 Nucleo-F030
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* @ingroup boards
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* @brief Board specific files for the nucleo-f030 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo-f030 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Mohmmad Ayman <mohmmad.khzrag@gmail.com>
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* @author José Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include <stdint.h>
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#include "board_common.h"
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief xtimer configuration
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* @{
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*/
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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/** @} */
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@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f030
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-f030 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author José Ignacio Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_FREQ (CLOCK_CORECLOCK)
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#define TIMER_0_MAX_VALUE (0x0000ffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
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#define TIMER_0_IRQ_CHAN TIM3_IRQn
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#define TIMER_0_ISR isr_tim3
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/** @} */
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/**
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* @brief UART configuration
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* @}
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*/
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#define UART_NUMOF (2U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLKDIS() (RCC->APB1ENR &= (~RCC_APB1ENR_USART2EN))
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#define UART_0_IRQ USART2_IRQn
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#define UART_0_ISR isr_usart2
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_0_RX_PIN 3
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#define UART_0_TX_PIN 2
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#define UART_0_AF 1
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/* UART 1 device configuration */
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#define UART_1_DEV USART1
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#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_1_CLKDIS() (RCC->APB2ENR &= (~RCC_APB2ENR_USART1EN))
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#define UART_1_IRQ USART1_IRQn
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#define UART_1_ISR isr_usart1
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOB
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#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define UART_1_RX_PIN 7
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#define UART_1_TX_PIN 6
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#define UART_1_AF 0
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/** @} */
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/**
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* @brief ADC configuration
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* @{
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*/
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#define ADC_CONFIG { \
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{ GPIO_PIN(PORT_A, 0), 0 },\
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{ GPIO_PIN(PORT_A, 1), 1 },\
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{ GPIO_PIN(PORT_A, 4), 4 },\
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{ GPIO_PIN(PORT_B, 0), 8 },\
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{ GPIO_PIN(PORT_C, 1), 11 },\
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{ GPIO_PIN(PORT_C, 0), 10 } \
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}
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#define ADC_NUMOF (6)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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/**
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* Nucleos with MB1136 C-02 or MB1136 C-03 -sticker on it have the required LSE
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* oscillator provided on the X2 slot.
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* See Nucleo User Manual UM1724 section 5.6.2.
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*/
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#define RTC_NUMOF (1U)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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