cpu/stm32f1: optimize ACR setting and move to cpu.c

boards/fox/include/periph_conf.h

@@ -42,8 +42,6 @@ extern "C" {
 /* resulting bus clocks */
 #define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 #define CLOCK_APB2          (CLOCK_CORECLOCK)
-/* configuration of flash access cycles */
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
 /** @} */
 
 /**

boards/iotlab-common/include/periph_conf_common.h

@@ -40,8 +40,6 @@ extern "C" {
 #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1      /* AHB clock -> 72MHz */
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 72MHz */
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* APB1 clock -> 36MHz */
-/* configuration of flash access cycles */
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
 
 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
 #define CLOCK_AHB           (CLOCK_CORECLOCK / 1)

boards/nucleo-f103/include/periph_conf.h

@@ -38,8 +38,6 @@ extern "C" {
 #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2    /* max 36 MHz (!) */
-/* Flash latency */
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2    /* for >= 72 MHz */
 
 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
 #define CLOCK_AHB           (CLOCK_CORECLOCK / 1)

boards/spark-core/include/periph_conf.h

@@ -42,8 +42,6 @@
 /* resulting bus clocks */
 #define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 #define CLOCK_APB2          (CLOCK_CORECLOCK)
-/* configuration of flash access cycles */
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
 /** @} */
 
  /**

cpu/stm32f1/cpu.c

@@ -28,6 +28,15 @@
 #include "cpu.h"
 #include "periph_conf.h"
 
+/* Configuration of flash access cycles */
+#if CLOCK_CORECLOCK <= 24000000
+#define FLASH_LATENCY (0) /* Zero wait state, if 0 < SYSCLK≤ 24 MHz */
+#elif CLOCK_CORECLOCK <= 48000000
+#define FLASH_LATENCY (1) /* One wait states, if 24 MHz < SYSCLK ≤ 48 MHz */
+#elif CLOCK_CORECLOCK <= 72000000
+#define FLASH_LATENCY (2) /* Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz */
+#endif
+
 /* See if we want to use the PLL */
 #if defined(CLOCK_PLL_DIV) || defined(CLOCK_PLL_MUL)
 #define CLOCK_USE_PLL              1
@@ -121,11 +130,8 @@ static void clk_init(void)
     /* Wait till the high speed clock source is ready
      * NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */
     while ((RCC->CR & CLOCK_CR_SOURCE_RDY) == 0) {}
-    /* Enable Prefetch Buffer */
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-    /* Set the flash wait state */
-    FLASH->ACR &= ~((uint32_t)FLASH_ACR_LATENCY);
-    FLASH->ACR |= (uint32_t)CLOCK_FLASH_LATENCY;
+    /* Enable prefetch buffer and set flash wait state */
+    FLASH->ACR = (uint32_t)(FLASH_ACR_PRFTBE | FLASH_LATENCY);
     /* HCLK = SYSCLK */
     RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
     /* PCLK2 = HCLK */