Browse Source

drivers/kw2xrf: cleanup

- use generic short and long address generator
    - defines in main header file
    - refine debug output
    - correct signed/unsigned warnings
patch-1
smlng 6 years ago
parent
commit
432b03e99e
  1. 17
      drivers/Makefile.dep
  2. 32
      drivers/include/kw2xrf.h
  3. 60
      drivers/kw2xrf/kw2xrf.c
  4. 45
      drivers/kw2xrf/kw2xrf_getset.c
  5. 22
      drivers/kw2xrf/kw2xrf_intern.c
  6. 61
      drivers/kw2xrf/kw2xrf_netdev.c
  7. 14
      drivers/kw2xrf/kw2xrf_spi.c

17
drivers/Makefile.dep

@ -114,14 +114,15 @@ ifneq (,$(filter jc42,$(USEMODULE)))
endif
ifneq (,$(filter kw2xrf,$(USEMODULE)))
USEMODULE += ieee802154
USEMODULE += netif
USEMODULE += netdev2_ieee802154
ifneq (,$(filter gnrc_netdev_default,$(USEMODULE)))
# XXX: this can be modelled as a dependency for gnrc_netdev_default as soon
# as all drivers are ported to netdev2
USEMODULE += gnrc_netdev2
endif
USEMODULE += uuid
USEMODULE += netif
USEMODULE += ieee802154
USEMODULE += netdev2_ieee802154
ifneq (,$(filter gnrc_netdev_default,$(USEMODULE)))
# XXX: this can be modelled as a dependency for gnrc_netdev_default as soon
# as all drivers are ported to netdev2
USEMODULE += gnrc_netdev2
endif
endif
ifneq (,$(filter lis3dh,$(USEMODULE)))

32
drivers/include/kw2xrf.h

@ -17,10 +17,11 @@
*
* @author Johann Fischer <j.fischer@phytec.de>
* @author Jonas Remmert <j.remmert@phytec.de>
* @author Sebastian Meiling <s@mlng.net>
*/
#ifndef MKW2XDRF_H
#define MKW2XDRF_H
#ifndef KW2XDRF_H
#define KW2XDRF_H
#include <stdint.h>
@ -38,33 +39,20 @@ extern "C" {
/**
* @brief Maximum packet length
*/
#define KW2XRF_MAX_PKT_LENGTH (IEEE802154_FRAME_LEN_MAX)
/**
* @brief Default short address used after initialization
*/
#define KW2XRF_DEFAULT_SHORT_ADDR (0x0042)
/**
* @brief Default short address used after initialization
*/
#define KW2XRF_DEFAULT_ADDR_LONG (0x0000000DEADCAB1E)
#define KW2XRF_MAX_PKT_LENGTH (IEEE802154_FRAME_LEN_MAX)
/**
* @brief Default PAN ID used after initialization
*/
#define KW2XRF_DEFAULT_PANID (IEEE802154_DEFAULT_PANID)
#define KW2XRF_DEFAULT_PANID (IEEE802154_DEFAULT_PANID)
/**
* @brief Default channel used after initialization
*
* @{
*/
#ifdef DEFAULT_CHANNEL
#define KW2XRF_DEFAULT_CHANNEL (DEFAULT_CHANNEL)
#endif
#ifndef KW2XRF_DEFAULT_CHANNEL
#define KW2XRF_DEFAULT_CHANNEL (IEEE802154_DEFAULT_CHANNEL)
#define KW2XRF_DEFAULT_CHANNEL (IEEE802154_DEFAULT_CHANNEL)
#endif
/** @} */
@ -80,17 +68,17 @@ extern "C" {
/**
* @brief Default TX_POWER in dbm used after initialization
*/
#define KW2XRF_DEFAULT_TX_POWER (IEEE802154_DEFAULT_TXPOWER)
#define KW2XRF_DEFAULT_TX_POWER (IEEE802154_DEFAULT_TXPOWER)
/**
* @brief Maximum output power of the kw2x device in dBm
*/
#define MKW2XDRF_OUTPUT_POWER_MAX (8)
#define KW2XDRF_OUTPUT_POWER_MAX (8)
/**
* @brief Minimum output power of the kw2x device in dBm
*/
#define MKW2XDRF_OUTPUT_POWER_MIN (-35)
#define KW2XDRF_OUTPUT_POWER_MIN (-35)
/**
* @brief Internal device option flags
@ -182,5 +170,5 @@ void kw2xrf_reset_phy(kw2xrf_t *dev);
}
#endif
#endif /* MKW2XDRF_H */
#endif /* KW2XDRF_H */
/** @} */

60
drivers/kw2xrf/kw2xrf.c

@ -15,17 +15,20 @@
* @author Johann Fischer <j.fischer@phytec.de>
* @author Jonas Remmert <j.remmert@phytec.de>
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Sebastian Meiling <s@mlng.net>
* @}
*/
#include <stdint.h>
#include <string.h>
#include "log.h"
#include "mutex.h"
#include "msg.h"
#include "periph/gpio.h"
#include "periph/cpuid.h"
#include "net/gnrc.h"
#include "net/ieee802154.h"
#include "uuid.h"
#include "kw2xrf.h"
#include "kw2xrf_spi.h"
@ -37,55 +40,22 @@
#define ENABLE_DEBUG (0)
#include "debug.h"
#if CPUID_LEN
/* make sure that the buffer is always big enough to store a 64bit value */
#if CPUID_LEN < IEEE802154_LONG_ADDRESS_LEN
#define KW2XRF_ID_LEN IEEE802154_LONG_ADDRESS_LEN
#else
#define KW2XRF_ID_LEN CPUID_LEN
#endif
#endif
static void kw2xrf_set_address(kw2xrf_t *dev)
{
DEBUG("[kw2xrf] set MAC addresses\n");
eui64_t addr_long;
addr_long.uint64.u64 = KW2XRF_DEFAULT_ADDR_LONG;
uint16_t addr_short = KW2XRF_DEFAULT_SHORT_ADDR;
#if CPUID_LEN
if (CPUID_LEN) {
uint8_t cpuid[KW2XRF_ID_LEN];
/* in case CPUID_LEN < 8, fill missing bytes with zeros */
memset(cpuid, 0, CPUID_LEN);
cpuid_get(cpuid);
/* generate short hardware address if CPUID_LEN > 0 */
for (int i = 0; i < CPUID_LEN; i++) {
/* XOR each even byte of the CPUID with LSB of short address
and each odd byte with MSB */
addr_short ^= (uint16_t)(cpuid[i] << ((i & 0x01) * 8));
}
for (int i = IEEE802154_LONG_ADDRESS_LEN; i < CPUID_LEN; i++) {
cpuid[i & 0x07] ^= cpuid[i];
}
/* make sure we mark the address as non-multicast and not globally unique */
cpuid[0] &= ~(0x01);
cpuid[0] |= 0x02;
/* copy and set long address */
memcpy(&addr_long, cpuid, IEEE802154_LONG_ADDRESS_LEN);
}
#endif
kw2xrf_set_addr_long(dev, addr_long.uint64.u64);
kw2xrf_set_addr_short(dev, addr_short);
/* get an 8-byte unique ID to use as hardware address */
uuid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
/* make sure we mark the address as non-multicast and not globally unique */
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
kw2xrf_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
kw2xrf_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
}
void kw2xrf_setup(kw2xrf_t *dev, const kw2xrf_params_t *params)
{
DEBUG("[kw2xrf]: kw2xrf_setup\n");
netdev2_t *netdev = (netdev2_t *)dev;
netdev->driver = &kw2xrf_driver;
@ -96,7 +66,7 @@ void kw2xrf_setup(kw2xrf_t *dev, const kw2xrf_params_t *params)
dev->pending_tx = 0;
kw2xrf_spi_init(dev);
kw2xrf_set_power_mode(dev, KW2XRF_IDLE);
DEBUG("[kw2xrf]: setup finished\n");
DEBUG("[kw2xrf] setup finished\n");
}
int kw2xrf_init(kw2xrf_t *dev, gpio_cb_t cb)
@ -113,7 +83,7 @@ int kw2xrf_init(kw2xrf_t *dev, gpio_cb_t cb)
kw2xrf_abort_sequence(dev);
kw2xrf_update_overwrites(dev);
kw2xrf_timer_init(dev, KW2XRF_TIMEBASE_62500HZ);
DEBUG("[kw2xrf]: init finished\n");
DEBUG("[kw2xrf] init finished\n");
return 0;
}
@ -157,6 +127,6 @@ void kw2xrf_reset_phy(kw2xrf_t *dev)
kw2xrf_enable_irq_b(dev);
DEBUG("[kw2xrf]: Initialized and set to channel %d and pan %d.\n",
DEBUG("[kw2xrf] init phy and (re)set to channel %d and pan %d.\n",
KW2XRF_DEFAULT_CHANNEL, KW2XRF_DEFAULT_PANID);
}

45
drivers/kw2xrf/kw2xrf_getset.c

@ -15,23 +15,27 @@
* @author Johann Fischer <j.fischer@phytec.de>
* @author Jonas Remmert <j.remmert@phytec.de>
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Sebastian Meiling <s@mlng.net>
* @}
*/
#include "log.h"
#include "kw2xrf.h"
#include "kw2xrf_spi.h"
#include "kw2xrf_reg.h"
#include "kw2xrf_getset.h"
#include "kw2xrf_intern.h"
#define ENABLE_DEBUG (0)
#define ENABLE_DEBUG (0)
#include "debug.h"
#define KW2XRF_LQI_HW_MAX 230 /**< LQI Saturation Level */
/* Modem_PA_PWR Register (PA Power Control) has a valid range from 3-31 */
#define MKW2XDRF_PA_RANGE_MAX 31 /**< Maximum value of PA Power Control Register */
#define MKW2XDRF_PA_RANGE_MIN 3 /**< Minimum value of PA Power Control Register */
#define KW2XRF_PA_RANGE_MAX 31 /**< Maximum value of PA Power Control Register */
#define KW2XRF_PA_RANGE_MIN 3 /**< Minimum value of PA Power Control Register */
#define KW2XRF_NUM_CHANNEL (KW2XRF_MAX_CHANNEL - KW2XRF_MIN_CHANNEL + 1)
/* PLL integer and fractional lookup tables
*
@ -71,16 +75,17 @@ static const uint8_t pow_lt[44] = {
void kw2xrf_set_tx_power(kw2xrf_t *dev, int16_t txpower)
{
if (txpower > MKW2XDRF_OUTPUT_POWER_MAX) {
txpower = MKW2XDRF_OUTPUT_POWER_MAX;
if (txpower > KW2XDRF_OUTPUT_POWER_MAX) {
txpower = KW2XDRF_OUTPUT_POWER_MAX;
}
if (txpower < MKW2XDRF_OUTPUT_POWER_MIN) {
txpower = MKW2XDRF_OUTPUT_POWER_MIN;
if (txpower < KW2XDRF_OUTPUT_POWER_MIN) {
txpower = KW2XDRF_OUTPUT_POWER_MIN;
}
uint8_t level = pow_lt[txpower - MKW2XDRF_OUTPUT_POWER_MIN];
uint8_t level = pow_lt[txpower - KW2XDRF_OUTPUT_POWER_MIN];
kw2xrf_write_dreg(dev, MKW2XDM_PA_PWR, MKW2XDM_PA_PWR(level));
LOG_DEBUG("[kw2xrf] set txpower to: %d\n", txpower);
dev->tx_power = txpower;
}
@ -95,7 +100,7 @@ uint8_t kw2xrf_get_channel(kw2xrf_t *dev)
uint16_t pll_frac = kw2xrf_read_dreg(dev, MKW2XDM_PLL_FRAC0_LSB);
pll_frac |= ((uint16_t)kw2xrf_read_dreg(dev, MKW2XDM_PLL_FRAC0_MSB) << 8);
for (int i = 0; i < 16; i++) {
for (unsigned i = 0; i < KW2XRF_NUM_CHANNEL; i++) {
if ((pll_frac_lt[i] == pll_frac) && (pll_int_lt[i] == pll_int)) {
return i + 11;
}
@ -117,7 +122,7 @@ int kw2xrf_set_channel(kw2xrf_t *dev, uint8_t channel)
uint8_t old_seq = kw2xrf_get_sequence(dev);
if (channel < KW2XRF_MIN_CHANNEL || channel > KW2XRF_MAX_CHANNEL) {
DEBUG("[kw2xrf]: Invalid channel %i set\n", channel);
LOG_ERROR("[kw2xrf] Invalid channel %u\n", channel);
return -1;
}
@ -136,7 +141,7 @@ int kw2xrf_set_channel(kw2xrf_t *dev, uint8_t channel)
kw2xrf_set_sequence(dev, old_seq);
}
DEBUG("[kw2xrf]: set channel to %u\n", channel);
LOG_DEBUG("[kw2xrf] set channel to %u\n", channel);
return 0;
}
@ -156,7 +161,7 @@ void kw2xrf_abort_sequence(kw2xrf_t *dev)
uint8_t state;
do {
state = kw2xrf_read_dreg(dev, MKW2XDM_SEQ_STATE);
DEBUG("[kw2xrf]: abort SEQ_STATE: %x\n", state);
DEBUG("[kw2xrf] abort SEQ_STATE: %x\n", state);
} while ((state & 0x1F) != 0);
/* clear all IRQ bits */
@ -182,7 +187,7 @@ void kw2xrf_set_idle_sequence(kw2xrf_t *dev)
kw2xrf_write_dreg(dev, MKW2XDM_PHY_CTRL1, reg);
if (dev->pending_tx) {
DEBUG("[kw2xrf]: pending tx, cannot set idle sequenz\n");
DEBUG("[kw2xrf] pending tx, cannot set idle sequenz\n");
return;
}
@ -210,7 +215,6 @@ void kw2xrf_set_idle_sequence(kw2xrf_t *dev)
default:
dev->state = NETOPT_STATE_IDLE;
}
kw2xrf_enable_irq_b(dev);
}
@ -238,11 +242,11 @@ void kw2xrf_set_sequence(kw2xrf_t *dev, kw2xrf_physeq_t seq)
break;
default:
DEBUG("[kw2xrf]: undefined state assigned to phy\n");
DEBUG("[kw2xrf] undefined state assigned to phy\n");
dev->state = NETOPT_STATE_IDLE;
}
DEBUG("[kw2xrf]: set sequence to %i\n", seq);
DEBUG("[kw2xrf] set sequence to %i\n", seq);
reg = kw2xrf_read_dreg(dev, MKW2XDM_PHY_CTRL1);
reg &= ~(MKW2XDM_PHY_CTRL1_XCVSEQ_MASK);
reg |= MKW2XDM_PHY_CTRL1_XCVSEQ(seq);
@ -257,6 +261,7 @@ void kw2xrf_set_pan(kw2xrf_t *dev, uint16_t pan)
val_ar[1] = (pan >> 8);
val_ar[0] = (uint8_t)pan;
kw2xrf_write_iregs(dev, MKW2XDMI_MACPANID0_LSB, val_ar, 2);
LOG_DEBUG("[kw2xrf] set pan to: 0x%x\n", pan);
dev->netdev.pan = pan;
}
@ -281,7 +286,7 @@ void kw2xrf_set_addr_long(kw2xrf_t *dev, uint64_t addr)
uint64_t tmp;
uint8_t *ap = (uint8_t *)(&tmp);
for (int i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) {
for (unsigned i = 0; i < IEEE802154_LONG_ADDRESS_LEN; i++) {
dev->netdev.long_addr[i] = (uint8_t)(addr >> (i * 8));
ap[i] = (addr >> ((IEEE802154_LONG_ADDRESS_LEN - 1 - i) * 8));
}
@ -361,7 +366,7 @@ uint32_t kw2xrf_get_rssi(uint32_t value)
void kw2xrf_set_option(kw2xrf_t *dev, uint16_t option, bool state)
{
DEBUG("[kw2xrf]: set option %i to %i\n", option, state);
DEBUG("[kw2xrf] set option %i to %i\n", option, state);
/* set option field */
if (state) {
@ -370,13 +375,13 @@ void kw2xrf_set_option(kw2xrf_t *dev, uint16_t option, bool state)
/* trigger option specific actions */
switch (option) {
case KW2XRF_OPT_AUTOCCA:
DEBUG("[kw2xrf] opt: enabling CCA before TX mode\n");
LOG_DEBUG("[kw2xrf] opt: enabling CCA before TX mode\n");
kw2xrf_set_dreg_bit(dev, MKW2XDM_PHY_CTRL1,
MKW2XDM_PHY_CTRL1_CCABFRTX);
break;
case KW2XRF_OPT_PROMISCUOUS:
DEBUG("[kw2xrf] opt: enabling PROMISCUOUS mode\n");
LOG_DEBUG("[kw2xrf] opt: enabling PROMISCUOUS mode\n");
/* disable auto ACKs in promiscuous mode */
kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL1,
MKW2XDM_PHY_CTRL1_AUTOACK | MKW2XDM_PHY_CTRL1_RXACKRQD);

22
drivers/kw2xrf/kw2xrf_intern.c

@ -24,11 +24,12 @@
#include "kw2xrf_intern.h"
#include "overwrites.h"
#define ENABLE_DEBUG (0)
#define ENABLE_DEBUG (0)
#include "debug.h"
void kw2xrf_disable_interrupts(kw2xrf_t *dev)
{
DEBUG("[kw2xrf] disable interrupts\n");
/* Clear and disable all interrupts */
kw2xrf_write_dreg(dev, MKW2XDM_PHY_CTRL2, 0xff);
int reg = kw2xrf_read_dreg(dev, MKW2XDM_PHY_CTRL3);
@ -62,7 +63,7 @@ void kw2xrf_set_out_clk(kw2xrf_t *dev)
void kw2xrf_set_power_mode(kw2xrf_t *dev, kw2xrf_powermode_t pm)
{
DEBUG("[kw2xrf]: kw2xrf_set_power_mode\n");
DEBUG("[kw2xrf] set power mode to %d\n", pm);
uint8_t reg = 0;
switch (pm) {
case KW2XRF_HIBERNATE:
@ -95,7 +96,7 @@ int kw2xrf_can_switch_to_idle(kw2xrf_t *dev)
{
uint8_t state = kw2xrf_read_dreg(dev, MKW2XDM_SEQ_STATE);
uint8_t seq = kw2xrf_read_dreg(dev, MKW2XDM_PHY_CTRL1) & MKW2XDM_PHY_CTRL1_XCVSEQ_MASK;
DEBUG("[kw2xrf]: state 0x%0x, seq 0x%0x\n", state, seq);
DEBUG("[kw2xrf] state 0x%0x, seq 0x%0x\n", state, seq);
if ((seq != XCVSEQ_TRANSMIT) && (seq != XCVSEQ_TX_RX)) {
return 1;
@ -175,10 +176,7 @@ void kw2xrf_trigger_tx_ops_disable(kw2xrf_t *dev)
{
kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL3, MKW2XDM_PHY_CTRL3_TMR2CMP_EN);
kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS3, MKW2XDM_IRQSTS3_TMR2IRQ);
if (ENABLE_DEBUG) {
uint32_t now = kw2xrf_timer_get(dev);
printf("[kw2xrf] now: %" PRIx32 "\n", now);
}
DEBUG("[kw2xrf] trigger_tx_ops_disable, now: %" PRIx32 "\n", kw2xrf_timer_get(dev));
}
void kw2xrf_abort_rx_ops_enable(kw2xrf_t *dev, uint32_t timeout)
@ -191,10 +189,7 @@ void kw2xrf_abort_rx_ops_disable(kw2xrf_t *dev)
{
kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL3, MKW2XDM_PHY_CTRL3_TMR3CMP_EN);
kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS3, MKW2XDM_IRQSTS3_TMR3IRQ);
if (ENABLE_DEBUG) {
uint32_t now = kw2xrf_timer_get(dev);
printf("[kw2xrf] now: %" PRIx32 "\n", now);
}
DEBUG("[kw2xrf] abort_rx_ops_disable, now: %" PRIx32 "\n", kw2xrf_timer_get(dev));
}
void kw2xrf_seq_timeout_on(kw2xrf_t *dev, uint32_t timeout)
@ -216,10 +211,7 @@ void kw2xrf_seq_timeout_off(kw2xrf_t *dev)
{
kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL3, MKW2XDM_PHY_CTRL3_TMR4CMP_EN);
kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS3, MKW2XDM_IRQSTS3_TMR4IRQ);
if (ENABLE_DEBUG) {
uint32_t now = kw2xrf_timer_get(dev);
printf("[kw2xrf] now: %" PRIx32 "\n", now);
}
DEBUG("[kw2xrf] seq_timeout_off, now: %" PRIx32 "\n", kw2xrf_timer_get(dev));
}
uint32_t kw2xrf_get_timestamp(kw2xrf_t *dev)

61
drivers/kw2xrf/kw2xrf_netdev.c

@ -20,6 +20,7 @@
#include <assert.h>
#include <errno.h>
#include "log.h"
#include "net/eui64.h"
#include "net/ieee802154.h"
#include "net/netdev2.h"
@ -33,7 +34,7 @@
#include "kw2xrf_tm.h"
#include "kw2xrf_intern.h"
#define ENABLE_DEBUG (0)
#define ENABLE_DEBUG (0)
#include "debug.h"
#define _MAX_MHR_OVERHEAD (25)
@ -57,7 +58,7 @@ static int _init(netdev2_t *netdev)
/* initialise SPI and GPIOs */
if (kw2xrf_init(dev, &_irq_handler)) {
DEBUG("[kw2xrf]: error: unable to initialize device\n");
LOG_ERROR("[kw2xrf] unable to initialize device\n");
return -1;
}
@ -73,7 +74,7 @@ static int _init(netdev2_t *netdev)
static size_t kw2xrf_tx_load(uint8_t *pkt_buf, uint8_t *buf, size_t len, size_t offset)
{
for (int i = 0; i < len; i++) {
for (unsigned i = 0; i < len; i++) {
pkt_buf[i + offset] = buf[i];
}
return offset + len;
@ -101,7 +102,7 @@ static int _send(netdev2_t *netdev, const struct iovec *vector, unsigned count)
for (unsigned i = 0; i < count; i++, ptr++) {
/* current packet data + FCS too long */
if ((len + ptr->iov_len + IEEE802154_FCS_LEN) > KW2XRF_MAX_PKT_LENGTH) {
DEBUG("[kw2xrf]: error: packet too large (%u byte) to be send\n",
LOG_ERROR("[kw2xrf] packet too large (%u byte) to be send\n",
(unsigned)len + IEEE802154_FCS_LEN);
return -EOVERFLOW;
}
@ -518,13 +519,13 @@ static void _isr_event_seq_r(netdev2_t *netdev, uint8_t *dregs)
uint8_t irqsts1 = 0;
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_RXWTRMRKIRQ) {
DEBUG("[kw2xrf]: got RXWTRMRKIRQ\n");
DEBUG("[kw2xrf] got RXWTRMRKIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_RXWTRMRKIRQ;
netdev->event_callback(netdev, NETDEV2_EVENT_RX_STARTED);
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_RXIRQ) {
DEBUG("[kw2xrf]: finished RXSEQ\n");
DEBUG("[kw2xrf] finished RXSEQ\n");
dev->state = NETOPT_STATE_RX;
irqsts1 |= MKW2XDM_IRQSTS1_RXIRQ;
netdev->event_callback(netdev, NETDEV2_EVENT_RX_COMPLETE);
@ -534,12 +535,12 @@ static void _isr_event_seq_r(netdev2_t *netdev, uint8_t *dregs)
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_TXIRQ) {
DEBUG("[kw2xrf]: finished (ACK) TXSEQ\n");
DEBUG("[kw2xrf] finished (ACK) TXSEQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_TXIRQ;
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_SEQIRQ) {
DEBUG("[kw2xrf]: SEQIRQ\n");
DEBUG("[kw2xrf] SEQIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_SEQIRQ;
kw2xrf_set_idle_sequence(dev);
}
@ -554,18 +555,18 @@ static void _isr_event_seq_t(netdev2_t *netdev, uint8_t *dregs)
uint8_t irqsts1 = 0;
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_TXIRQ) {
DEBUG("[kw2xrf]: finished TXSEQ\n");
DEBUG("[kw2xrf] finished TXSEQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_TXIRQ;
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_SEQIRQ) {
DEBUG("[kw2xrf]: SEQIRQ\n");
DEBUG("[kw2xrf] SEQIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_SEQIRQ;
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_CCAIRQ) {
irqsts1 |= MKW2XDM_IRQSTS1_CCAIRQ;
if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_CCA) {
DEBUG("[kw2xrf]: CCA CH busy\n");
DEBUG("[kw2xrf] CCA CH busy\n");
netdev->event_callback(netdev, NETDEV2_EVENT_TX_MEDIUM_BUSY);
}
else {
@ -592,10 +593,10 @@ static void _isr_event_seq_cca(netdev2_t *netdev, uint8_t *dregs)
(dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_SEQIRQ)) {
irqsts1 |= MKW2XDM_IRQSTS1_CCAIRQ | MKW2XDM_IRQSTS1_SEQIRQ;
if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_CCA) {
DEBUG("[kw2xrf]: SEQIRQ, CCA CH busy\n");
DEBUG("[kw2xrf] SEQIRQ, CCA CH busy\n");
}
else {
DEBUG("[kw2xrf]: SEQIRQ, CCA CH idle\n");
DEBUG("[kw2xrf] SEQIRQ, CCA CH idle\n");
}
kw2xrf_set_idle_sequence(dev);
}
@ -609,26 +610,26 @@ static void _isr_event_seq_tr(netdev2_t *netdev, uint8_t *dregs)
uint8_t irqsts1 = 0;
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_TXIRQ) {
DEBUG("[kw2xrf]: finished TXSEQ\n");
DEBUG("[kw2xrf] finished TXSEQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_TXIRQ;
if (dregs[MKW2XDM_PHY_CTRL1] & MKW2XDM_PHY_CTRL1_RXACKRQD) {
DEBUG("[kw2xrf]: wait for RX ACK\n");
DEBUG("[kw2xrf] wait for RX ACK\n");
kw2xrf_seq_timeout_on(dev, _MACACKWAITDURATION);
}
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_RXWTRMRKIRQ) {
DEBUG("[kw2xrf]: got RXWTRMRKIRQ\n");
DEBUG("[kw2xrf] got RXWTRMRKIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_RXWTRMRKIRQ;
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_FILTERFAIL_IRQ) {
DEBUG("[kw2xrf]: got FILTERFAILIRQ\n");
DEBUG("[kw2xrf] got FILTERFAILIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_FILTERFAIL_IRQ;
}
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_RXIRQ) {
DEBUG("[kw2xrf]: got RX ACK\n");
DEBUG("[kw2xrf] got RX ACK\n");
irqsts1 |= MKW2XDM_IRQSTS1_RXIRQ;
}
@ -636,12 +637,12 @@ static void _isr_event_seq_tr(netdev2_t *netdev, uint8_t *dregs)
if (dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_CCAIRQ) {
irqsts1 |= MKW2XDM_IRQSTS1_CCAIRQ;
if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_CCA) {
DEBUG("[kw2xrf]: CCA CH busy\n");
DEBUG("[kw2xrf] CCA CH busy\n");
netdev->event_callback(netdev, NETDEV2_EVENT_TX_MEDIUM_BUSY);
}
}
DEBUG("[kw2xrf]: SEQIRQ\n");
DEBUG("[kw2xrf] SEQIRQ\n");
irqsts1 |= MKW2XDM_IRQSTS1_SEQIRQ;
assert(dev->pending_tx != 0);
dev->pending_tx--;
@ -650,7 +651,7 @@ static void _isr_event_seq_tr(netdev2_t *netdev, uint8_t *dregs)
kw2xrf_set_idle_sequence(dev);
}
else if (dregs[MKW2XDM_IRQSTS3] & MKW2XDM_IRQSTS3_TMR4IRQ) {
DEBUG("[kw2xrf]: TC4TMOUT, no SEQIRQ, TX failed\n");
DEBUG("[kw2xrf] TC4TMOUT, no SEQIRQ, TX failed\n");
assert(dev->pending_tx != 0);
dev->pending_tx--;
netdev->event_callback(netdev, NETDEV2_EVENT_TX_NOACK);
@ -670,13 +671,13 @@ static void _isr_event_seq_ccca(netdev2_t *netdev, uint8_t *dregs)
if ((dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_CCAIRQ) &&
(dregs[MKW2XDM_IRQSTS1] & MKW2XDM_IRQSTS1_SEQIRQ)) {
irqsts1 |= MKW2XDM_IRQSTS1_CCAIRQ | MKW2XDM_IRQSTS1_SEQIRQ;
DEBUG("[kw2xrf]: CCCA CH idle\n");
DEBUG("[kw2xrf] CCCA CH idle\n");
kw2xrf_seq_timeout_off(dev);
kw2xrf_set_sequence(dev, dev->idle_state);
}
else if (dregs[MKW2XDM_IRQSTS3] & MKW2XDM_IRQSTS3_TMR4IRQ) {
irqsts1 |= MKW2XDM_IRQSTS1_CCAIRQ | MKW2XDM_IRQSTS1_SEQIRQ;
DEBUG("[kw2xrf]: CCCA timeout\n");
DEBUG("[kw2xrf] CCCA timeout\n");
kw2xrf_seq_timeout_off(dev);
kw2xrf_set_sequence(dev, dev->idle_state);
}
@ -692,7 +693,7 @@ static void _isr(netdev2_t *netdev)
kw2xrf_read_dregs(dev, MKW2XDM_IRQSTS1, dregs, MKW2XDM_PHY_CTRL4 + 1);
kw2xrf_mask_irq_b(dev);
DEBUG("[kw2xrf]: CTRL1 %0x, IRQSTS1 %0x, IRQSTS2 %0x\n",
DEBUG("[kw2xrf] CTRL1 %0x, IRQSTS1 %0x, IRQSTS2 %0x\n",
dregs[MKW2XDM_PHY_CTRL1], dregs[MKW2XDM_IRQSTS1], dregs[MKW2XDM_IRQSTS2]);
switch (dregs[MKW2XDM_PHY_CTRL1] & MKW2XDM_PHY_CTRL1_XCVSEQ_MASK) {
@ -718,17 +719,17 @@ static void _isr(netdev2_t *netdev)
case XCVSEQ_IDLE:
default:
DEBUG("[kw2xrf]: undefined seq state in isr\n");
DEBUG("[kw2xrf] undefined seq state in isr\n");
break;
}
uint8_t irqsts2 = 0;
if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_PB_ERR_IRQ) {
DEBUG("[kw2xrf]: untreated PB_ERR_IRQ\n");
DEBUG("[kw2xrf] untreated PB_ERR_IRQ\n");
irqsts2 |= MKW2XDM_IRQSTS2_PB_ERR_IRQ;
}
if (dregs[MKW2XDM_IRQSTS2] & MKW2XDM_IRQSTS2_WAKE_IRQ) {
DEBUG("[kw2xrf]: untreated WAKE_IRQ\n");
DEBUG("[kw2xrf] untreated WAKE_IRQ\n");
irqsts2 |= MKW2XDM_IRQSTS2_WAKE_IRQ;
}
kw2xrf_write_dreg(dev, MKW2XDM_IRQSTS2, irqsts2);
@ -737,15 +738,15 @@ static void _isr(netdev2_t *netdev)
/* for debugging only */
kw2xrf_read_dregs(dev, MKW2XDM_IRQSTS1, dregs, MKW2XDM_IRQSTS1 + 3);
if (dregs[MKW2XDM_IRQSTS1] & 0x7f) {
DEBUG("[kw2xrf]: IRQSTS1 contains untreated IRQs: 0x%02x\n",
DEBUG("[kw2xrf] IRQSTS1 contains untreated IRQs: 0x%02x\n",
dregs[MKW2XDM_IRQSTS1]);
}
if (dregs[MKW2XDM_IRQSTS2] & 0x02) {
DEBUG("[kw2xrf]: IRQSTS2 contains untreated IRQs: 0x%02x\n",
DEBUG("[kw2xrf] IRQSTS2 contains untreated IRQs: 0x%02x\n",
dregs[MKW2XDM_IRQSTS2]);
}
if (dregs[MKW2XDM_IRQSTS3] & 0x0f) {
DEBUG("[kw2xrf]: IRQSTS3 contains untreated IRQs: 0x%02x\n",
DEBUG("[kw2xrf] IRQSTS3 contains untreated IRQs: 0x%02x\n",
dregs[MKW2XDM_IRQSTS3]);
}
}

14
drivers/kw2xrf/kw2xrf_spi.c

@ -17,6 +17,8 @@
* @author Sebastian Meiling <s@mlng.net>
* @}
*/
#include "log.h"
#include "kw2xrf.h"
#include "kw2xrf_reg.h"
#include "kw2xrf_spi.h"
@ -68,28 +70,28 @@ int kw2xrf_spi_init(kw2xrf_t *dev)
#endif
if (res != SPI_OK) {
DEBUG("[kw2xrf_spi] error: initializing SPI_%i device (code %i)\n",
SPIDEV, res);
LOG_ERROR("[kw2xrf_spi] failed to init SPI_%i device (code %i)\n",
SPIDEV, res);
return 1;
}
/* verify SPI params */
res = spi_acquire(SPIDEV, CSPIN, SPIMODE, SPICLK);
if (res == SPI_NOMODE) {
puts("[kw2xrf_spi] error: given SPI mode is not supported");
LOG_ERROR("[kw2xrf_spi] given SPI mode is not supported");
return 1;
}
else if (res == SPI_NOCLK) {
puts("[kw2xrf_spi] error: targeted clock speed is not supported");
LOG_ERROR("[kw2xrf_spi] targeted clock speed is not supported");
return 1;
}
else if (res != SPI_OK) {
puts("[kw2xrf_spi] error: unable to acquire bus with given parameters");
LOG_ERROR("[kw2xrf_spi] unable to acquire bus with given parameters");
return 1;
}
spi_release(SPIDEV);
DEBUG("[kw2xrf_spi] SPI_DEV(%i) initialized: mode: %i, clk: %i, cs_pin: %i\n",
SPIDEV, SPIMODE, SPICLK, CSPIN);
SPIDEV, SPIMODE, SPICLK, CSPIN);
return 0;
}

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