cpu/stm32_common: add support of stm32f7 to RTC driver

cpu/stm32_common/periph/rtc.c

@@ -27,7 +27,7 @@
 
 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
     defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32L1)
+    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1)
 
 /* guard file in case no RTC device was specified */
 #if RTC_NUMOF
@@ -59,7 +59,11 @@ void rtc_init(void)
 {
     /* Enable write access to RTC registers */
     periph_clk_en(APB1, RCC_APB1ENR_PWREN);
+#if defined(CPU_FAM_STM32F7)
+    PWR->CR1 |= PWR_CR1_DBP;
+#else
     PWR->CR |= PWR_CR_DBP;
+#endif
 
 #if defined(CPU_FAM_STM32L1)
     if (!(RCC->CSR & RCC_CSR_RTCEN)) {
@@ -98,7 +102,11 @@ int rtc_set_time(struct tm *time)
 {
     /* Enable write access to RTC registers */
     periph_clk_en(APB1, RCC_APB1ENR_PWREN);
+#if defined(CPU_FAM_STM32F7)
+    PWR->CR1 |= PWR_CR1_DBP;
+#else
     PWR->CR |= PWR_CR_DBP;
+#endif
 
     /* Unlock RTC write protection */
     RTC->WPR = RTC_WRITE_PROTECTION_KEY1;
@@ -152,7 +160,11 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
 {
     /* Enable write access to RTC registers */
     periph_clk_en(APB1, RCC_APB1ENR_PWREN);
+#if defined(CPU_FAM_STM32F7)
+    PWR->CR1 |= PWR_CR1_DBP;
+#else
     PWR->CR |= PWR_CR_DBP;
+#endif
 
     /* Unlock RTC write protection */
     RTC->WPR = RTC_WRITE_PROTECTION_KEY1;
@@ -319,4 +331,4 @@ static uint8_t byte2bcd(uint8_t value)
 
 #endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
           defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
-          defined(CPU_FAM_STM32L1) */
+          defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) */