cpu: add CC26x0-family
Leon M. George
8 years ago
parent
4f3a40fb74
commit
475fb6f84d
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# Define the module that is built:
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MODULE = cpu
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# Add a list of subdirectories, that should also be built:
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DIRS = periph $(RIOTCPU)/cortexm_common
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include $(RIOTBASE)/Makefile.base
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export CPU_ARCH := cortex-m3
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include $(RIOTCPU)/Makefile.include.cortexm_common
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26x0
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* @{
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*
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* @file
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* @brief implementation of the CPU initialization
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*
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* @author Leon M. George <leon@georgemail.eu>
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* @}
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*/
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#include "cpu.h"
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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}
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/**
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* @defgroup cpu_cc26x0 Texas Instruments CC26x0
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* @ingroup cpu
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* @brief Texas Instruments CC26x0 Cortex-M3 MCU specific code
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*/
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/**
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* @defgroup cpu_specific_peripheral_memory_map
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* @ingroup cpu
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*/
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/**
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* @defgroup cpu_cc26x0_definitions Texas Instruments CC26x0 definitions
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* @ingroup cpu_cc26x0
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*/
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@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26x0_definitions
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* @{
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*
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* @file
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* @brief CC26x0 MCU interrupt definitions
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*
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* @author Leon M. George <leon@georgemail.eu>
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*/
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#ifndef CC26x0_H
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#define CC26x0_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile uint8_t reg8_t;
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typedef volatile uint32_t reg32_t;
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/** @addtogroup CC26x0_cmsis CMSIS Definitions */
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/*@{*/
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/** interrupt number definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ****************************/
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ResetHandler_IRQn = -15, /**< 1 Reset Handler */
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< 3 Cortex-M3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = - 5, /**< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = - 4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = - 2, /**< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = - 1, /**< 15 Cortex-M3 System Tick Interrupt */
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/****** CC26x0 specific Interrupt Numbers *********************************/
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EDGE_DETECT_IRQN = 0, /**< 16 AON edge detect */
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I2C_IRQN = 1, /**< 17 I2C */
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RF_CPE1_IRQN = 2, /**< 18 RF Command and Packet Engine 1 */
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SPIS_IRQN = 3, /**< 19 AON SpiSplave Rx, Tx and CS */
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AON_RTC_IRQN = 4, /**< 20 AON RTC */
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UART0_IRQN = 5, /**< 21 UART0 Rx and Tx */
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AON_AUX_SWEV0_IRQN = 6, /**< 22 Sensor Controller software event 0, through AON domain*/
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SSI0_IRQN = 7, /**< 23 SSI0 Rx and Tx */
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SSI1_IRQN = 8, /**< 24 SSI1 Rx and Tx */
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RF_CPE0_IRQN = 9, /**< 25 RF Command and Packet Engine 0 */
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RF_HW_IRQN = 10, /**< 26 RF Core Hardware */
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RF_CMD_ACK_IRQN = 11, /**< 27 RF Core Command Acknowledge */
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I2S_IRQN = 12, /**< 28 I2S */
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AON_AUX_SWEV1_IRQN = 13, /**< 29 Sensor Controller software event 1, through AON domain*/
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WATCHDOG_IRQN = 14, /**< 30 Watchdog timer */
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GPTIMER_0A_IRQN = 15, /**< 31 Timer 0 subtimer A */
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GPTIMER_0B_IRQN = 16, /**< 32 Timer 0 subtimer B */
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GPTIMER_1A_IRQN = 17, /**< 33 Timer 1 subtimer A */
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GPTIMER_1B_IRQN = 18, /**< 34 Timer 1 subtimer B */
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GPTIMER_2A_IRQN = 19, /**< 35 Timer 2 subtimer A */
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GPTIMER_2B_IRQN = 20, /**< 36 Timer 2 subtimer B */
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GPTIMER_3A_IRQN = 21, /**< 37 Timer 3 subtimer A */
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GPTIMER_3B_IRQN = 22, /**< 38 Timer 3 subtimer B */
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CRYPTO_IRQN = 23, /**< 39 Crypto Core Result available */
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UDMA_IRQN = 24, /**< 40 uDMA Software */
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UDMA_ERR_IRQN = 25, /**< 41 uDMA Error */
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FLASH_CTRL_IRQN = 26, /**< 42 Flash controller */
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SW0_IRQN = 27, /**< 43 Software Event 0 */
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AUX_COMBO_IRQN = 28, /**< 44 AUX combined event, directly to MCU domain*/
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AON_PRG0_IRQN = 29, /**< 45 AON programmable 0 */
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PROG_IRQN = 30, /**< 46 Dynamic Programmable interrupt (default source: PRCM)*/
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AUX_COMPA_IRQN = 31, /**< 47 AUX Comparator A */
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AUX_ADC_IRQN = 32, /**< 48 AUX ADC IRQ */
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TRNG_IRQN = 33, /**< 49 TRNG event */
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IRQN_COUNT = (TRNG_IRQN + 1) /**< Number of peripheral IDs */
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} IRQn_Type;
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/**
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* @brief Configuration of the Cortex-M3 processor and core peripherals
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*/
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#define __MPU_PRESENT 1 /**< CC26x0 does provide a MPU */
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#define __NVIC_PRIO_BITS 3 /**< CC26x0 offers priority levels from 0..7 */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick config is used */
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#define RCOSC48M_FREQ 48000000 /**< 48 MHz */
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#define RCOSC24M_FREQ 24000000 /**< 24 MHz */
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/**
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* @brief CMSIS includes
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*/
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#include <core_cm3.h>
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/*@}*/
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define FLASH_BASE 0x00000000 /**< FLASH base address */
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/*@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC26x0_H */
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/*@}*/
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@ -0,0 +1,250 @@
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x0_definitions
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* @{
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*
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* @file
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* @brief CC26x0 AUX register definitions
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*/
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#ifndef CC26x0_AUX_H
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#define CC26x0_AUX_H
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#include <stdbool.h>
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#include "cc26x0.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* AUX_AIODIO registers
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*/
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typedef struct {
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reg32_t GPIODOUT; /**< gpio data out */
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reg32_t IOMODE; /**< input output mode */
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reg32_t GPIODIN; /**< gpio data in */
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reg32_t GPIODOUTSET; /**< gpio data out set */
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reg32_t GPIODOUTCLR; /**< gpio data out clear */
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reg32_t GPIODOUTTGL; /**< gpio data out toggle */
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reg32_t GPIODIE; /**< gpio data input enable */
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} aux_aiodio_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_AIODIO0_BASE 0x400C1000 /**< AUX_AIODIO0 base address */
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#define AUX_AIODIO1_BASE 0x400C2000 /**< AUX_AIODIO1 base address */
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/** @} */
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#define AUX_AIODIO0 ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE)) /**< AUX_AIODIO0 register bank */
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#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */
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/**
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* AUX_TDC registers
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*/
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typedef struct {
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reg32_t CTL; /**< control */
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reg32_t STAT; /**< status */
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reg32_t RESULT; /**< result */
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reg32_t SATCFG; /**< saturaion configuration */
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reg32_t TRIGSRC; /**< trigger source */
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reg32_t TRIGCNT; /**< trigger counter */
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reg32_t TRIGCNTLOAD; /**< trigger counter load */
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reg32_t TRIGCNTCFG; /**< trigger counter config */
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reg32_t PRECTL; /**< prescaler control */
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reg32_t PRECNT; /**< prescaler counter */
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} aux_tdc_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */
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/** @} */
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#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */
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/**
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* AUX_EVCTL registers
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*/
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typedef struct {
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reg32_t VECCFG0; /**< vector config 0 */
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reg32_t VECCFG1; /**< vector config 1 */
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reg32_t SCEWEVSEL; /**< sensor controller engine wait event selection */
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reg32_t EVTOAONFLAGS; /**< events to AON domain flags */
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reg32_t EVTOAONPOL; /**< events to AON domain polarity */
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reg32_t DMACTL; /**< direct memoty access control */
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reg32_t SWEVSET; /**< software event set */
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reg32_t EVSTAT0; /**< event status 0 */
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reg32_t EVSTAT1; /**< event status 1 */
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reg32_t EVTOMCUPOL; /**< event to MCU domain polarity */
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reg32_t EVTOMCUFLAGS; /**< event to MCU domain flags */
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reg32_t COMBEVTOMCUMASK; /**< combined event to MCU domain mask */
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reg32_t __reserved; /**< meh */
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reg32_t VECFLAGS; /**< vector flags */
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reg32_t EVTOMCUFLAGSCLR; /**< events to MCU domain flags clear */
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reg32_t EVTOAONFLAGSCLR; /**< events to AON domain clear */
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reg32_t VECFLAGSCLR; /**< vector flags clear */
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} aux_evtcl_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */
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/** @} */
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#define AUX_EVCTL ((aux_evctl_regs_t *) (AUX_EVCTL_BASE)) /**< AUX_EVCTL register bank */
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/**
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* AUX_WUC registers
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*/
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typedef struct {
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reg32_t MODCLKEN0; /**< module clock enable */
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reg32_t PWROFFREQ; /**< power off request */
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reg32_t PWRDWNREQ; /**< power down request */
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reg32_t PWRDWNACK; /**< power down acknowledgement */
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reg32_t CLKLFREQ; /**< low frequency clock request */
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reg32_t CLKLFACK; /**< low frequency clock acknowledgement */
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reg32_t __reserved1[4]; /**< meh */
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reg32_t WUEVFLAGS; /**< wake-up event flags */
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reg32_t WUEVCLR; /**< wake-up event clear */
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reg32_t ADCCLKCTL; /**< ADC clock control */
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reg32_t TDCCLKCTL; /**< TDC clock control */
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reg32_t REFCLKCTL; /**< reference clock control */
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reg32_t RTCSUBSECINC0; /**< real time counter sub second increment 0 */
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reg32_t RTCSUBSECINC1; /**< real time counter sub second increment 1 */
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reg32_t RTCSUBSECINCCTL; /**< real time counter sub second increment control */
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reg32_t MCUBUSCTL; /**< MCU bus control */
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reg32_t MCUBUSSTAT; /**< MCU bus status */
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reg32_t AONCTLSTAT; /**< AON domain control status */
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reg32_t AUXIOLATCH; /**< AUX input output latch */
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reg32_t MODCLKEN1; /**< module clock enable 1 */
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} aux_wuc_regs_t;
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/**
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* @brief AUX_WUC register values
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* @{
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*/
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/** @} */
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_WUC_BASE 0x400C6000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_WUC ((aux_wuc_regs_t *) (AUX_WUC_BASE)) /**< AUX_WUC register bank */
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/**
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* AUX_TIMER registers
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*/
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typedef struct {
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reg32_t T0CFG; /**< timer 0 config */
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reg32_t T1CFG; /**< timer 1 config */
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reg32_t T0CTL; /**< timer 0 control */
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reg32_t T0TARGET; /**< timer 0 target */
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reg32_t T1TARGET; /**< timer 1 target */
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reg32_t T1CTL; /**< timer 1 control */
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} aux_timer_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_TIMER_BASE 0x400C7000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_TIMER ((aux_timer_regs_t *) (AUX_TIMER_BASE)) /**< AUX_TIMER register bank */
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/**
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* AUX_SMPH registers
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*/
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typedef struct {
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reg32_t SMPH0; /**< semaphore 0 */
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reg32_t SMPH1; /**< semaphore 1 */
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reg32_t SMPH2; /**< semaphore 2 */
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reg32_t SMPH3; /**< semaphore 3 */
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reg32_t SMPH4; /**< semaphore 4 */
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reg32_t SMPH5; /**< semaphore 5 */
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reg32_t SMPH6; /**< semaphore 6 */
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reg32_t SMPH7; /**< semaphore 7 */
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reg32_t AUTOTAKE; /**< sticky request for single semaphore */
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} aux_smph_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */
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/* @} */
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#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */
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/**
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* AUX_ANAIF registers
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*/
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typedef struct {
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reg32_t __reserved[4]; /**< meh */
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reg32_t ADCCTL; /**< ADC control */
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reg32_t ADCFIFOSTAT; /**< ADC fifo status */
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reg32_t ADCFIFO; /**< ADC fifo */
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reg32_t ADCTRIG; /**< ADC trigger */
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reg32_t ISRCCTL; /**< current source control */
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} aux_anaif_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */
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/** @} */
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#define AUX_ANAIF ((aux_anaif_regs_t *) (AUX_ANAIF_BASE)) /**< AUX_ANAIF register bank */
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/**
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* ADI_4_AUX registers
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*/
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typedef struct {
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reg8_t MUX0; /**< multiplexer 0 */
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reg8_t MUX1; /**< multiplexer 1 */
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reg8_t MUX2; /**< multiplexer 2 */
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reg8_t MUX3; /**< multiplexer 3 */
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reg8_t ISRC; /**< current source */
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reg8_t COMP; /**< comparator */
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reg8_t MUX4; /**< multiplexer 4 */
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reg8_t ADC0; /**< ADC control 0 */
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reg8_t ADC1; /**< ADC control 1 */
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reg8_t ADCREF0; /**< ADC reference 0 */
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reg8_t ADCREF1; /**< ADC reference 1 */
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} adi_4_aux_regs_t;
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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#define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */
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/** @} */
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#define ADI_4_AUX ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE)) /**< ADI_4_AUX register bank */
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#define ADDI_SEM AUX_SMPH->SMPH0 /**< the semamphore used for ADDI */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26x0_AUX_H */
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/** @}*/
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@ -0,0 +1,70 @@
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x0_definitions
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* @{
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*
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* @file
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* @brief CC26x0 CCFG register definitions
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*/
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#ifndef CC26x0_CCFG_H
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#define CC26x0_CCFG_H
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#include <cc26x0.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
|
||||
#define CCFG_BASE 0x50003000 /**< base address of CCFG memory */
|
||||
/*@}*/
|
||||
|
||||
/* TODO not present in datasheet but explained in cc26x0ware-lds */
|
||||
#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 /**< CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM */
|
||||
|
||||
/**
|
||||
* CCFG registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t EXT_LF_CLK; /**< extern LF clock config */
|
||||
reg32_t MODE_CONF_1; /**< mode config 1 */
|
||||
reg32_t SIZE_AND_DIS_FLAGS; /**< CCFG size and disable flags */
|
||||
reg32_t MODE_CONF; /**< mmode config 0 */
|
||||
reg32_t VOLT_LOAD_0; /**< voltage load 0 */
|
||||
reg32_t VOLT_LOAD_1; /**< voltage load 1 */
|
||||
reg32_t RTC_OFFSET; /**< RTC offset */
|
||||
reg32_t FREQ_OFFSET; /**< frequency offset */
|
||||
reg32_t IEEE_MAC_0; /**< IEEE MAC address 0 */
|
||||
reg32_t IEEE_MAC_1; /**< IEEE MAC address 1 */
|
||||
reg32_t IEEE_BLE_0; /**< IEEE BLE address 0 */
|
||||
reg32_t IEEE_BLE_1; /**< IEEE BLE address 1 */
|
||||
reg32_t BL_CONFIG; /**< bootloader config */
|
||||
reg32_t ERASE_CONF; /**< erase config */
|
||||
reg32_t CCFG_TI_OPTIONS; /**< TI options */
|
||||
reg32_t CCFG_TAP_DAP_0; /**< test access points enable 0 */
|
||||
reg32_t CCFG_TAP_DAP_1; /**< test access points enable 1 */
|
||||
reg32_t IMAGE_VALID_CONF; /**< image valid */
|
||||
reg32_t CCFG_PROT_31_0; /**< protect sectors 0-31 */
|
||||
reg32_t CCFG_PROT_63_32; /**< protect sectors 32-63 */
|
||||
reg32_t CCFG_PROT_95_64; /**< protect sectors 64-95 */
|
||||
reg32_t CCFG_PROT_127_96; /**< protect sectors 96-127 */
|
||||
} ccfg_regs_t;
|
||||
|
||||
#define CCFG ((ccfg_regs_t *) (CCFG_BASE + 0xFA8)) /**< CCFG register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_CCFG_H */
|
||||
|
||||
/*@}*/
|
||||
@ -0,0 +1,139 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC26x0 FCFG register definitions
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_FCFG_H
|
||||
#define CC26x0_FCFG_H
|
||||
|
||||
#include <cc26x0.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* FCFG registers
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t __reserved1[0xA0]; /**< meh */
|
||||
/* TODO does it pad here? */
|
||||
reg32_t MISC_CONF_1; /**< misc config */
|
||||
reg32_t __reserved2[8]; /**< meh */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV5; /**< config of RF frontend in divide-by-5 mode */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV6; /**< config of RF frontend in divide-by-6 mode */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV10; /**< config of RF frontend in divide-by-10 mode */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV12; /**< config of RF frontend in divide-by-12 mode */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV15; /**< config of RF frontend in divide-by-15 mode */
|
||||
reg32_t CONFIG_RF_FRONTEND_DIV30; /**< config of RF frontend in divide-by-30 mode */
|
||||
reg32_t CONFIG_SYNTH_DIV5; /**< config of synthesizer in divide-by-5-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV6; /**< config of synthesizer in divide-by-5-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV10; /**< config of synthesizer in divide-by-10-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV12; /**< config of synthesizer in divide-by-12-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV15; /**< config of synthesizer in divide-by-15-mode */
|
||||
reg32_t CONFIG_SYNTH_DIV30; /**< config of synthesizer in divide-by-30-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV5; /**< config of IFADC in divide-by-5-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV6; /**< config of IFADC in divide-by-6-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV10; /**< config of IFADC in divide-by-10-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV12; /**< config of IFADC in divide-by-12-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV15; /**< config of IFADC in divide-by-15-mode */
|
||||
reg32_t CONFIG_MISC_ADC_DIV30; /**< config of IFADC in divide-by-30-mode */
|
||||
reg32_t __reserved3[3]; /**< meh */
|
||||
reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */
|
||||
reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */
|
||||
reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */
|
||||
reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */
|
||||
reg32_t __reserved4[4]; /**< meh */
|
||||
reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< shadow of JTAG_TAP::EFUSE::BIAS_LDO_TIM.* */
|
||||
reg32_t SHDW_ANA_TRIM; /**< shadow of JTAG_TAP::EFUSE::ANA_TIM.* */
|
||||
reg32_t __reserved5[9]; /**< meh */
|
||||
reg32_t FLASH_NUMBER; /**< number of manufactoring lot that produced this unit */
|
||||
reg32_t FLASH_COORDINATE; /**< X and Y coordinates of this unit on the wafer */
|
||||
reg32_t FLASH_E_P; /**< flash erase and program setup time */
|
||||
reg32_t FLASH_C_E_P_R; /**< flash compaction, execute, program, and read */
|
||||
reg32_t FLASH_P_R_PV; /**< flash program, read, and program verify */
|
||||
reg32_t FLASH_EH_SEQ; /**< flash erase hold and sequence */
|
||||
reg32_t FLASH_VHV_E; /**< flash VHV erase */
|
||||
reg32_t FLASH_PP; /**< flash program pulse */
|
||||
reg32_t FLASH_PROG_EP; /**< flash program and erase pulse */
|
||||
reg32_t FLASH_ERA_PW; /**< flash erase pulse width */
|
||||
reg32_t FLASH_VHV; /**< flash VHV */
|
||||
reg32_t FLASH_VHV_PV; /**< flash VHV program verify */
|
||||
reg32_t FLASH_V; /**< flash voltages */
|
||||
reg32_t __reserved6[0x3E]; /**< meh */
|
||||
reg32_t USER_ID; /**< user identification */
|
||||
reg32_t __reserved7[6]; /**< meh */
|
||||
reg32_t FLASH_OTP_DATA3; /**< flash OTP data 3 */
|
||||
reg32_t ANA2_TRIM; /**< misc analog trim */
|
||||
reg32_t LDO_TRIM; /**< LDO trim */
|
||||
reg32_t __reserved8[0xB]; /**< meh */
|
||||
reg32_t MAC_BLE_0; /**< MAC BLE address 0 */
|
||||
reg32_t MAC_BLE_1; /**< MAC BLE address 1 */
|
||||
reg32_t MAC_15_4_0; /**< MAC IEEE 820.15.4 address 0 */
|
||||
reg32_t MAC_15_4_1; /**< MAC IEEE 820.15.4 address 1 */
|
||||
reg32_t __reserved9[4]; /**< meh */
|
||||
reg32_t FLASH_OTP_DATA4; /**< flash OTP data 4 */
|
||||
reg32_t MISC_TRIM; /**< misc trim parameters */
|
||||
reg32_t RCOSC_HF_TEMPCOMP; /**< RFOSC HF temperature compensation */
|
||||
reg32_t __reserved10; /**< meh */
|
||||
reg32_t ICEPICK_DEVICE_ID; /**< IcePick device identification */
|
||||
reg32_t FCFG1_REVISION; /**< FCFG1 revision */
|
||||
reg32_t MISC_OTP_DATA; /**< misc OTP data */
|
||||
reg32_t __reserved11[8]; /**< meh */
|
||||
reg32_t IOCONF; /**< IO config */
|
||||
reg32_t __reserved12; /**< meh */
|
||||
reg32_t CONFIG_IF_ADC; /**< config of IF_ADC */
|
||||
reg32_t CONFIG_OSC_TOP; /**< config of OSC */
|
||||
reg32_t CONFIG_RF_FRONTEND; /**< config of RF frontend in dividy-by-2-mode */
|
||||
reg32_t CONFIG_SYNTH; /**< config of synthesizer in dividy-by-2-mode */
|
||||
reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */
|
||||
reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */
|
||||
reg32_t __reserved13; /**< meh */
|
||||
reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */
|
||||
reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< AUX_ADC reference trim and offset of external reference mode */
|
||||
reg32_t AMPCOMP_TH1; /**< amplitude compensation threshold 1 */
|
||||
reg32_t AMPCOMP_TH2; /**< amplitude compensation threshold 2 */
|
||||
reg32_t AMPCOMP_CTRL1; /**< amplitude compensation control */
|
||||
reg32_t ANABYPASS_VALUE2; /**< analog bypass value for OSC */
|
||||
reg32_t CONFIG_MISC_ADC; /**< config of IFADC in divide-by-2-mode */
|
||||
reg32_t __reserved14; /**< meh */
|
||||
reg32_t VOLT_TRIM; /**< voltage trim */
|
||||
reg32_t OSC_CONF; /**< OSC configuration */
|
||||
reg32_t __reserved15; /**< meh */
|
||||
reg32_t CAP_TRIM; /**< capacitor trim (it says 'capasitor' in the manual - if you know what that is ;-) */
|
||||
reg32_t MISC_OTP_DATA_1; /**< misc OSC control */
|
||||
reg32_t PWD_CURR_20C; /**< power down current control 20C */
|
||||
reg32_t PWD_CURR_35C; /**< power down current control 35C */
|
||||
reg32_t PWD_CURR_50C; /**< power down current control 50C */
|
||||
reg32_t PWD_CURR_65C; /**< power down current control 65C */
|
||||
reg32_t PWD_CURR_80C; /**< power down current control 80C */
|
||||
reg32_t PWD_CURR_95C; /**< power down current control 95C */
|
||||
reg32_t PWD_CURR_110C; /**< power down current control 110C */
|
||||
reg32_t PWD_CURR_125C; /**< power down current control 125C */
|
||||
} fcfg_regs_t;
|
||||
|
||||
#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_FCFG_H */
|
||||
|
||||
/*@}*/
|
||||
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Driver for the cc26x0 GPIO controller
|
||||
*
|
||||
* @author Leon George <leon@georgemail.eu>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_GPIO_H
|
||||
#define CC26x0_GPIO_H
|
||||
|
||||
#include "cc26x0.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_BASE (0x40022000) /**< GPIO base address */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* GPIO registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t DOUT_FRAG[8]; /**< w the first bit of each byte corresponds to one bit of DOUT */
|
||||
reg32_t __reserved1[24]; /**< unused */
|
||||
reg32_t DOUT; /**< r/w state of the output */
|
||||
reg32_t __reserved2[3]; /**< unused */
|
||||
reg32_t DOUTSET; /**< w1s set output */
|
||||
reg32_t __reserved3[3]; /**< unused */
|
||||
reg32_t DOUTCLR; /**< w1c clear output */
|
||||
reg32_t __reserved4[3]; /**< unused */
|
||||
reg32_t DOUTTGL; /**< r/w toggle output */
|
||||
reg32_t __reserved5[3]; /**< unused */
|
||||
reg32_t DIN; /**< r input status */
|
||||
reg32_t __reserved6[3]; /**< unused */
|
||||
reg32_t DOE; /**< r/w enable output */
|
||||
reg32_t __reserved7[3]; /**< unused */
|
||||
reg32_t EVFLAGS; /**< r/w1c indicates an input event */
|
||||
} gpio_regs_t;
|
||||
|
||||
#define GPIO ((gpio_regs_t *) (GPIO_BASE)) /**< GPIO register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_GPIO_H */
|
||||
|
||||
/** @} */
|
||||
@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief definitions for the CC26x0 GPT moduls
|
||||
*
|
||||
* @author Leon George <leon@georgemail.eu>
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_GPT_H
|
||||
#define CC26x0_GPT_H
|
||||
|
||||
#include "cc26x0.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPT registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t CFG; /**< config */
|
||||
reg32_t TAMR; /**< timer A mode */
|
||||
reg32_t TBMR; /**< timer B mode */
|
||||
reg32_t CTL; /**< control */
|
||||
reg32_t SYNC; /**< sync timers */
|
||||
reg32_t __reserved1; /**< unused */
|
||||
reg32_t IMR; /**< interrupt mask register */
|
||||
reg32_t RIS; /**< raw interrupt status */
|
||||
reg32_t MIS; /**< masked interrupt status */
|
||||
reg32_t ICLR; /**< interrupt clear */
|
||||
reg32_t TAILR; /**< timer A interval load register */
|
||||
reg32_t TBILR; /**< timer B interval load register */
|
||||
reg32_t TAMATCHR; /**< timer A match register */
|
||||
reg32_t TBMATCHR; /**< timer B match register */
|
||||
reg32_t TAPR; /**< timer A pre-scale */
|
||||
reg32_t TBPR; /**< timer B pre-scale */
|
||||
reg32_t TAPMR; /**< timer A pre-scale match register */
|
||||
reg32_t TBPMR; /**< timer B pre-scale match register */
|
||||
reg32_t TAR; /**< timer A register */
|
||||
reg32_t TBR; /**< timer B register */
|
||||
reg32_t TAV; /**< timer A value */
|
||||
reg32_t TBV; /**< timer B value */
|
||||
reg32_t RTCPD; /**< config */
|
||||
reg32_t TAPS; /**< config */
|
||||
reg32_t TBPS; /**< config */
|
||||
reg32_t TAPV; /**< config */
|
||||
reg32_t TBPV; /**< config */
|
||||
reg32_t DMAEV; /**< config */
|
||||
reg32_t __reserved2[976]; /**< config */
|
||||
reg32_t VERSION; /**< config */
|
||||
reg32_t ANDCCP; /**< config */
|
||||
} gpt_reg_t;
|
||||
|
||||
/**
|
||||
* @brief GPT base register addresses
|
||||
* @{
|
||||
*/
|
||||
#define GPT0_BASE (0x40010000) /**< GTP0 base address */
|
||||
#define GPT1_BASE (0x40011000) /**< GTP1 base address */
|
||||
#define GPT2_BASE (0x40012000) /**< GTP2 base address */
|
||||
#define GPT3_BASE (0x40013000) /**< GTP3 base address */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief GPT instances
|
||||
* @{
|
||||
*/
|
||||
#define GPT0 ((gpt_reg_t *) (GPT0_BASE))
|
||||
#define GPT1 ((gpt_reg_t *) (GPT1_BASE))
|
||||
#define GPT2 ((gpt_reg_t *) (GPT2_BASE))
|
||||
#define GPT3 ((gpt_reg_t *) (GPT3_BASE))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief GPT register values
|
||||
* @{
|
||||
*/
|
||||
#define GPT_CFG_32T 0
|
||||
#define GPT_CFG_32RTC 1
|
||||
#define GPT_CFG_16T 4
|
||||
|
||||
#define GPT_TXMR_TXMR_ONE_SHOT 0x00000001
|
||||
#define GPT_TXMR_TXMR_PERIODIC 0x00000002
|
||||
#define GPT_TXMR_TXMR_CAPTURE 0x00000003
|
||||
#define GPT_TXMR_TXCM_EDGECNT 0x00000000
|
||||
#define GPT_TXMR_TXCM_EDGETIME 0x00000004
|
||||
#define GPT_TXMR_TXAMS_CAPTCOMP 0x00000000
|
||||
#define GPT_TXMR_TXAMS_PWM 0x00000008
|
||||
#define GPT_TXMR_TXCDIR_DOWN 0x00000000
|
||||
#define GPT_TXMR_TXCDIR_UP 0x00000010 /* starts from 0 */
|
||||
#define GPT_TXMR_TXMIE 0x00000020 /* match interrupt */
|
||||
#define GPT_TXMR_TXWOT 0x00000040 /* wait on trigger from daisy */
|
||||
#define GPT_TXMR_TXSNAPS 0x00000080
|
||||
#define GPT_TXMR_TXILD_CLOCK 0x00000000 /* interrupt loac: update TXPR or TXR */
|
||||
#define GPT_TXMR_TXILD_TIMEOUT 0x00000100
|
||||
#define GPT_TXMR_TXPWMIE 0x00000200
|
||||
#define GPT_TXMR_TXMRSU 0x00000400
|
||||
#define GPT_TXMR_TXPLO 0x00000800
|
||||
#define GPT_TXMR_TXCIN 0x00001000
|
||||
#define GPT_TXMR_TCACT_DIS 0x00000000
|
||||
#define GPT_TXMR_TCACT_TGL_TO 0x00002000
|
||||
#define GPT_TXMR_TCACT_CLR_TO 0x00004000
|
||||
#define GPT_TXMR_TCACT_SET_TO 0x00006000
|
||||
#define GPT_TXMR_TCACT_SET_NOW_TGL_TO 0x00008000
|
||||
#define GPT_TXMR_TCACT_CLR_NOW_TGL_TO 0x0000a000
|
||||
#define GPT_TXMR_TCACT_SET_NOW_CLR_TO 0x0000c000
|
||||
#define GPT_TXMR_TCACT_CLR_NOW_SET_TO 0x0000e000
|
||||
|
||||
#define GPT_CTL_TAEN 0x00000001
|
||||
#define GPT_CTL_TASTALL 0x00000002
|
||||
#define GPT_CTL_TAEVENT_POS 0x00000000
|
||||
#define GPT_CTL_TAEVENT_NEG 0x00000004
|
||||
#define GPT_CTL_TAEVENT_BOTH 0x0000000c
|
||||
#define GPT_CTL_RTCEN 0x00000010
|
||||
#define GPT_CTL_TAPWML_INV 0x00000040
|
||||
#define GPT_CTL_TBEN 0x00000100 /* still need capture CFG */
|
||||
#define GPT_CTL_TBSTALL 0x00000200
|
||||
#define GPT_CTL_TBEVENT_POS 0x00000000
|
||||
#define GPT_CTL_TBEVENT_NEG 0x00000400
|
||||
#define GPT_CTL_TBEVENT_BOTH 0x00000c00
|
||||
#define GPT_CTL_TBPWML_INV 0x00004000
|
||||
|
||||
#define GPT_SYNC_SYNC1_A 0x00000001
|
||||
#define GPT_SYNC_SYNC1_B 0x00000002
|
||||
#define GPT_SYNC_SYNC2_A 0x00000004
|
||||
#define GPT_SYNC_SYNC2_B 0x00000008
|
||||
#define GPT_SYNC_SYNC3_A 0x00000010
|
||||
#define GPT_SYNC_SYNC3_B 0x00000020
|
||||
#define GPT_SYNC_SYNC4_A 0x00000040
|
||||
#define GPT_SYNC_SYNC4_B 0x00000080
|
||||
|
||||
#define GPT_IMR_TATOIM 0x00000001
|
||||
#define GPT_IMR_CAMIM 0x00000002
|
||||
#define GPT_IMR_CAEIM 0x00000004
|
||||
#define GPT_IMR_RTCIM 0x00000008
|
||||
#define GPT_IMR_TAMIM 0x00000010
|
||||
#define GPT_IMR_DMAAIM 0x00000020
|
||||
#define GPT_IMR_TBTOIM 0x00000100
|
||||
#define GPT_IMR_CBMIM 0x00000200
|
||||
#define GPT_IMR_CBEIM 0x00000400
|
||||
#define GPT_IMR_TBMIM 0x00000800
|
||||
#define GPT_IMR_DMABIM 0x00002000
|
||||
#define GPT_IMR_WUMIS 0x00010000
|
||||
|
||||
#define GPT_RIS_TATORIS 0x00000001
|
||||
#define GPT_RIS_CAMRIS 0x00000002
|
||||
#define GPT_RIS_CAERIS 0x00000004
|
||||
#define GPT_RIS_RTCRIS 0x00000008
|
||||
#define GPT_RIS_TAMRIS 0x00000010
|
||||
#define GPT_RIS_TBTORIS 0x00000100
|
||||
#define GPT_RIS_CBMRIS 0x00000200
|
||||
#define GPT_RIS_CBERIS 0x00000400
|
||||
#define GPT_RIS_TBMRIS 0x00000800
|
||||
#define GPT_RIS_DMARIS 0x00002000
|
||||
#define GPT_RIS_WURIS 0x00010000
|
||||
|
||||
#define GPT_MIS_TATOMIS 0x00000001
|
||||
#define GPT_MIS_CAMMIS 0x00000002
|
||||
#define GPT_MIS_CAEMIS 0x00000004
|
||||
#define GPT_MIS_RTCMIS 0x00000008
|
||||
#define GPT_MIS_TAMMIS 0x00000010
|
||||
#define GPT_MIS_TBTOMIS 0x00000100
|
||||
#define GPT_MIS_CBMMIS 0x00000200
|
||||
#define GPT_MIS_CBEMIS 0x00000400
|
||||
#define GPT_MIS_TBMMIS 0x00000800
|
||||
#define GPT_MIS_DMAMIS 0x00002000
|
||||
#define GPT_MIS_WUMIS 0x00010000
|
||||
|
||||
#define GPT_ICLR_TATOCINT 0x00000001
|
||||
#define GPT_ICLR_CAMCINT 0x00000002
|
||||
#define GPT_ICLR_CAECINT 0x00000004
|
||||
#define GPT_ICLR_RTCCINT 0x00000008
|
||||
#define GPT_ICLR_TAMCINT 0x00000010
|
||||
#define GPT_ICLR_TBTOCINT 0x00000100
|
||||
#define GPT_ICLR_CBMCINT 0x00000200
|
||||
#define GPT_ICLR_CBECINT 0x00000400
|
||||
#define GPT_ICLR_TBMCINT 0x00000800
|
||||
#define GPT_ICLR_DMACINT 0x00002000
|
||||
#define GPT_ICLR_WUCINT 0x00010000
|
||||
|
||||
#define GPT_DMAEV_TATODMAEN 0x00000001
|
||||
#define GPT_DMAEV_CAMDMAEN 0x00000002
|
||||
#define GPT_DMAEV_CAEDMAEN 0x00000004
|
||||
#define GPT_DMAEV_RTCDMAEN 0x00000008
|
||||
#define GPT_DMAEV_TAMDMAEN 0x00000010
|
||||
#define GPT_DMAEV_TBTODMAEN 0x00000100
|
||||
#define GPT_DMAEV_CBMDMAEN 0x00000200
|
||||
#define GPT_DMAEV_CBEDMAEN 0x00000400
|
||||
#define GPT_DMAEV_TBMDMAEN 0x00000800
|
||||
/** @} */
|
||||
|
||||
#define GPT_NUMOF 4 /**< GPT count */
|
||||
#define NUM_CHANNELS_PER_GPT 1 /**< GPT channel count */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_GPT_H */
|
||||
/** @} */
|
||||
@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_i2c_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC26x0 MCU I/O register definitions
|
||||
*
|
||||
* @author Leon George <leon@georgemail.eu>
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_I2C_H
|
||||
#define CC26x0_I2C_H
|
||||
|
||||
#include "cc26x0.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* I2C registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t SOAR; /**< slave own address */
|
||||
union {
|
||||
reg32_t SSTAT; /**< slave status */
|
||||
reg32_t SCTL; /**< slave control */
|
||||
};
|
||||
reg32_t SDR; /**< slave data */
|
||||
reg32_t SIMR; /**< slave interrupt mask */
|
||||
reg32_t SRIS; /**< slave raw interrupt status */
|
||||
reg32_t SMIS; /**< slave masked interrupt status */
|
||||
reg32_t SICR; /**< slave interrupt clear */
|
||||
reg32_t __reserved[0x1F9]; /**< meh */
|
||||
reg32_t MSA; /**< master slave address */
|
||||
union {
|
||||
reg32_t MSTAT; /**< master status */
|
||||
reg32_t MCTRL; /**< master control */
|
||||
};
|
||||
reg32_t MDR; /**< master data */
|
||||
reg32_t MTPR; /**< master timer period */
|
||||
reg32_t MIMR; /**< master interrupt mask */
|
||||
reg32_t MRIS; /**< master raw interrupt status */
|
||||
reg32_t MMIS; /**< master masked interrupt statues */
|
||||
reg32_t MICR; /**< master interrupt clear */
|
||||
reg32_t MCR; /**< master configuration */
|
||||
} i2c_regs_t;
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define I2C_BASE (PERIPH_BASE + 0x2000) /**< I2C base address */
|
||||
/** @} */
|
||||
|
||||
#define I2C ((i2c_regs_t *) (I2C_BASE)) /**< I2C register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_I2C_H */
|
||||
|
||||
/*@}*/
|
||||
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_ioc_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC26x0 MCU I/O register definitions
|
||||
*
|
||||
* @author Leon George <leon@georgemail.eu>
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_IOC_H
|
||||
#define CC26x0_IOC_H
|
||||
|
||||
#include "cc26x0.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define MCU_IOC_BASE (0x40081000) /**< IOC (MCU) base address */
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @brief obtain IOCFG-register for a DIO
|
||||
*
|
||||
* @param[in] dio_num DIO number (0-31)
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t CFG[32]; /**< config */
|
||||
} cc26x0_ioc_regs_t;
|
||||
|
||||
#define IOC ((cc26x0_ioc_regs_t *)(MCU_IOC_BASE)) /**< IOC register banks */
|
||||
|
||||
/**
|
||||
* @name values for IOCFG
|
||||
* @{
|
||||
*/
|
||||
#define IOCFG_PORTID_GPIO 0x00000000 /**< GPIO */
|
||||
#define IOCFG_PORTID_AON_SCS 0x00000001 /**< AON SPI-S SCS */
|
||||
#define IOCFG_PORTID_AON_SCK 0x00000002 /**< AON SPI-S SCK */
|
||||
#define IOCFG_PORTID_AON_SDI 0x00000003 /**< AON SPI-S SDI */
|
||||
#define IOCFG_PORTID_AON_SDO 0x00000004 /**< AON SPI-S SDO */
|
||||
#define IOCFG_PORTID_AON_CLK32K 0x00000007 /**< AON external 32kHz clock */
|
||||
#define IOCFG_PORTID_AUX_IO 0x00000008 /**< AUX IO */
|
||||
#define IOCFG_PORTID_SSI0_RX 0x00000009 /**< SSI0 receive */
|
||||
#define IOCFG_PORTID_SSI0_TX 0x0000000A /**< SSI0 transmit */
|
||||
#define IOCFG_PORTID_SSI0_FSS 0x0000000B /**< SSI0 FSS */
|
||||
#define IOCFG_PORTID_SSI0_CLK 0x0000000C /**< SSI0 clock */
|
||||
#define IOCFG_PORTID_I2C_MSSDA 0x0000000D /**< I2C data */
|
||||
#define IOCFG_PORTID_I2C_MSSCL 0x0000000E /**< I2C clock */
|
||||
#define IOCFG_PORTID_UART0_RX 0x0000000F /**< UART0 receive */
|
||||
#define IOCFG_PORTID_UART0_TX 0x00000010 /**< UART0 transmit */
|
||||
#define IOCFG_PORTID_UART0_CTS 0x00000011 /**< UART0 clear to send */
|
||||
#define IOCFG_PORTID_UART0_RTS 0x00000012 /**< UART0 request to send */
|
||||
#define IOCFG_PORTID_PORT_EVT0 0x00000017 /**< PORT EVENT 0 */
|
||||
#define IOCFG_PORTID_PORT_EVT1 0x00000018 /**< PORT EVENT 1 */
|
||||
#define IOCFG_PORTID_PORT_EVT2 0x00000019 /**< PORT EVENT 2 */
|
||||
#define IOCFG_PORTID_PORT_EVT3 0x0000001A /**< PORT EVENT 3 */
|
||||
#define IOCFG_PORTID_PORT_EVT4 0x0000001B /**< PORT EVENT 4 */
|
||||
#define IOCFG_PORTID_PORT_EVT5 0x0000001C /**< PORT EVENT 5 */
|
||||
#define IOCFG_PORTID_PORT_EVT6 0x0000001D /**< PORT EVENT 6 */
|
||||
#define IOCFG_PORTID_PORT_EVT7 0x0000001E /**< PORT EVENT 7 */
|
||||
#define IOCFG_PORTID_SWV 0x00000020 /**< serial wire viewer */
|
||||
#define IOCFG_PORTID_SSI1_RX 0x00000021 /**< SSI1 receive */
|
||||
#define IOCFG_PORTID_SSI1_TX 0x00000022 /**< SSI1 transmit */
|
||||
#define IOCFG_PORTID_SSI1_FSS 0x00000023 /**< SSI1 FSS */
|
||||
#define IOCFG_PORTID_SSI1_CLK 0x00000024 /**< SSI1 clock */
|
||||
#define IOCFG_PORTID_I2S_AD0 0x00000025 /**< I2S data 0 */
|
||||
#define IOCFG_PORTID_I2S_AD1 0x00000026 /**< I2S data 1 */
|
||||
#define IOCFG_PORTID_I2S_WCLK 0x00000027 /**< I2S frame/word clock */
|
||||
#define IOCFG_PORTID_I2S_BCLK 0x00000028 /**< I2S bit clock */
|
||||
#define IOCFG_PORTID_I2S_MCLK 0x00000029 /**< I2S master clock 2 */
|
||||
#define IOCFG_PORTID_RFC_TRC 0x0000002E /**< RF core trace */
|
||||
#define IOCFG_PORTID_RFC_GPO0 0x0000002F /**< RC core data out 0 */
|
||||
#define IOCFG_PORTID_RFC_GPO1 0x00000030 /**< RC core data out 1 */
|
||||
#define IOCFG_PORTID_RFC_GPO2 0x00000031 /**< RC core data out 2 */
|
||||
#define IOCFG_PORTID_RFC_GPO3 0x00000032 /**< RC core data out 3 */
|
||||
#define IOCFG_PORTID_RFC_GPI0 0x00000033 /**< RC core data in 0 */
|
||||
#define IOCFG_PORTID_RFC_GPI1 0x00000034 /**< RC core data in 1 */
|
||||
#define IOCFG_PORTID_RFC_SMI_DL_OUT 0x00000035 /**< RF core SMI data link out */
|
||||
#define IOCFG_PORTID_RFC_SMI_DL_IN 0x00000036 /**< RF core SMI data link in */
|
||||
#define IOCFG_PORTID_RFC_SMI_CMD_OUT 0x00000037 /**< RF core SMI command link out */
|
||||
#define IOCFG_PORTID_RFC_SMI_CMD_IN 0x00000038 /**< RF core SMI command link in */
|
||||
|
||||
#define IOCFG_IOSTR_AUTO 0x00000000 /**< automatic drive strength (2/4/8 mA @ VVDS) */
|
||||
#define IOCFG_IOSTR_MAX 0x00000300 /**< maximum drive strength (2/4/8 mA @ 1.8V) */
|
||||
#define IOCFG_IOSTR_MED 0x00000200 /**< medium drive strength (2/4/8 mA @ 2.5V) */
|
||||
#define IOCFG_IOSTR_MIN 0x00000100 /**< minimum drive strength (2/4/8 mA @ 3.3V) */
|
||||
|
||||
#define IOCFG_IOCURR_2MA 0x00000000 /**< 2mA drive strength */
|
||||
#define IOCFG_IOCURR_4MA 0x00000400 /**< 4mA drive strength */
|
||||
#define IOCFG_IOCURR_8MA 0x00000800 /**< 4 or 8mA drive strength */
|
||||
#define IOCFG_IOCURR_16MA 0x00000C00 /**< Up to 16mA drive strength */
|
||||
|
||||
#define IOCFG_SLEW_RED 0x00001000 /**< reduced slew rate */
|
||||
|
||||
#define IOCFG_PULLCTL_OFF 0x00006000 /**< no IO pull */
|
||||
#define IOCFG_PULLCTL_UP 0x00004000 /**< pull up */
|
||||
#define IOCFG_PULLCTL_DOWN 0x00002000 /**< pull down */
|
||||
|
||||
#define IOCFG_EDGEDET_FALLING 0x00010000 /**< edge detection on falling edge */
|
||||
#define IOCFG_EDGEDET_RISING 0x00020000 /**< edge detection on rising edge */
|
||||
#define IOCFG_EDGEDET_BOTH 0x00030000 /**< edge detection on both edges */
|
||||
#define IOCFG_EDGEIRQ_ENABLE 0x00040000 /**< enable interrupt on edge detect */
|
||||
|
||||
/* n/a when port_id is AON or AUX */
|
||||
#define IOCFG_IOMODE_INV 0x01000000 /**< inverted I/O */
|
||||
#define IOCFG_IOMODE_OPEN_DRAIN 0x04000000 /**< open drain */
|
||||
#define IOCFG_IOMODE_OPEN_SRC 0x06000000 /**< open source */
|
||||
|
||||
/* both enable waking up when port_id is AON or AUX */
|
||||
#define IOCFG_WUCFG_LOW 0x10000000
|
||||
#define IOCFG_WUCFG_HIGH 0x18000000
|
||||
|
||||
/* ignored if port_id is AUX */
|
||||
#define IOCFG_INPUT_ENABLE 0x20000000
|
||||
|
||||
#define IOCFG_HYST_ENABLE 0x40000000
|
||||
/** @} */
|
||||
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define AON_IOC_BASE (PERIPH_BASE + 0x94000) /**< always-on-IOC base address */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* AON registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t IOSTRMIN; /**< IO drive strength minimum */
|
||||
reg32_t IOSTRMED; /**< IO drive strength medium */
|
||||
reg32_t IOSTRMAX; /**< IO drive strength maximum */
|
||||
reg32_t IOCLATCH; /**< IO latch control */
|
||||
reg32_t CLK32KCTL; /**< SCLK_LF external output control */
|
||||
} aon_regs_t;
|
||||
|
||||
#define AON ((aon_regs_t *) (AON_IOC_BASE)) /**< AON register bank */
|
||||
|
||||
#define IOCLATCH_EN 0x00000001 /**< IO controlled by GPIO or peripheral; kept in AON otherwise */
|
||||
|
||||
#define CLK32KCTL_OEN 0x00000001 /**< don't output SCLK_LF on DIOs with PORT_ID AON_CLK32K */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_IOC_H */
|
||||
|
||||
/*@}*/
|
||||
@ -0,0 +1,322 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_cc26x0_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC26x0 PRCM register definitions
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_PRCM_H
|
||||
#define CC26x0_PRCM_H
|
||||
|
||||
#include <cc26x0.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* DDI_0_OSC registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t CTL0; /**< control 0 */
|
||||
reg32_t CTL1; /**< control 1 */
|
||||
reg32_t RADCEXTCFG; /**< RADC external config */
|
||||
reg32_t AMPCOMPCTL; /**< amplitude compensation control */
|
||||
reg32_t AMPCOMPTH1; /**< amplitude compensation threshold 1 */
|
||||
reg32_t AMPCOMPTH2; /**< amplitude compensation threshold 2 */
|
||||
reg32_t ANABYPASSVAL1; /**< analog bypass values 1 */
|
||||
reg32_t ANABYPASSVAL2; /**< analog bypass values 2 */
|
||||
reg32_t ATESTCTL; /**< analog test control */
|
||||
reg32_t ADCDOUBLERNANOAMPCTL; /**< ADC doubler nanoamp control */
|
||||
reg32_t XOSCHFCTL; /**< XOSCHF control */
|
||||
reg32_t LFOSCCTL; /**< low frequency oscillator control */
|
||||
reg32_t RCOSCHFCTL; /**< RCOSCHF control */
|
||||
reg32_t STAT0; /**< status 0 */
|
||||
reg32_t STAT1; /**< status 1 */
|
||||
reg32_t STAT2; /**< status 2 */
|
||||
} ddi0_osc_regs_t;
|
||||
|
||||
/**
|
||||
* @brief DDI_0_OSC register values
|
||||
* @{
|
||||
*/
|
||||
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x0
|
||||
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x1
|
||||
#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x2
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask 0x6
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC 0x0
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC 0x4
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC 0x8
|
||||
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC 0xC
|
||||
#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask 0x60
|
||||
#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF 0x00 /* 31.25kHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF 0x20 /* 31.25kHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF 0x40 /* 32kHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF 0x60 /* 32.768kHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask 0x180
|
||||
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF 0x000 /* 48MHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF 0x080 /* 48MHz */
|
||||
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF 0x100 /* 24MHz */
|
||||
#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x200 /* enable clock loss detection */
|
||||
#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x400 /* bypass XOSC_LF and use digital input clock from AON foor xosx_lf (precuations in datasheet) */
|
||||
#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x800
|
||||
#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x1000
|
||||
#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x10000
|
||||
#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x400000
|
||||
#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x2000000
|
||||
#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask 0x6000000
|
||||
#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
|
||||
#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
|
||||
#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */
|
||||
/*@}*/
|
||||
|
||||
#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */
|
||||
|
||||
|
||||
/**
|
||||
* AON_SYSCTL registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t PWRCTL; /**< power management */
|
||||
reg32_t RESETCTL; /**< reset management */
|
||||
reg32_t SLEEPCTL; /**< sleep mode */
|
||||
} aon_sysctl_regs_t;
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define AON_SYSCTL_BASE 0x40090000 /**< AON_SYSCTL base address */
|
||||
/*@}*/
|
||||
|
||||
#define AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE)) /**< AON_SYSCTL register bank */
|
||||
|
||||
|
||||
/**
|
||||
* AON_WUC registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t MCUCLK; /**< MCU clock management */
|
||||
reg32_t AUXCLK; /**< AUX clock management */
|
||||
reg32_t MCUCFG; /**< MCU config */
|
||||
reg32_t AUXCFG; /**< AUX config */
|
||||
reg32_t AUXCTL; /**< AUX control */
|
||||
reg32_t PWRSTAT; /**< power status */
|
||||
reg32_t __reserved1; /**< meh */
|
||||
reg32_t SHUTDOWN; /**< shutdown control */
|
||||
reg32_t CTL0; /**< control 0 */
|
||||
reg32_t CTL1; /**< control 1 */
|
||||
reg32_t __reserved2[2]; /**< meh */
|
||||
reg32_t RECHARGECFG; /**< recharge controller config */
|
||||
reg32_t RECHARGESTAT; /**< recharge controller status */
|
||||
reg32_t __reserved3; /**< meh */
|
||||
reg32_t OSCCFG; /**< oscillator config */
|
||||
reg32_t JTAGCFG; /**< JTAG config */
|
||||
reg32_t JTAGUSERCODE; /**< JTAG USERCODE */
|
||||
} aon_wuc_regs_t;
|
||||
|
||||
/**
|
||||
* @brief AON_WUC register values
|
||||
* @{
|
||||
*/
|
||||
#define MCUCLK_PWR_DWN_SRC 0x1 /* SCLK_LF in powerdown (no clock elsewise) */
|
||||
#define MCUCLK_PWR_DWN_SRC_mask 0x3
|
||||
#define MCUCLK_RCOSC_HF_CAL_DONE 0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */
|
||||
|
||||
#define AUXCLK_SRC_HF 0x1 /* SCLK for AUX */
|
||||
#define AUXCLK_SRC_LF 0x4
|
||||
#define AUXCLK_SRC_mask 0x7 /* garuanteed to be glitchless */
|
||||
#define AUXCLK_SCLK_HF_DIV_pos 8 /* don't set while SCLK_HF active for AUX */
|
||||
#define AUXCLK_SCLK_HF_DIV_mask 0x700 /* divisor will be 2^(value+1) */
|
||||
#define AUXCLK_PWR_DWN_SRC_pos 11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */
|
||||
#define AUXCLK_PWR_DWN_SRC_mask 0x1800 /* datasheet is confusing.. */
|
||||
|
||||
#define MCUCFG_SRAM_RET_OFF 0x0 /* no retention for any SRAM-bank */
|
||||
#define MCUCFG_SRAM_RET_B0 0x1
|
||||
#define MCUCFG_SRAM_RET_B01 0x3
|
||||
#define MCUCFG_SRAM_RET_B012 0x7
|
||||
#define MCUCFG_SRAM_RET_B0124 0xF /* retention for banks 0, 1, 2, and 3 */
|
||||
#define MCUCFG_SRAM_FIXED_WU_EN 0x100
|
||||
#define MCUCFG_SRAM_VIRT_OFF 0x200
|
||||
|
||||
#define AUXCFG_RAM_RET_EN 0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */
|
||||
|
||||
#define AUXCTL_AUX_FORCE_ON 0x1
|
||||
#define AUXCTL_SWEV 0x2
|
||||
#define AUXCTL_SCE_RUN_EN 0x3
|
||||
#define AUXCTL_RESET_REQ 0x80000000
|
||||
|
||||
#define PWRSTAT_AUX_RESET_DONE 0x2
|
||||
#define PWRSTAT_AUX_BUS_CONNECTED 0x4
|
||||
#define PWRSTAT_MCU_PD_ON 0x10
|
||||
#define PWRSTAT_AUX_PD_ON 0x20
|
||||
#define PWRSTAT_JTAG_PD_ON 0x40
|
||||
#define PWRSTAT_AUX_PWR_DNW 0x200
|
||||
|
||||
#define SHUTDOWN_EN 0x1 /* register/cancel shutdown request */
|
||||
|
||||
#define AONWUC_CTL0_MCU_SRAM_ERASE 0x4
|
||||
#define AONWUC_CTL0_AUX_SRAM_ERASE 0x8
|
||||
#define AONWUC_CTL0_PWR_DWN_DIS 0x10 /* disable powerdown on request */
|
||||
|
||||
#define AONWUC_CTL1_MCU_WARM_RESET 0x1 /* last MCU reset was a warm reset */
|
||||
#define AONWUC_CTL1_MCU_RESET_SRC 0x2 /* JTAG was source of last reset (MCU SW elsewise) */
|
||||
|
||||
#define RECHARGECFG_PER_E_mask 0x00000007 /* number of 32KHz clocks between activation of recharge controller: */
|
||||
#define RECHARGECFG_PER_M_mask 0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
|
||||
#define RECHARGECFG_MAX_PER_E_mask 0x00000700 /* maximum period the recharge algorithm can take */
|
||||
#define RECHARGECFG_MAX_PER_M_mask 0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */
|
||||
#define RECHARGECFG_C1_mask 0x000F0000 /* i resign */
|
||||
#define RECHARGECFG_C2_mask 0x000F0000
|
||||
#define RECHARGECFG_ADAPTIVE_EN 0x80000000
|
||||
|
||||
#define RECHARGESTAT_MAX_USED_PER_mask 0x0FFFF
|
||||
#define RECHARGESTAT_VDDR_SMPLS_mask 0xF0000
|
||||
|
||||
#define OSCCFG_PER_E_mask 0x07 /* number of 32KHz clocks between oscillator amplitude callibrations */
|
||||
#define OSCCFG_PER_M_mask 0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
|
||||
|
||||
#define JTAGCFG_JTAG_PD_FORCE_ON 0x10
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define AON_WUC_BASE 0x40091000 /**< AON_WUC base address */
|
||||
/*@}*/
|
||||
|
||||
#define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) /**< AON_WUC register bank */
|
||||
|
||||
|
||||
/**
|
||||
* PRCM registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */
|
||||
reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */
|
||||
reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */
|
||||
reg32_t VDCTL; /**< MCU voltage domain control */
|
||||
reg32_t __reserved1[6]; /**< meh */
|
||||
reg32_t CLKLOADCTL; /**< clock load control */
|
||||
reg32_t RFCCLKG; /**< RFC clock gate */
|
||||
reg32_t VIMSCLKG; /**< VIMS clock gate */
|
||||
reg32_t __reserved2[2]; /**< meh */
|
||||
reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */
|
||||
reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */
|
||||
reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */
|
||||
reg32_t GPIOCLKGR; /**< GPIO clock gate for run mode */
|
||||
reg32_t GPIOCLKGS; /**< GPIO clock gate for sleep mode */
|
||||
reg32_t GPIOCLKGDS; /**< GPIO clock gate for deep sleep mode */
|
||||
reg32_t GPTCLKGR; /**< GPT clock gate for run mode */
|
||||
reg32_t GPTCLKGS; /**< GPT clock gate for sleep mode */
|
||||
reg32_t GPTCLKGDS; /**< GPT clock gate for deep sleep mode */
|
||||
reg32_t I2CCLKGR; /**< I2C clock gate for run mode */
|
||||
reg32_t I2CCLKGS; /**< I2C clock gate for sleep mode */
|
||||
reg32_t I2CCLKGDS; /**< I2C clock gate for deep sleep mode */
|
||||
reg32_t UARTCLKGR; /**< UART clock gate for run mode */
|
||||
reg32_t UARTCLKGS; /**< UART clock gate for sleep mode */
|
||||
reg32_t UARTCLKGDS; /**< UART clock gate for deep sleep mode */
|
||||
reg32_t SSICLKGR; /**< SSI clock gate for run mode */
|
||||
reg32_t SSICLKGS; /**< SSI clock gate for sleep mode */
|
||||
reg32_t SSICLKGDS; /**< SSI clock gate for deep sleep mode */
|
||||
reg32_t I2SCLKGR; /**< I2S clock gate for run mode */
|
||||
reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */
|
||||
reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */
|
||||
reg32_t __reserved3[10]; /**< meh */
|
||||
reg32_t CPUCLKDIV; /**< CPU clock division factor */
|
||||
reg32_t __reserved4[3]; /**< meh */
|
||||
reg32_t I2SBCLKSEL; /**< I2S clock select */
|
||||
reg32_t GPTCLKDIV; /**< GPT scalar */
|
||||
reg32_t I2SCLKCTL; /**< I2S clock control */
|
||||
reg32_t I2SMCLKDIV; /**< MCLK division ratio */
|
||||
reg32_t I2SBCLKDIV; /**< BCLK division ratio */
|
||||
reg32_t I2SWCLKDIV; /**< WCLK division ratio */
|
||||
reg32_t __reserved5[11]; /**< meh */
|
||||
reg32_t SWRESET; /**< SW initiated resets */
|
||||
reg32_t WARMRESET; /**< WARM reset control and status */
|
||||
reg32_t __reserved6[6]; /**< meh */
|
||||
reg32_t PDCTL0; /**< power domain control */
|
||||
reg32_t PDCTL0RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */
|
||||
reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */
|
||||
reg32_t __reserved7; /**< meh */
|
||||
reg32_t PDSTAT0; /**< power domain status */
|
||||
reg32_t PDSTAT0RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */
|
||||
reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */
|
||||
reg32_t __reserved8[11]; /**< meh */
|
||||
reg32_t PDCTL1; /**< power domain control */
|
||||
reg32_t __reserved9; /**< power domain control */
|
||||
reg32_t PDCTL1CPU; /**< CPU power domain control */
|
||||
reg32_t PDCTL1RFC; /**< RFC power domain control */
|
||||
reg32_t PDCTL1VIMS; /**< VIMS power domain control */
|
||||
reg32_t __reserved10; /**< meh */
|
||||
reg32_t PDSTAT1; /**< power domain status */
|
||||
reg32_t PDSTAT1BUS; /**< BUS power domain status */
|
||||
reg32_t PDSTAT1RFC; /**< RFC power domain status */
|
||||
reg32_t PDSTAT1CPU; /**< CPU power domain status */
|
||||
reg32_t PDSTAT1VIMS; /**< VIMS power domain status */
|
||||
reg32_t __reserved11[10]; /**< meh */
|
||||
reg32_t RFCMODESEL; /**< selected RFC mode */
|
||||
reg32_t __reserved12[20]; /**< meh */
|
||||
reg32_t RAMRETEN; /**< memory retention control */
|
||||
reg32_t __reserved13; /**< meh */
|
||||
reg32_t PDRETEN; /**< power domain retention (undocumented) */
|
||||
reg32_t __reserved14[8]; /**< meh */
|
||||
reg32_t RAMHWOPT; /**< undocumented */
|
||||
} prcm_regs_t;
|
||||
|
||||
/**
|
||||
* @brief PRCM register values
|
||||
* @{
|
||||
*/
|
||||
#define CLKLOADCTL_LOAD 0x1
|
||||
#define CLKLOADCTL_LOADDONE 0x2
|
||||
|
||||
#define PDCTL0_RFC_ON 0x1
|
||||
#define PDCTL0_SERIAL_ON 0x2
|
||||
#define PDCTL0_PERIPH_ON 0x4
|
||||
|
||||
#define PDSTAT0_RFC_ON 0x1
|
||||
#define PDSTAT0_SERIAL_ON 0x2
|
||||
#define PDSTAT0_PERIPH_ON 0x4
|
||||
|
||||
#define PDCTL1_CPU_ON 0x2
|
||||
#define PDCTL1_RFC_ON 0x4
|
||||
#define PDCTL1_VIMS_ON 0x8
|
||||
|
||||
#define PDSTAT1_CPU_ON 0x2
|
||||
#define PDSTAT1_RFC_ON 0x4
|
||||
#define PDSTAT1_VIMS_ON 0x8
|
||||
/** @} */
|
||||
|
||||
/** @ingroup cpu_specific_peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
#define PRCM_BASE 0x40082000 /**< PRCM base address */
|
||||
/*@}*/
|
||||
|
||||
#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* end extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* CC26x0_PRCM_H */
|
||||
|
||||
/*@}*/
|
||||
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Leon George
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_cc26x0_definitions
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief CC26x0 UART interface
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef CC26x0_UART_H
|
||||
#define CC26x0_UART_H
|
||||
|
||||
#include "cc26x0.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UART_BASE (0x40001000) /**< UART base address */
|
||||
|
||||
/**
|
||||
* @brief UART component registers
|
||||
*/
|
||||
typedef struct {
|
||||
reg32_t DR; /**< data */
|
||||
union {
|
||||
reg32_t RSR; /**< status */
|
||||
reg32_t ECR; /**< error clear */
|
||||
};
|
||||
reg32_t __reserved1[4]; /**< meh */
|
||||
reg32_t FR; /**< flag */
|
||||
reg32_t __reserved2[2]; /**< meh */
|
||||
reg32_t IBRD; /**< integer baud-rate divisor */
|
||||
reg32_t FBRD; /**< fractional baud-rate divisor */
|
||||
reg32_t LCRH; /**< line control */
|
||||
reg32_t CTL; /**< control */
|
||||
reg32_t IFLS; /**< interrupt fifo level select */
|
||||
reg32_t IMSC; /**< interrupt mask set/clear */
|
||||
reg32_t RIS; /**< raw interrupt status */
|
||||
reg32_t MIS; /**< masked interrupt status */
|
||||
reg32_t ICR; /**< interrupt clear */
|
||||
reg32_t DMACTL; /**< DMA control */
|
||||
} uart_regs_t;
|
||||
|
||||
/**
|
||||
* @brief UART register values
|
||||
* @{
|
||||
*/
|
||||
#define UART_DR_DATA_mask 0xFF
|
||||
#define UART_DR_FE 0x100
|
||||
#define UART_DR_PE 0x200
|
||||
#define UART_DR_BE 0x400
|
||||
#define UART_DR_OE 0x800
|
||||
|
||||
#define UART_ECR_FE 0x1
|
||||
#define UART_ECR_PE 0x2
|
||||
#define UART_ECR_BE 0x4
|
||||
#define UART_ECR_OE 0x8
|
||||
|
||||
#define UART_FR_CTS 0x1
|
||||
#define UART_FR_BUSY 0x4
|
||||
#define UART_FR_RXFE 0x10
|
||||
#define UART_FR_TXFF 0x20
|
||||
#define UART_FR_RXFF 0x40
|
||||
#define UART_FR_TXFE 0x80
|
||||
|
||||
#define UART_LCRH_PEN 0x1
|
||||
#define UART_LCRH_EPS 0x2
|
||||
#define UART_LCRH_RXFE 0x4
|
||||
#define UART_LCRH_STP2 0x8
|
||||
#define UART_LCRH_FEN 0x10
|
||||
#define UART_LCRH_WLEN_mask 0x60
|
||||
#define UART_LCRH_WLEN_5 0x0
|
||||
#define UART_LCRH_WLEN_6 0x20
|
||||
#define UART_LCRH_WLEN_7 0x40
|
||||
#define UART_LCRH_WLEN_8 0x60
|
||||
#define UART_LCRH_SPS 0x80
|
||||
|
||||
#define UART_CTL_UARTEN 0x1
|
||||
#define UART_CTL_LBE 0x80
|
||||
#define UART_CTL_TXE 0x100
|
||||
#define UART_CTL_RXE 0x200
|
||||
#define UART_CTL_RTS 0x800
|
||||
#define UART_CTL_RTSEN 0x4000
|
||||
#define UART_CTL_CTSEN 0x8000
|
||||
|
||||
#define UART_MIS_CTSMMIS 0x1
|
||||
#define UART_MIS_RXMIS 0x10
|
||||
#define UART_MIS_TXMIS 0x20
|
||||
#define UART_MIS_RTMIS 0x40
|
||||
#define UART_MIS_FEMIS 0x80
|
||||
#define UART_MIS_PEMIS 0x100
|
||||
#define UART_MIS_BEMIS 0x200
|
||||
#define UART_MIS_OEMIS 0x400
|
||||
|
||||
#define UART_IMSC_CTSMIM 0x2
|
||||
#define UART_IMSC_RXIM 0x10
|
||||
#define UART_IMSC_TXIM 0x20
|
||||
#define UART_IMSC_RTIM 0x40
|
||||
#define UART_IMSC_FEIM 0x80
|
||||
#define UART_IMSC_PEIM 0x100
|
||||
#define UART_IMSC_BEIM 0x200
|
||||
#define UART_IMSC_OEIM 0x400
|
||||
|
||||
#define UART_IFLS_TXSEL_1_8 0x0
|
||||