cpu/stm32x: unified PWM driver
Hauke Petersen
7 years ago
parent
6ab089e63e
commit
4d09d09ee4
@ -0,0 +1,142 @@
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/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* 2015 Engineering-Spirit
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* 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @{
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*
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* @file
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* @brief Low-level PWM driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Aurelien Gonce <aurelien.gonce@altran.fr>
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*
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* @}
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*/
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#include "cpu.h"
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#include "assert.h"
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#include "periph/pwm.h"
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#include "periph/gpio.h"
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#ifdef PWM_NUMOF
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#define CCMR_LEFT (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | \
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2)
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#define CCMR_RIGHT (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | \
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TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_0 | \
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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static inline TIM_TypeDef *dev(pwm_t pwm)
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{
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return pwm_config[pwm].dev;
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}
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uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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uint32_t bus_clk = periph_apb_clk(pwm_config[pwm].bus);
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/* verify parameters */
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assert((pwm < PWM_NUMOF) && ((freq * res) < bus_clk));
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/* power on the used timer */
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pwm_poweron(pwm);
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/* reset configuration and CC channels */
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dev(pwm)->CR1 = 0;
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dev(pwm)->CR2 = 0;
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for (int i = 0; i < TIMER_CHAN; i++) {
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dev(pwm)->CCR[i] = 0;
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}
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/* configure the used pins */
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for (unsigned i = 0; i < pwm_config[pwm].chan; i++) {
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gpio_init(pwm_config[pwm].pins[i], GPIO_OUT);
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gpio_init_af(pwm_config[pwm].pins[i], pwm_config[pwm].af);
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}
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/* configure the PWM frequency and resolution by setting the auto-reload
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* and prescaler registers */
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dev(pwm)->PSC = (bus_clk / (res * freq)) - 1;
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dev(pwm)->ARR = res - 1;
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/* set PWM mode */
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switch (mode) {
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case PWM_LEFT:
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dev(pwm)->CCMR1 = CCMR_LEFT;
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dev(pwm)->CCMR2 = CCMR_LEFT;
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break;
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case PWM_RIGHT:
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dev(pwm)->CCMR1 = CCMR_RIGHT;
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dev(pwm)->CCMR2 = CCMR_RIGHT;
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break;
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case PWM_CENTER:
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dev(pwm)->CCMR1 = 0;
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dev(pwm)->CCMR2 = 0;
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dev(pwm)->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
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break;
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}
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/* enable PWM outputs and start PWM generation */
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#ifdef TIM_BDTR_MOE
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dev(pwm)->BDTR = TIM_BDTR_MOE;
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#endif
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dev(pwm)->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E |
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TIM_CCER_CC3E | TIM_CCER_CC4E);
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dev(pwm)->CR1 |= TIM_CR1_CEN;
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/* return the actual used PWM frequency */
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return (bus_clk / (res * (dev(pwm)->PSC + 1)));
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}
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uint8_t pwm_channels(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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return pwm_config[pwm].chan;
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}
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void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value)
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{
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assert((pwm < PWM_NUMOF) && (channel < pwm_config[pwm].chan));
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/* norm value to maximum possible value */
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if (value > dev(pwm)->ARR) {
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value = (uint16_t)dev(pwm)->ARR;
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}
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/* set new value */
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dev(pwm)->CCR[channel] = value;
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}
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void pwm_start(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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dev(pwm)->CR1 |= TIM_CR1_CEN;
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}
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void pwm_stop(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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dev(pwm)->CR1 &= ~TIM_CR1_CEN;
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}
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void pwm_poweron(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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periph_clk_en(pwm_config[pwm].bus, pwm_config[pwm].rcc_mask);
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}
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void pwm_poweroff(pwm_t pwm)
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{
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assert(pwm < PWM_NUMOF);
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periph_clk_dis(pwm_config[pwm].bus, pwm_config[pwm].rcc_mask);
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}
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#endif /* PWM_NUMOF */
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@ -1,237 +0,0 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f3
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* @{
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*
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* @file
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* @brief Low-level PWM driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include <string.h>
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#include "cpu.h"
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#include "periph_conf.h"
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/* guard file in case no PWM device is defined */
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#if (PWM_0_EN || PWM_1_EN)
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/* pull the PWM header inside the guards for now. Guards will be removed on
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* adapting this driver implementation... */
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#include "periph/pwm.h"
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uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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TIM_TypeDef *tim = NULL;
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GPIO_TypeDef *port = NULL;
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uint32_t pins[PWM_MAX_CHANNELS];
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uint32_t af;
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int channels;
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uint32_t pwm_clk;
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pwm_poweron(dev);
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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tim = PWM_0_DEV;
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port = PWM_0_PORT;
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pins[0] = PWM_0_PIN_CH0;
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pins[1] = PWM_0_PIN_CH1;
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pins[2] = PWM_0_PIN_CH2;
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pins[3] = PWM_0_PIN_CH3;
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af = PWM_0_PIN_AF;
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channels = PWM_0_CHANNELS;
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pwm_clk = PWM_0_CLK;
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PWM_0_PORT_CLKEN();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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tim = PWM_1_DEV;
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port = PWM_1_PORT;
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pins[0] = PWM_1_PIN_CH0;
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pins[1] = PWM_1_PIN_CH1;
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pins[2] = PWM_1_PIN_CH2;
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pins[3] = PWM_1_PIN_CH3;
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af = PWM_1_PIN_AF;
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channels = PWM_1_CHANNELS;
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pwm_clk = PWM_1_CLK;
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PWM_1_PORT_CLKEN();
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break;
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#endif
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default:
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pwm_poweroff(dev);
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return 0;
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}
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/* setup pins: alternate function */
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for (int i = 0; i < channels; i++) {
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port->MODER &= ~(3 << (pins[i] * 2));
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port->MODER |= (2 << (pins[i] * 2));
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if (pins[i] < 8) {
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port->AFR[0] &= ~(0xf << (pins[i] * 4));
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port->AFR[0] |= (af << (pins[i] * 4));
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}
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else {
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port->AFR[1] &= ~(0xf << ((pins[i] - 8) * 4));
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port->AFR[1] |= (af << ((pins[i] - 8) * 4));
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}
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}
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/* reset timer configuration registers */
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tim->CR1 = 0;
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tim->CR2 = 0;
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tim->CCMR1 = 0;
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tim->CCMR2 = 0;
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/* set prescale and auto-reload registers to matching values for resolution and frequency */
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if ((res > 0xffff) || ((res * freq) > pwm_clk)) {
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return 0;
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}
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tim->PSC = (pwm_clk / (res * freq)) - 1;
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tim->ARR = res - 1;
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freq = (pwm_clk / (res * (tim->PSC + 1)));
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/* set PWM mode */
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switch (mode) {
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case PWM_LEFT:
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tim->CCMR1 |= (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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tim->CCMR2 |= (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
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break;
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case PWM_RIGHT:
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tim->CCMR1 |= (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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tim->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
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break;
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case PWM_CENTER:
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tim->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
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break;
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}
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/* enable output on PWM pins */
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tim->CCER |= (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
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/* enable PWM generation */
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pwm_start(dev);
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return freq;
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}
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uint8_t pwm_channels(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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return PWM_0_CHANNELS;
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#endif
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#if PWM_1_EN
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case PWM_1:
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return PWM_1_CHANNELS;
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#endif
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default:
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return 0;
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}
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}
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void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
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{
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TIM_TypeDef *tim = NULL;
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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tim = PWM_0_DEV;
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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tim = PWM_1_DEV;
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break;
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#endif
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default:
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return;
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}
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tim->CCR[channel] = value;
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}
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void pwm_start(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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}
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}
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void pwm_stop(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_DEV->CR1 &= ~(TIM_CR1_CEN);
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_DEV->CR1 &= ~(TIM_CR1_CEN);
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break;
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#endif
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}
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}
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void pwm_poweron(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_CLKEN();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_CLKEN();
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break;
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#endif
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}
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}
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void pwm_poweroff(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_CLKDIS();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_CLKDIS();
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break;
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#endif
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}
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}
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#endif /* (PWM_0_EN || PWM_1_EN) */
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@ -1,281 +0,0 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Low-level PWM driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include <string.h>
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#include "cpu.h"
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#include "periph_conf.h"
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/* guard file in case no PWM device is defined */
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#if (PWM_0_EN || PWM_1_EN)
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/* pull the PWM header inside the guards for now. Guards will be removed on
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* adapting this driver implementation... */
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#include "periph/pwm.h"
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uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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TIM_TypeDef *tim = NULL;
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GPIO_TypeDef *port = NULL;
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uint32_t pins[PWM_MAX_CHANNELS];
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uint32_t af = 0;
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uint32_t pwm_clk = 0;
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int channels = 0;
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pwm_poweron(dev);
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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tim = PWM_0_DEV;
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port = PWM_0_PORT;
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pins[0] = PWM_0_PIN_CH0;
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#if (PWM_0_CHANNELS > 1)
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pins[1] = PWM_0_PIN_CH1;
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#endif
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#if (PWM_0_CHANNELS > 2)
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pins[2] = PWM_0_PIN_CH2;
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#endif
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#if (PWM_0_CHANNELS > 3)
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pins[3] = PWM_0_PIN_CH3;
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#endif
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af = PWM_0_PIN_AF;
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channels = PWM_0_CHANNELS;
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pwm_clk = PWM_0_CLK;
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PWM_0_PORT_CLKEN();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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tim = PWM_1_DEV;
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port = PWM_1_PORT;
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pins[0] = PWM_1_PIN_CH0;
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#if (PWM_1_CHANNELS > 1)
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pins[1] = PWM_1_PIN_CH1;
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#endif
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#if (PWM_1_CHANNELS > 2)
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pins[2] = PWM_1_PIN_CH2;
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#endif
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#if (PWM_1_CHANNELS > 3)
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pins[3] = PWM_1_PIN_CH3;
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#endif
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af = PWM_1_PIN_AF;
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channels = PWM_1_CHANNELS;
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pwm_clk = PWM_1_CLK;
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PWM_1_PORT_CLKEN();
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break;
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#endif
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}
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/* setup pins: alternate function */
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for (int i = 0; i < channels; i++) {
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port->MODER &= ~(3 << (pins[i] * 2));
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port->MODER |= (2 << (pins[i] * 2));
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if (pins[i] < 8) {
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port->AFR[0] &= ~(0xf << (pins[i] * 4));
|
||||
port->AFR[0] |= (af << (pins[i] * 4));
|
||||
} else {
|
||||
port->AFR[1] &= ~(0xf << ((pins[i] - 8) * 4));
|
||||
port->AFR[1] |= (af << ((pins[i] - 8) * 4));
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset C/C and timer configuration register */
|
||||
switch (channels) {
|
||||
case 4:
|
||||
tim->CCR[3] = 0;
|
||||
/* Fall through */
|
||||
case 3:
|
||||
tim->CCR[2] = 0;
|
||||
tim->CR2 = 0;
|
||||
/* Fall through */
|
||||
case 2:
|
||||
tim->CCR[1] = 0;
|
||||
/* Fall through */
|
||||
case 1:
|
||||
tim->CCR[0] = 0;
|
||||
tim->CR1 = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* set prescale and auto-reload registers to matching values for resolution
|
||||
* and frequency */
|
||||
if (res > 0xffff || (res * freq) > pwm_clk) {
|
||||
return 0;
|
||||
}
|
||||
tim->PSC = (pwm_clk / (res * freq)) - 1;
|
||||
tim->ARR = res - 1;
|
||||
|
||||
/* calculate the actual PWM frequency */
|
||||
freq = (pwm_clk / (res * (tim->PSC + 1)));
|
||||
|
||||
/* set PWM mode */
|
||||
switch (mode) {
|
||||
case PWM_LEFT:
|
||||
tim->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
|
||||
TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
|
||||
if (channels > 2) {
|
||||
tim->CCMR2 = (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
|
||||
TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
|
||||
}
|
||||
break;
|
||||
case PWM_RIGHT:
|
||||
tim->CCMR1 = (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
|
||||
TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
|
||||
if (channels > 2) {
|
||||
tim->CCMR2 = (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
|
||||
TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
|
||||
}
|
||||
break;
|
||||
case PWM_CENTER:
|
||||
tim->CCMR1 = 0;
|
||||
if (channels > 2) {
|
||||
tim->CCMR2 = 0;
|
||||
}
|
||||
tim->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable output on PWM pins */
|
||||
tim->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
|
||||
|
||||
/* enable PWM outputs */
|
||||
tim->BDTR = TIM_BDTR_MOE;
|
||||
|
||||
/* enable timer ergo the PWM generation */
|
||||
pwm_start(dev);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
uint8_t pwm_channels(pwm_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
return PWM_0_CHANNELS;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
return PWM_1_CHANNELS;
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
|
||||
{
|
||||
TIM_TypeDef *tim = NULL;
|
||||
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
tim = PWM_0_DEV;
|
||||
if (channel >= PWM_0_CHANNELS) {
|
||||
return;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
tim = PWM_1_DEV;
|
||||
if (channel >= PWM_1_CHANNELS) {
|
||||
return;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* norm value to maximum possible value */
|
||||
if (value > tim->ARR) {
|
||||
value = (uint32_t)tim->ARR;
|
||||
}
|
||||
|
||||
tim->CCR[channel] = value;
|
||||
}
|
||||
|
||||
void pwm_start(pwm_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
PWM_0_DEV->CR1 |= TIM_CR1_CEN;
|
||||
break;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
PWM_1_DEV->CR1 |= TIM_CR1_CEN;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void pwm_stop(pwm_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
PWM_0_DEV->CR1 &= ~(TIM_CR1_CEN);
|
||||
break;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
PWM_1_DEV->CR1 &= ~(TIM_CR1_CEN);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void pwm_poweron(pwm_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
PWM_0_CLKEN();
|
||||
break;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
PWM_1_CLKEN();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void pwm_poweroff(pwm_t dev)
|
||||
{
|
||||
switch (dev) {
|
||||
#if PWM_0_EN
|
||||
case PWM_0:
|
||||
PWM_0_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
#if PWM_1_EN
|
||||
case PWM_1:
|
||||
PWM_1_CLKDIS();
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* (PWM_0_EN || PWM_1_EN) */
|
||||
Loading…
Reference in New Issue