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Merge pull request #2756 from jremmert-phytec-iot/pr@ng_kw2xrf

driver/kw2xrf: added ng_netdev implementation for the Freescale kw2x radio
dev/timer
Oleg Hahm 8 years ago
parent
commit
4d64b98f2c
  1. 3
      drivers/Makefile.include
  2. 147
      drivers/include/kw2xrf.h
  3. 1
      drivers/kw2xrf/Makefile
  4. 356
      drivers/kw2xrf/include/kw2xrf_reg.h
  5. 118
      drivers/kw2xrf/include/kw2xrf_spi.h
  6. 1173
      drivers/kw2xrf/kw2xrf.c
  7. 153
      drivers/kw2xrf/kw2xrf_spi.c
  8. 2
      sys/include/net/ng_netconf.h
  9. 51
      tests/driver_kw2xrf/Makefile
  10. 12
      tests/driver_kw2xrf/README.md
  11. 1
      tests/driver_kw2xrf/auto_init_ng_netif/Makefile
  12. 86
      tests/driver_kw2xrf/auto_init_ng_netif/netif_app.c
  13. 72
      tests/driver_kw2xrf/main.c

3
drivers/Makefile.include

@ -16,6 +16,9 @@ endif
ifneq (,$(filter ng_at86rf2xx,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/ng_at86rf2xx/include
endif
ifneq (,$(filter kw2xrf,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw2xrf/include
endif
ifneq (,$(filter isl29020,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/isl29020/include
endif

147
drivers/include/kw2xrf.h

@ -0,0 +1,147 @@
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup drivers_kw2xrf kw2x radio-driver
* @ingroup drivers
* @brief Device driver for the Freescale KW2xD radio
* @{
*
* @file
* @brief Interface definition for the KW2xD device driver
*
* @author Johann Fischer <j.fischer@phytec.de>
* @author Jonas Remmert <j.remmert@phytec.de>
*/
#ifndef MKW2XDRF_H_
#define MKW2XDRF_H_
#include <stdint.h>
#include "board.h"
#include "periph/spi.h"
#include "periph/gpio.h"
#include "net/ng_netdev.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Maximum packet length
*/
#define KW2XRF_MAX_PKT_LENGTH (127U)
/**
* @brief Default protocol for data that is coming in
*/
#ifdef MODULE_NG_SIXLOWPAN
#define KW2XRF_DEFAULT_PROTOCOL NG_NETTYPE_SIXLOWPAN
#else
#define KW2XRF_DEFAULT_PROTOCOL NG_NETTYPE_UNDEF
#endif
/**
* @brief Default short address used after initialization
*/
#define KW2XRF_DEFAULT_SHORT_ADDR (0x0002)
/**
* @brief Default short address used after initialization
*/
#define KW2XRF_DEFAULT_ADDR_LONG (0x0000000000000000)
/**
* @brief Default PAN ID used after initialization
*/
#define KW2XRF_DEFAULT_PANID (0x0023)
/**
* @brief Default channel used after initialization
*/
#define KW2XRF_DEFAULT_CHANNEL (17U)
/**
* @brief Default TX_POWER in dbm used after initialization
*/
#define KW2XRF_DEFAULT_TX_POWER (0)
/**
* @brief Maximum output power of the kw2x device in dBm
*/
#define MKW2XDRF_OUTPUT_POWER_MAX (8)
/**
* @brief Minimum output power of the kw2x device in dBm
*/
#define MKW2XDRF_OUTPUT_POWER_MIN (-35)
/**
* @brief Internal device option flags
* @{
*/
#define KW2XRF_OPT_AUTOACK (0x0001) /**< auto ACKs active */
#define KW2XRF_OPT_CSMA (0x0002) /**< CSMA active */
#define KW2XRF_OPT_PROMISCUOUS (0x0004) /**< promiscuous mode active */
#define KW2XRF_OPT_PRELOADING (0x0008) /**< preloading enabled */
#define KW2XRF_OPT_TELL_TX_START (0x0010) /**< notify MAC layer on TX start */
#define KW2XRF_OPT_TELL_TX_END (0x0020) /**< notify MAC layer on TX finished */
#define KW2XRF_OPT_TELL_RX_START (0x0040) /**< notify MAC layer on RX start */
#define KW2XRF_OPT_TELL_RX_END (0x0080) /**< notify MAC layer on RX finished */
#define KW2XRF_OPT_RAWDUMP (0x0100) /**< pass RAW frame data to upper layer */
#define KW2XRF_OPT_SRC_ADDR_LONG (0x0200) /**< send data using long source address */
#define KW2XRF_OPT_USE_SRC_PAN (0x0400) /**< do not compress source PAN ID */
/** @} */
/**
* @brief kw2xrf device descriptor
*/
typedef struct {
/* netdev fields */
ng_netdev_driver_t const *driver; /**< Pointer to the devices interface */
ng_netdev_event_cb_t event_cb; /**< Netdev event callback */
kernel_pid_t mac_pid; /**< The driver's thread's PID */
/* driver specific fields */
uint8_t buf[KW2XRF_MAX_PKT_LENGTH]; /**< Buffer for incoming or outgoing packets */
ng_netconf_state_t state; /**< Variable to keep radio driver's state */
uint8_t seq_nr; /**< Next packets sequence number */
uint16_t radio_pan; /**< The PAN the radio device is using */
uint8_t radio_channel; /**< The channel the radio device is using */
uint8_t addr_short[2]; /**< The short address the radio device is using */
uint8_t addr_long[8]; /**< The long address the radio device is using */
uint16_t option; /**< Bit field to save enable/disable options */
int8_t tx_power; /**< The current tx-power setting of the device */
ng_nettype_t proto; /**< Protocol the interface speaks */
} kw2xrf_t;
/**
* @brief Initialize the given KW2XRF device
* @param[out] dev device descriptor
* @param[in] spi SPI bus the device is connected to
* @param[in] spi_speed SPI speed to use
* @param[in] cs_pin GPIO pin connected to chip select
* @param[in] int_pin GPIO pin connected to the interrupt pin
*
* @return 0 on success
* @return <0 on error
*/
int kw2xrf_init(kw2xrf_t *dev, spi_t spi, spi_speed_t spi_speed,
gpio_t cs_pin, gpio_t int_pin);
/**
* @brief Reference to the KW2XRF driver interface
*/
extern const ng_netdev_driver_t kw2xrf_driver;
#ifdef __cplusplus
}
#endif
#endif
/** @} */

1
drivers/kw2xrf/Makefile

@ -0,0 +1 @@
include $(RIOTBASE)/Makefile.base

356
drivers/kw2xrf/include/kw2xrf_reg.h

@ -0,0 +1,356 @@
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup drivers_kw2xrf
* @{
*
* @file
* @brief Register and command definitions for the MKW2XD Modem
*
* @author Johann Fischer <j.fischer@phytec.de>
*/
#ifndef MKW2XD_MODEM_REG_H
#define MKW2XD_MODEM_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/** Option to for SPI-IF to read a register */
#define MKW2XDRF_REG_READ (uint8_t)(1 << 7)
/** Option to for SPI-IF to write a register */
#define MKW2XDRF_REG_WRITE (uint8_t)(0)
/** Option to for SPI-IF to read data from the RX/TX-Buffer */
#define MKW2XDRF_BUF_READ (uint8_t)(1 << 7 | 1 << 6)
/** Option to for SPI-IF to write data to RX/TX-Buffer */
#define MKW2XDRF_BUF_WRITE (uint8_t)(1 << 6)
/** Option for SPI-IF */
#define MKW2XDRF_BUF_BYTE_READ (uint8_t)(1 << 7 | 1 << 6 | 1 << 5)
/** Option for SPI-IF */
#define MKW2XDRF_BUF_BYTE_WRITE (uint8_t)(1 << 6 | 1 << 5)
/** Transceiver Sequence Selector, define Values for XCVSEQ */
typedef enum {
XCVSEQ_IDLE = 0,
XCVSEQ_RECEIVE,
XCVSEQ_TRANSMIT,
XCVSEQ_CCA,
XCVSEQ_TX_RX,
XCVSEQ_CONTINUOUS_CCA,
}
kw2xrf_physeq_t;
enum mkw2xdrf_dregister {
MKW2XDM_IRQSTS1 = 0x0, /**< Interrupt Request Status 1 */
MKW2XDM_IRQSTS2 = 0x1, /**< Interrupt Request Status 2 */
MKW2XDM_IRQSTS3 = 0x2, /**< Interrupt Request Status 3 */
MKW2XDM_PHY_CTRL1 = 0x3, /**< PHY Control 1 */
MKW2XDM_PHY_CTRL2 = 0x4, /**< PHY Control 2 */
MKW2XDM_PHY_CTRL3 = 0x5, /**< PHY Control 3 */
MKW2XDM_RX_FRM_LEN = 0x6, /**< Receive Frame Length */
MKW2XDM_PHY_CTRL4 = 0x7, /**< PHY Control 4 */
MKW2XDM_SRC_CTRL = 0x8, /**< SRC Control */
MKW2XDM_SRC_ADDRS_SUM_LSB = 0x9, /**< SRC Address SUM LSB */
MKW2XDM_SRC_ADDRS_SUM_MSB = 0xa, /**< SRC Address SUM MSB */
MKW2XDM_CCA1_ED_FNL = 0xb, /**< CCA1 ED FNL */
MKW2XDM_EVENT_TIMER_LSB = 0xc, /**< Event Timer LSB */
MKW2XDM_EVENT_TIMER_MSB = 0xd, /**< Event Timer MSB */
MKW2XDM_EVENT_TIMER_USB = 0xe, /**< Event Timer USB */
MKW2XDM_TIMESTAMP_LSB = 0xf, /**< Timestamp LSB */
MKW2XDM_TIMESTAMP_MSB = 0x10, /**< Timestamp MSB */
MKW2XDM_TIMESTAMP_USB = 0x11, /**< Timestamp USB */
MKW2XDM_T3CMP_LSB = 0x12, /**< Timer 3 Compare Value LSB */
MKW2XDM_T3CMP_MSB = 0x13, /**< Timer 3 Compare Value MSB */
MKW2XDM_T3CMP_USB = 0x14, /**< Timer 3 Compare Value USB */
MKW2XDM_T2PRIMECMP_LSB = 0x15, /**< Timer 2-Prime Compare Value LSB */
MKW2XDM_T2PRIMECMP_MSB = 0x16, /**< Timer 2-Prime Compare Value MSB */
MKW2XDM_T1CMP_LSB = 0x17, /**< Timer 1 Compare Value LSB */
MKW2XDM_T1CMP_MSB = 0x18, /**< Timer 1 Compare Value MSB */
MKW2XDM_T1CMP_USB = 0x19, /**< Timer 1 Compare Value USB */
MKW2XDM_T2CMP_LSB = 0x1a, /**< Timer 2 Compare Value LSB */
MKW2XDM_T2CMP_MSB = 0x1b, /**< Timer 2 Compare Value MSB */
MKW2XDM_T2CMP_USB = 0x1c, /**< Timer 2 Compare Value USB */
MKW2XDM_T4CMP_LSB = 0x1d, /**< Timer 4 Compare Value LSB */
MKW2XDM_T4CMP_MSB = 0x1e, /**< Timer 4 Compare Value MSB */
MKW2XDM_T4CMP_USB = 0x1f, /**< Timer 4 Compare Value USB */
MKW2XDM_PLL_INT0 = 0x20, /**< PLL Integer Value for PAN0 */
MKW2XDM_PLL_FRAC0_LSB = 0x21, /**< PLL Frequency Fractional Value for PAN0 */
MKW2XDM_PLL_FRAC0_MSB = 0x22, /**< PLL Frequency Fractional Value for PAN0 */
MKW2XDM_PA_PWR = 0x23, /**< PA Power Control (PA_PWR) */
MKW2XDM_SEQ_STATE = 0x24, /**< Sequence Manager State */
MKW2XDM_LQI_VALUE = 0x25, /**< Link Quality Indicator */
MKW2XDM_RSSI_CCA_CNT = 0x26, /**< RSSI CCA CNT */
MKW2XDM_OVERWRITE_VER = 0x3b, /**< Overwrite Version Number */
MKW2XDM_CLK_OUT_CTRL = 0x3c, /**< CLK_OUT Control */
MKW2XDM_PWR_MODES = 0x3d, /**< Power Modes */
MKW2XDM_IAR_INDEX = 0x3e, /**< IAR Index */
MKW2XDM_IAR_DATA = 0x3f, /**< IAR Data */
};
#define MKW2XDM_IRQSTS1_RX_FRM_PEND (1 << 7)
#define MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ (1 << 6)
#define MKW2XDM_IRQSTS1_FILTERFAIL_IRQ (1 << 5)
#define MKW2XDM_IRQSTS1_RXWTRMRKIRQ (1 << 4)
#define MKW2XDM_IRQSTS1_CCAIRQ (1 << 3)
#define MKW2XDM_IRQSTS1_RXIRQ (1 << 2)
#define MKW2XDM_IRQSTS1_TXIRQ (1 << 1)
#define MKW2XDM_IRQSTS1_SEQIRQ (1 << 0)
#define MKW2XDM_IRQSTS2_CRCVALID (1 << 7)
#define MKW2XDM_IRQSTS2_CCA (1 << 6)
#define MKW2XDM_IRQSTS2_SRCADDR (1 << 5)
#define MKW2XDM_IRQSTS2_PI (1 << 4)
#define MKW2XDM_IRQSTS2_TMRSTATUS (1 << 3)
#define MKW2XDM_IRQSTS2_PB_ERR_IRQ (1 << 1)
#define MKW2XDM_IRQSTS2_WAKE_IRQ (1 << 0)
#define MKW2XDM_IRQSTS3_TMR4MSK (1 << 7)
#define MKW2XDM_IRQSTS3_TMR3MSK (1 << 6)
#define MKW2XDM_IRQSTS3_TMR2MSK (1 << 5)
#define MKW2XDM_IRQSTS3_TMR1MSK (1 << 4)
#define MKW2XDM_IRQSTS3_TMR4IRQ (1 << 3)
#define MKW2XDM_IRQSTS3_TMR3IRQ (1 << 2)
#define MKW2XDM_IRQSTS3_TMR2IRQ (1 << 1)
#define MKW2XDM_IRQSTS3_TMR1IRQ (1 << 0)
#define MKW2XDM_PHY_CTRL1_TMRTRIGEN (1 << 7)
#define MKW2XDM_PHY_CTRL1_SLOTTED (1 << 6)
#define MKW2XDM_PHY_CTRL1_CCABFRTX (1 << 5)
#define MKW2XDM_PHY_CTRL1_RXACKRQD (1 << 4)
#define MKW2XDM_PHY_CTRL1_AUTOACK (1 << 3)
#define MKW2XDM_PHY_CTRL1_XCVSEQ_MASK 0x03u
#define MKW2XDM_PHY_CTRL1_XCVSEQ(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PHY_CTRL1_XCVSEQ_MASK)
#define MKW2XDM_PHY_CTRL2_CRC_MSK (1 << 7)
#define MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK (1 << 6)
#define MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK (1 << 5)
#define MKW2XDM_PHY_CTRL2_RX_WMRK_MSK (1 << 4)
#define MKW2XDM_PHY_CTRL2_CCAMSK (1 << 3)
#define MKW2XDM_PHY_CTRL2_RXMSK (1 << 2)
#define MKW2XDM_PHY_CTRL2_TXMSK (1 << 1)
#define MKW2XDM_PHY_CTRL2_SEQMSK (1 << 0)
#define MKW2XDM_PHY_CTRL3_TMR4CMP_EN (1 << 7)
#define MKW2XDM_PHY_CTRL3_TMR3CMP_EN (1 << 6)
#define MKW2XDM_PHY_CTRL3_TMR2CMP_EN (1 << 5)
#define MKW2XDM_PHY_CTRL3_TMR1CMP_EN (1 << 4)
#define MKW2XDM_PHY_CTRL3_PB_ERR_MSK (1 << 1)
#define MKW2XDM_PHY_CTRL3_WAKE_MSK (1 << 0)
#define MKW2XDM_RX_FRM_LENGTH_MASK 0x7Fu
#define MKW2XDM_PHY_CTRL4_TRCV_MSK (1 << 7)
#define MKW2XDM_PHY_CTRL4_TC3TMOUT (1 << 6)
#define MKW2XDM_PHY_CTRL4_PANCORDNTR0 (1 << 5)
#define MKW2XDM_PHY_CTRL4_CCATYPE_MASK 0x18u
#define MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT 3
#define MKW2XDM_PHY_CTRL4_CCATYPE(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT))&MKW2XDM_PHY_CTRL4_CCATYPE_MASK)
#define MKW2XDM_PHY_CTRL4_TMRLOAD (1 << 2)
#define MKW2XDM_PHY_CTRL4_PROMISCUOUS (1 << 1)
#define MKW2XDM_PHY_CTRL4_TC2PRIME_EN (1 << 0)
#define MKW2XDM_SRC_CTRL_INDEX_MASK 0xF0u
#define MKW2XDM_SRC_CTRL_INDEX_SHIFT 4
#define MKW2XDM_SRC_CTRL_ACK_FRM_PND (1 << 3)
#define MKW2XDM_SRC_CTRL_SRCADDR_EN (1 << 2)
#define MKW2XDM_SRC_CTRL_INDEX_EN (1 << 1)
#define MKW2XDM_SRC_CTRL_INDEX_DISABLE (1 << 0)
#define MKW2XDM_PLL_INT0_MASK 0x1Fu
#define MKW2XDM_PLL_INT0_VAL(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PLL_INT0_MASK)
#define MKW2XDM_PA_PWR_MASK 0x1Fu
#define MKW2XDM_PA_PWR(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PA_PWR_MASK)
#define MKW2XDM_CLK_OUT_EXTEND (1 << 7)
#define MKW2XDM_CLK_OUT_HIZ (1 << 6)
#define MKW2XDM_CLK_OUT_SR (1 << 5)
#define MKW2XDM_CLK_OUT_DS (1 << 4)
#define MKW2XDM_CLK_OUT_EN (1 << 3)
#define MKW2XDM_CLK_OUT_DIV_MASK 0x03u
#define MKW2XDM_CLK_OUT_DIV(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_CLK_OUT_DIV_MASK)
#define MKW2XDM_PWR_MODES_XTAL_READY (1 << 5)
#define MKW2XDM_PWR_MODES_XTALEN (1 << 4)
#define MKW2XDM_PWR_MODES_AUTODOZE (1 << 1)
#define MKW2XDM_PWR_MODES_PMC_MODE (1 << 0)
enum mkw2xdrf_iregister {
MKW2XDMI_PART_ID = 0x00, /**< Part Identification */
MKW2XDMI_XTAL_TRIM = 0x01, /**< XTAL 32 MHz Trim */
MKW2XDMI_MACPANID0_LSB = 0x03, /**< MAC PAN ID for PAN0 */
MKW2XDMI_MACPANID0_MSB = 0x04, /**< MAC PAN ID for PAN0 */
MKW2XDMI_MACSHORTADDRS0_LSB = 0x05, /**< MAC Short Address for PAN0 */
MKW2XDMI_MACSHORTADDRS0_MSB = 0x06, /**< MAC Short Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_0 = 0x07, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_1 = 0x08, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_2 = 0x09, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_3 = 0x0a, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_4 = 0x0b, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_5 = 0x0c, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_6 = 0x0d, /**< MAC Long Address for PAN0 */
MKW2XDMI_MACLONGADDRS0_7 = 0x0e, /**< MAC Long Address for PAN0 */
MKW2XDMI_RX_FRAME_FILTER = 0x0f, /**< Receive Frame Filter */
MKW2XDMI_PLL_INT1 = 0x10, /**< Frequency Integer for PAN1 */
MKW2XDMI_PLL_FRAC1_LSB = 0x11, /**< Frequency Fractional Value for PAN1 */
MKW2XDMI_PLL_FRAC1_MSB = 0x12, /**< Frequency Fractional Value for PAN1 */
MKW2XDMI_MACPANID1_LSB = 0x13, /**< Frequency Fractional Value for PAN1 */
MKW2XDMI_MACPANID1_MSB = 0x14, /**< Frequency Fractional Value for PAN1 */
MKW2XDMI_MACSHORTADDRS1_LSB = 0x15, /**< MAC Short Address for PAN1 */
MKW2XDMI_MACSHORTADDRS1_MSB = 0x16, /**< MAC Short Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_0 = 0x17, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_1 = 0x18, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_2 = 0x19, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_3 = 0x1a, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_4 = 0x1b, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_5 = 0x1c, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_6 = 0x1d, /**< MAC Long Address for PAN1 */
MKW2XDMI_MACLONGADDRS1_7 = 0x1e, /**< MAC Long Address for PAN1 */
MKW2XDMI_DUAL_PAN_CTRL = 0x1f, /**< Dual PAN Control */
MKW2XDMI_DUAL_PAN_DWELL = 0x20, /**< Channel Frequency Dwell Time */
MKW2XDMI_DUAL_PAN_STS = 0x21, /**< Dual PAN Status */
MKW2XDMI_CCA1_THRESH = 0x22, /**< Clear Channel Assessment 1 Threshold */
MKW2XDMI_CCA1_ED_OFFSET_COMP = 0x23, /**< Clear Channel Assessment / ED Offset Computation */
MKW2XDMI_LQI_OFFSET_COMP = 0x24, /**< LQI Offset Computation */
MKW2XDMI_CCA_CTRL = 0x25, /**< CCA Control */
MKW2XDMI_CCA2_CORR_PEAKS = 0x26, /**< Clear Channel Assessment 2 Threshold Peak Compare */
MKW2XDMI_CCA2_THRESH = 0x27, /**< Clear Channel Assessment 2 Threshold */
MKW2XDMI_GPIO_DATA = 0x2a, /**< GPIO Data */
MKW2XDMI_GPIO_DIR = 0x2b, /**< GPIO Direction Control */
MKW2XDMI_GPIO_PUL_EN = 0x2c, /**< GPIO Pullup Enable */
MKW2XDMI_GPIO_SEL = 0x2d, /**< GPIO Pullup Select */
MKW2XDMI_GPIO_DS = 0x2e, /**< GPIO Drive Strength */
MKW2XDMI_ANT_PAD_CTRL = 0x30, /**< Antenna Control */
MKW2XDMI_MISC_PAD_CTRL = 0x31, /**< Miscellaneous Pad Control */
MKW2XDMI_ANT_AGC_CTRL = 0x51, /**< Antenna AGC and FAD Control */
MKW2XDMI_LPPS_CTRL = 0x56, /**< LPPS_CTRL */
};
#define MKW2XDMI_PART_ID_MANUF_ID_MASK 0x60u
#define MKW2XDMI_PART_ID_VERSION_MASK 0x1Cu
#define MKW2XDMI_PART_ID_MASK_SET_MASK 0x07u
#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK 0xC0u
#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT 6
#define MKW2XDMI_RX_FRAME_FILTER_FRM_VER(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT))&MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK)
#define MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS (1 << 5)
#define MKW2XDMI_RX_FRAME_FILTER_NS_FT (1 << 4)
#define MKW2XDMI_RX_FRAME_FILTER_CMD_FT (1 << 3)
#define MKW2XDMI_RX_FRAME_FILTER_ACK_FT (1 << 2)
#define MKW2XDMI_RX_FRAME_FILTER_DATA_FT (1 << 1)
#define MKW2XDMI_RX_FRAME_FILTER_BEACON_FT (1 << 0)
#define MKW2XDMI_PLL_INT1_MASK 0x1Fu
#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK 0xF0
#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT 4
#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT))&MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK)
#define MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK (1 << 3)
#define MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1 (1 << 2)
#define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO (1 << 1)
#define MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK (1 << 0)
#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1 (1 << 7)
#define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0 (1 << 6)
#define MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK 0x3Fu
#define MKW2XDMI_CCA_CTRL_AGC_FRZ_EN (1 << 6)
#define MKW2XDMI_CCA_CTRL_CONT_RSSI_EN (1 << 5)
#define MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR (1 << 4)
#define MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR (1 << 3)
#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI (1 << 2)
#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED (1 << 1)
#define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1 (1 << 0)
#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK 0x70u
#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT 4
#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT))&MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK)
#define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK 0x0Fu
#define MKW2XDMI_GPIO_DATA8 (1 << 7)
#define MKW2XDMI_GPIO_DATA7 (1 << 6)
#define MKW2XDMI_GPIO_DATA6 (1 << 5)
#define MKW2XDMI_GPIO_DATA5 (1 << 4)
#define MKW2XDMI_GPIO_DATA4 (1 << 3)
#define MKW2XDMI_GPIO_DATA3 (1 << 2)
#define MKW2XDMI_GPIO_DATA2 (1 << 1)
#define MKW2XDMI_GPIO_DATA1 (1 << 0)
#define MKW2XDMI_GPIO_DIR8 (1 << 7)
#define MKW2XDMI_GPIO_DIR7 (1 << 6)
#define MKW2XDMI_GPIO_DIR6 (1 << 5)
#define MKW2XDMI_GPIO_DIR5 (1 << 4)
#define MKW2XDMI_GPIO_DIR4 (1 << 3)
#define MKW2XDMI_GPIO_DIR3 (1 << 2)
#define MKW2XDMI_GPIO_DIR2 (1 << 1)
#define MKW2XDMI_GPIO_DIR1 (1 << 0)
#define MKW2XDMI_GPIO_PUL_EN8 (1 << 7)
#define MKW2XDMI_GPIO_PUL_EN7 (1 << 6)
#define MKW2XDMI_GPIO_PUL_EN6 (1 << 5)
#define MKW2XDMI_GPIO_PUL_EN5 (1 << 4)
#define MKW2XDMI_GPIO_PUL_EN4 (1 << 3)
#define MKW2XDMI_GPIO_PUL_EN3 (1 << 2)
#define MKW2XDMI_GPIO_PUL_EN2 (1 << 1)
#define MKW2XDMI_GPIO_PUL_EN1 (1 << 0)
#define MKW2XDMI_GPIO_PUL_SEL8 (1 << 7)
#define MKW2XDMI_GPIO_PUL_SEL7 (1 << 6)
#define MKW2XDMI_GPIO_PUL_SEL6 (1 << 5)
#define MKW2XDMI_GPIO_PUL_SEL5 (1 << 4)
#define MKW2XDMI_GPIO_PUL_SEL4 (1 << 3)
#define MKW2XDMI_GPIO_PUL_SEL3 (1 << 2)
#define MKW2XDMI_GPIO_PUL_SEL2 (1 << 1)
#define MKW2XDMI_GPIO_PUL_SEL1 (1 << 0)
#define MKW2XDMI_GPIO_DS8 (1 << 7)
#define MKW2XDMI_GPIO_DS7 (1 << 6)
#define MKW2XDMI_GPIO_DS6 (1 << 5)
#define MKW2XDMI_GPIO_DS5 (1 << 4)
#define MKW2XDMI_GPIO_DS4 (1 << 3)
#define MKW2XDMI_GPIO_DS3 (1 << 2)
#define MKW2XDMI_GPIO_DS2 (1 << 1)
#define MKW2XDMI_GPIO_DS1 (1 << 0)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3 (1 << 7)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL2 (1 << 6)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL1 (1 << 5)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL0 (1 << 4)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_CTRLMODE (1 << 3)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_HZ (1 << 2)
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK 0x03u
#define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK)
#define MKW2XDMI_MISC_PAD_CTRL_MISO_HIZ_EN (1 << 3)
#define MKW2XDMI_MISC_PAD_CTRL_IRQ_B_OD (1 << 2)
#define MKW2XDMI_MISC_PAD_CTRL_NON_GPIO_DS (1 << 1)
#define MKW2XDMI_MISC_PAD_CTRL_ANTX_CURR (1 << 0)
#define MKW2XDMI_ANT_AGC_CTRL_SNF_EN (1 << 7)
#define MKW2XDMI_ANT_AGC_CTRL_AGC_EN (1 << 6)
#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK 0x30u
#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT 4
#define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT))&MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK)
#define MKW2XDMI_ANT_AGC_CTRL_ANTX (1 << 1)
#define MKW2XDMI_ANT_AGC_CTRL_AD_EN (1 << 0)
#define MKW2XDMI_LPPS_CTRL_LPPS_EN (1 << 0)
#ifdef __cplusplus
}
#endif
#endif
/** @} */

118
drivers/kw2xrf/include/kw2xrf_spi.h

@ -0,0 +1,118 @@
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup drivers_kw2xrf
* @{
* @file kw2xrf_spi.h
* @brief Definition of KW2XRF SPI functions
*
* @author Johann Fischer <j.fischer@phytec.de>
*/
#ifndef KW2XRF_SPI_H
#define KW2XRF_SPI_H
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "periph/spi.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief SPI interface initialization
* @param[in] spi SPI bus the device is connected to
* @param[in] spi_speed SPI speed to use
* @param[in] cs_pin GPIO pin connected to chip select
*
* @return 0 on success
* @return -1 on error
*/
int kw2xrf_spi_init(spi_t spi, spi_speed_t spi_speed,
gpio_t cs_pin);
/**
* @brief Writes a byte to the kw2xrf register.
*
* @param[in] addr Address of the register to write.
* @param[in] value The value to write in the register.
*/
void kw2xrf_write_dreg(uint8_t addr, uint8_t value);
/**
* @brief Reads a byte from the kw2xrf register.
*
* @param[in] addr Address of the register to read.
* @return Value of the register.
*/
uint8_t kw2xrf_read_dreg(uint8_t addr);
/**
* @brief Writes to a byte from the kw2xrf indirect register.
*
* @param[in] addr Address of the register to write into.
* @param[in] value Value that shall be written.
*/
void kw2xrf_write_ireg(uint8_t addr, uint8_t value);
/**
* @brief Reads a byte from the kw2xrf indirect register.
*
* @param[in] addr Address of the register to read.
*
* @return value in the register
*/
uint8_t kw2xrf_read_ireg(uint8_t addr);
/**
* @brief Writes to kw2xrf indirect registers.
*
* @param[in] addr Address of the register to write into.
* @param[in] buf Value that shall be written.
* @param[in] length Length of the register.
*/
void kw2xrf_write_iregs(uint8_t addr, uint8_t *buf, uint8_t length);
/**
* @brief Reads a byte from the kw2xrf indirect register.
*
* @param[in] addr Address of the register to read.
* @param[in] buf Buffer, where the content of the reg shall be written to.
* @param[in] length Length of the register.
*/
void kw2xrf_read_iregs(uint8_t addr, uint8_t *buf, uint8_t length);
/**
* @brief Writes multiple bytes to the kw2xrf fifo.
*
* @param[in] data A buffer with the value to write to the fifo.
* @param[in] data_length The count of bytes which should be written.
*
* @return number of bytes written.
*/
void kw2xrf_write_fifo(uint8_t *data, uint8_t data_length);
/**
* @brief Reads multiple bytes from the kw2xrf fifo.
*
* @param[out] data A buffer to store the value of the fifo.
* @param[in] data_length The count of bytes which should be read.
*
* @return number of bytes read.
*/
void kw2xrf_read_fifo(uint8_t *data, uint8_t data_length);
#ifdef __cplusplus
}
#endif
#endif
/** @} */

1173
drivers/kw2xrf/kw2xrf.c

File diff suppressed because it is too large Load Diff

153
drivers/kw2xrf/kw2xrf_spi.c

@ -0,0 +1,153 @@
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup drivers_kw2xrf
* @{
* @file kw2xrf_spi.c
* @brief Implementation of SPI-functions for the kw2xrf driver
*
* @author Johann Fischer <j.fischer@phytec.de>
* @author Jonas Remmert <j.remmert@phytec.de>
* @}
*/
#include "kw2xrf.h"
#include "kw2xrf_reg.h"
#include "kw2xrf_spi.h"
#include "periph/spi.h"
#include "periph/gpio.h"
#include "cpu-conf.h"
#include "irq.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define KW2XRF_IBUF_LENGTH 9
static uint8_t ibuf[KW2XRF_IBUF_LENGTH];
/** Set up in kw2xrf_spi_init during initialization */
static gpio_t kw2xrf_cs_pin;
static spi_t kw2xrf_spi;
void kw2xrf_spi_transfer_head(void)
{
#if KW2XRF_SHARED_SPI
spi_acquire(kw2xrf_spi);
gpio_clear(kw2xrf_cs_pin);
#endif
}
void kw2xrf_spi_transfer_tail(void)
{
#if KW2XRF_SHARED_SPI
gpio_set(kw2xrf_cs_pin);
spi_release(kw2xrf_spi);
#endif
}
int kw2xrf_spi_init(spi_t spi, spi_speed_t spi_speed,
gpio_t cs_pin)
{
int res;
kw2xrf_cs_pin = cs_pin; /**< for later reference */
kw2xrf_spi = spi;
#if KW2XRF_SHARED_SPI
spi_acquire(kw2xrf_spi);
#endif
res = spi_init_master(kw2xrf_spi, SPI_CONF_FIRST_RISING, spi_speed);
#if KW2XRF_SHARED_SPI
spi_release(kw2xrf_spi);
gpio_init_out(kw2xrf_cs_pin, GPIO_NOPULL);
gpio_set(kw2xrf_cs_pin);
#endif
if (res < 0) {
DEBUG("kw2xrf_spi_init: error initializing SPI_%i device (code %i)\n",
kw2xrf_spi, res);
return -1;
}
return 0;
}
void kw2xrf_write_dreg(uint8_t addr, uint8_t value)
{
kw2xrf_spi_transfer_head();
spi_transfer_reg(kw2xrf_spi, addr, value, NULL);
kw2xrf_spi_transfer_tail();
return;
}
uint8_t kw2xrf_read_dreg(uint8_t addr)
{
uint8_t value;
kw2xrf_spi_transfer_head();
spi_transfer_reg(kw2xrf_spi, (addr | MKW2XDRF_REG_READ),
0x0, (char *)&value);
kw2xrf_spi_transfer_tail();
return value;
}
void kw2xrf_write_iregs(uint8_t addr, uint8_t *buf, uint8_t length)
{
if (length > (KW2XRF_IBUF_LENGTH - 1)) {
length = KW2XRF_IBUF_LENGTH - 1;
}
ibuf[0] = addr;
for (uint8_t i = 0; i < length; i++) {
ibuf[i + 1] = buf[i];
}
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDM_IAR_INDEX,
(char *)ibuf, NULL, length + 1);
kw2xrf_spi_transfer_tail();
return;
}
void kw2xrf_read_iregs(uint8_t addr, uint8_t *buf, uint8_t length)
{
if (length > (KW2XRF_IBUF_LENGTH - 1)) {
length = KW2XRF_IBUF_LENGTH - 1;
}
ibuf[0] = addr;
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDM_IAR_INDEX | MKW2XDRF_REG_READ,
(char *)ibuf, (char *)ibuf, length + 1);
kw2xrf_spi_transfer_tail();
for (uint8_t i = 0; i < length; i++) {
buf[i] = ibuf[i + 1];
}
return;
}
void kw2xrf_write_fifo(uint8_t *data, uint8_t length)
{
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDRF_BUF_WRITE,
(char *)data, NULL, length);
kw2xrf_spi_transfer_tail();
}
void kw2xrf_read_fifo(uint8_t *data, uint8_t length)
{
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDRF_BUF_READ, NULL,
(char *)data, length);
kw2xrf_spi_transfer_tail();
}
/** @} */

2
sys/include/net/ng_netconf.h

@ -117,6 +117,8 @@ typedef enum {
* @note not all transceivers may support this interrupt
*/
NETCONF_OPT_TX_END_IRQ,
NETCONF_OPT_AUTOCCA, /**< en/disable to check automatically
before sending the channel is clear. */
/* add more options if needed */
} ng_netconf_opt_t;

51
tests/driver_kw2xrf/Makefile

@ -0,0 +1,51 @@
APPLICATION = driver_kw2xrf
include ../Makefile.tests_common
FEATURES_REQUIRED = periph_spi periph_gpio
BOARD_INSUFFICIENT_RAM := stm32f0discovery
ifneq (,$(filter pba-d-01-kw2x,$(BOARD)))
export KWRF_SPI ?= SPI_1
export KWRF_CS ?= GPIO_24
export KWRF_INT ?= GPIO_23
export KWRF_SPI_SPEED ?= SPI_SPEED_10MHZ
export KW2XRF_SHARED_SPI ?= 0
endif
USEMODULE += ng_netif
USEMODULE += ng_nomac
USEMODULE += ng_pktdump
USEMODULE += uart0
USEMODULE += shell
USEMODULE += shell_commands
USEMODULE += ps
USEMODULE += kw2xrf
CFLAGS += -DDEVELHELP
ifneq (,$(KWRF_SHARED_SPI))
CFLAGS += -DKW2XRF_SHARED_SPI=$(DKW2XRF_SHARED_SPI)
else
CFLAGS += -DKW2XRFD_SHARED_SPI=1 # activate spi-lock
endif
ifneq (,$(KWRF_SPI))
CFLAGS += -DKWRF_SPI=$(KWRF_SPI)
else
CFLAGS += -DKWRF_SPI=SPI_0 # set default
endif
ifneq (,$(KWRF_CS))
CFLAGS += -DKWRF_CS=$(KWRF_CS)
else
CFLAGS += -DKWRF_CS=GPIO_0 # set default
endif
ifneq (,$(KWRF_INT))
CFLAGS += -DKWRF_INT=$(KWRF_INT)
else
CFLAGS += -DKWRF_INT=GPIO_1 # set default
endif
ifneq (,$(KWRF_SPI_SPEED))
CFLAGS += -DKWRF_SPI_SPEED=$(KWRF_SPI_SPEED)
endif
include $(RIOTBASE)/Makefile.include

12
tests/driver_kw2xrf/README.md

@ -0,0 +1,12 @@
# About
This is a manual test application for testing the KW2xrf network device driver.
For running this test, you need to connect/configure the following pins of your
radio device:
- SPI DEV
- CS (chip select)
- INT (external interrupt)
# Usage
For testing the radio driver you can use the netif and txtsnd shell commands
that are included in this application.

1
tests/driver_kw2xrf/auto_init_ng_netif/Makefile

@ -0,0 +1 @@
include $(RIOTBASE)/Makefile.base

86
tests/driver_kw2xrf/auto_init_ng_netif/netif_app.c

@ -0,0 +1,86 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup tests
* @{
*
* @file
* @brief Test application for KW2xRF network device driver
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Jonas Remmert <j.remmert@phytec.de>
*
* @}
*/
#include <stdio.h>
#include "kernel.h"
#include "kw2xrf.h"
#include "net/ng_nomac.h"
#include "net/ng_netbase.h"
/* make sure the SPI port and the needed GPIO pins are defined */
#ifndef KWRF_SPI
#error "SPI not defined"
#endif
#ifndef KWRF_CS
#error "Chip select pin not defined"
#endif
#ifndef KWRF_INT
#error "Interrupt pin not defined"
#endif
#ifndef KWRF_SPI_SPEED
#define KWRF_SPI_SPEED (SPI_SPEED_10MHZ)
#endif
/**
* @brief MAC layer stack configuration
* @{
*/
#define STACKSIZE (KERNEL_CONF_STACKSIZE_MAIN)
#define PRIO (0)
/** @} */
/**
* @brief Allocate the KW2XRF device descriptor
*/
static kw2xrf_t dev;
/**
* @brief Stack for the nomac thread
*/
static char nomac_stack[STACKSIZE];
void auto_init_ng_netif(void)
{
kernel_pid_t iface;
int res;
/* initialize the KW2XRF device */
printf("Initializing the KW2XRF radio at SPI_%i... \n", KWRF_SPI);
res = kw2xrf_init(&dev, KWRF_SPI, KWRF_SPI_SPEED,
KWRF_CS, KWRF_INT);
if (res < 0) {
puts("Error initializing KW2XRF radio device");
return;
}
/* start MAC layer */
puts("Starting the NOMAC layer on top of the driver");
iface = ng_nomac_init(nomac_stack, sizeof(nomac_stack), PRIO, "kw2xrf",
(ng_netdev_t *)(&dev));
if (iface <= KERNEL_PID_UNDEF) {
puts("Error initializing MAC layer");
return;
}
}

72
tests/driver_kw2xrf/main.c

@ -0,0 +1,72 @@
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @{
* @ingroup tests
* @file
* @brief Test application for KW2x network device driver
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Jonas Remmert <j.remmert@phytec.de>
* @}
*/
#include <stdio.h>
#include "shell.h"
#include "shell_commands.h"
#include "posix_io.h"
#include "board_uart0.h"
#include "net/ng_netbase.h"
#include "net/ng_pktdump.h"
/**
* @brief Buffer size used by the shell
*/
#define SHELL_BUFSIZE (64U)
/**
* @brief Read chars from STDIO
*/
int shell_read(void)
{
char c = 0;
(void) posix_read(uart0_handler_pid, &c, 1);
return c;
}
/**
* @brief Write chars to STDIO
*/
void shell_put(int c)
{
putchar((char)c);
}
int main(void)
{
shell_t shell;
ng_netreg_entry_t dump;
puts("KW2XRF device driver test");
/* register the pktdump thread */
puts("Register the packet dump thread for NG_NETTYPE_UNDEF packets");
dump.pid = ng_pktdump_getpid();
dump.demux_ctx = NG_NETREG_DEMUX_CTX_ALL;
ng_netreg_register(NG_NETTYPE_UNDEF, &dump);
/* start the shell */
puts("Initialization successful - starting the shell now");
(void) posix_open(uart0_handler_pid, 0);
shell_init(&shell, NULL, SHELL_BUFSIZE, shell_read, shell_put);
shell_run(&shell);
return 0;
}
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