Browse Source

Merge pull request #4780 from haukepetersen/opt_periph_spi2

drivers/spi: reworked SPI driver interface
pr/spi.typo
Peter Kietzmann 6 years ago committed by GitHub
parent
commit
513b20ffd3
  1. 25
      boards/airfy-beacon/include/periph_conf.h
  2. 33
      boards/arduino-due/include/periph_conf.h
  3. 79
      boards/arduino-due/include/sdcard_spi_params.h
  4. 14
      boards/arduino-due/include/w5100_params.h
  5. 30
      boards/arduino-zero/include/periph_conf.h
  6. 27
      boards/cc2538dk/include/periph_conf.h
  7. 4
      boards/fox/include/board.h
  8. 47
      boards/fox/include/periph_conf.h
  9. 86
      boards/frdm-k64f/include/periph_conf.h
  10. 25
      boards/iotlab-a8-m3/include/periph_conf.h
  11. 8
      boards/iotlab-common/include/board_common.h
  12. 23
      boards/iotlab-common/include/periph_conf_common.h
  13. 2
      boards/iotlab-m3/include/board.h
  14. 33
      boards/iotlab-m3/include/periph_conf.h
  15. 77
      boards/limifrog-v1/include/periph_conf.h
  16. 74
      boards/maple-mini/include/periph_conf.h
  17. 1
      boards/msb-430/Makefile.features
  18. 2
      boards/msb-430/include/periph_conf.h
  19. 2
      boards/msb-430h/include/periph_conf.h
  20. 4
      boards/msba2/include/periph_conf.h
  21. 2
      boards/msbiot/include/board.h
  22. 61
      boards/msbiot/include/periph_conf.h
  23. 5
      boards/mulle/board.c
  24. 30
      boards/mulle/include/board.h
  25. 1
      boards/mulle/include/lis3dh_params.h
  26. 229
      boards/mulle/include/periph_conf.h
  27. 1
      boards/nrf52dk/Makefile.features
  28. 15
      boards/nrf52dk/include/periph_conf.h
  29. 32
      boards/nrf6310/include/periph_conf.h
  30. 1
      boards/nucleo-f072/Makefile.features
  31. 40
      boards/nucleo-f072/include/periph_conf.h
  32. 1
      boards/nucleo-f091/Makefile.features
  33. 42
      boards/nucleo-f091/include/periph_conf.h
  34. 73
      boards/nucleo-f103/include/periph_conf.h
  35. 91
      boards/nucleo-f207/include/periph_conf.h
  36. 90
      boards/nucleo-f303/include/periph_conf.h
  37. 59
      boards/nucleo-f334/include/periph_conf.h
  38. 60
      boards/nucleo-f401/include/periph_conf.h
  39. 60
      boards/nucleo-f446/include/periph_conf.h
  40. 58
      boards/nucleo-l1/include/periph_conf.h
  41. 7
      boards/opencm9-04/include/periph_conf.h
  42. 24
      boards/openmote-cc2538/include/periph_conf.h
  43. 4
      boards/pba-d-01-kw2x/include/board.h
  44. 123
      boards/pba-d-01-kw2x/include/periph_conf.h
  45. 32
      boards/pca10005/include/periph_conf.h
  46. 1
      boards/remote-common/include/periph_common.h
  47. 7
      boards/remote-pa/include/board.h
  48. 42
      boards/remote-pa/include/periph_conf.h
  49. 8
      boards/remote-reva/include/board.h
  50. 43
      boards/remote-reva/include/periph_conf.h
  51. 10
      boards/remote-revb/include/board.h
  52. 29
      boards/remote-revb/include/periph_conf.h
  53. 27
      boards/saml21-xpro/include/periph_conf.h
  54. 4
      boards/samr21-xpro/include/board.h
  55. 57
      boards/samr21-xpro/include/periph_conf.h
  56. 36
      boards/sodaq-autonomo/include/periph_conf.h
  57. 1
      boards/spark-core/Makefile.features
  58. 4
      boards/spark-core/include/board.h
  59. 47
      boards/spark-core/include/periph_conf.h
  60. 73
      boards/stm32f0discovery/include/periph_conf.h
  61. 85
      boards/stm32f3discovery/include/periph_conf.h
  62. 88
      boards/stm32f4discovery/include/periph_conf.h
  63. 4
      boards/telosb/include/board.h
  64. 2
      boards/telosb/include/periph_conf.h
  65. 35
      boards/udoo/include/periph_conf.h
  66. 17
      boards/weio/include/periph_conf.h
  67. 2
      boards/wsn430-common/include/periph_conf.h
  68. 1
      boards/wsn430-v1_3b/Makefile.features
  69. 1
      boards/wsn430-v1_4/Makefile.features
  70. 32
      boards/yunjia-nrf51822/include/periph_conf.h
  71. 4
      boards/z1/include/board.h
  72. 2
      boards/z1/include/periph_conf.h
  73. 5
      cpu/atmega1281/cpu.c
  74. 5
      cpu/atmega2560/cpu.c
  75. 5
      cpu/atmega328p/cpu.c
  76. 38
      cpu/atmega_common/include/periph_cpu_common.h
  77. 121
      cpu/atmega_common/periph/spi.c
  78. 3
      cpu/cc2538/cpu.c
  79. 40
      cpu/cc2538/include/cc2538_ssi.h
  80. 1
      cpu/cc2538/include/cpu_conf.h
  81. 56
      cpu/cc2538/include/periph_cpu.h
  82. 376
      cpu/cc2538/periph/spi.c
  83. 8
      cpu/cc26x0/cpu.c
  84. 3
      cpu/ezr32wg/cpu.c
  85. 3
      cpu/k60/cpu.c
  86. 3
      cpu/k64f/cpu.c
  87. 1
      cpu/kinetis_common/Makefile.include
  88. 12
      cpu/kinetis_common/dist/calc_spi_scalers/Makefile
  89. 242
      cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
  90. 60
      cpu/kinetis_common/include/periph_cpu.h
  91. 1632
      cpu/kinetis_common/periph/spi.c
  92. 3
      cpu/kw2x/cpu.c
  93. 4
      cpu/lm4f120/cpu.c
  94. 3
      cpu/lpc11u34/cpu.c
  95. 39
      cpu/lpc11u34/include/periph_cpu.h
  96. 275
      cpu/lpc11u34/periph/spi.c
  97. 3
      cpu/lpc1768/cpu.c
  98. 17
      cpu/lpc2387/include/periph_cpu.h
  99. 230
      cpu/lpc2387/periph/spi.c
  100. 40
      cpu/msp430fxyz/include/periph_cpu.h
  101. Some files were not shown because too many files have changed in this diff Show More

25
boards/airfy-beacon/include/periph_conf.h

@ -1,9 +1,9 @@
/*
* Copyright (C) 2014 Christian Mehlis <mehlis@inf.fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -83,15 +83,16 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
/* SPI_0 device configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_MOSI 13
#define SPI_0_PIN_MISO 14
#define SPI_0_PIN_SCK 15
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 15,
.mosi = 13,
.miso = 14
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

33
boards/arduino-due/include/periph_conf.h

@ -88,27 +88,18 @@ static const uart_conf_t uart_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_SPI0));
#define SPI_0_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_SPI0));
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_IRQ_PRIO 1
/* SPI 0 pin configuration */
#define SPI_0_MISO_PIN PIO_PA25A_SPI0_MISO
#define SPI_0_MOSI_PIN PIO_PA26A_SPI0_MOSI
#define SPI_0_SCK_PIN PIO_PA27A_SPI0_SPCK
#define SPI_0_MISO_PORT PIOA
#define SPI_0_MOSI_PORT PIOA
#define SPI_0_SCK_PORT PIOA
#define SPI_0_MISO_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_MOSI_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
#define SPI_0_SCK_PORT_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_PIOA));
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.id = ID_SPI0,
.clk = GPIO_PIN(PA, 27),
.mosi = GPIO_PIN(PA, 26),
.miso = GPIO_PIN(PA, 25),
.mux = GPIO_MUX_A
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

79
boards/arduino-due/include/sdcard_spi_params.h

@ -0,0 +1,79 @@
/*
* Copyright (C) 2017 Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
* 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_arduino-due
* @{
*
* @file
* @brief SD card configuration for the Arduino due
*
* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef SDCARD_SPI_PARAMS_H
#define SDCARD_SPI_PARAMS_H
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set default configuration parameters for the sdcard_spi driver
* @{
*/
#ifndef SDCARD_SPI_PARAM_SPI
#define SDCARD_SPI_PARAM_SPI (SPI_DEV(0))
#endif
#ifndef SDCARD_SPI_PARAM_CS
#define SDCARD_SPI_PARAM_CS (GPIO_PIN(PA, 29))
#endif
#ifndef SDCARD_SPI_PARAM_CLK
#define SDCARD_SPI_PARAM_CLK (GPIO_PIN(PA, 27))
#endif
#ifndef SDCARD_SPI_PARAM_MOSI
#define SDCARD_SPI_PARAM_MOSI (GPIO_PIN(PA, 26))
#endif
#ifndef SDCARD_SPI_PARAM_MISO
#define SDCARD_SPI_PARAM_MISO (GPIO_PIN(PA, 25))
#endif
#ifndef SDCARD_SPI_PARAM_POWER
#define SDCARD_SPI_PARAM_POWER (GPIO_UNDEF)
#endif
#ifndef SDCARD_SPI_PARAM_POWER_AH
/** treated as 'don't care' if SDCARD_SPI_PARAM_POWER is GPIO_UNDEF */
#define SDCARD_SPI_PARAM_POWER_AH (true)
#endif
/** @} */
/**
* @brief sdcard_spi configuration
*/
static const sdcard_spi_params_t sdcard_spi_params[] = {
{
.spi_dev = SDCARD_SPI_PARAM_SPI,
.cs = SDCARD_SPI_PARAM_CS,
.clk = SDCARD_SPI_PARAM_CLK,
.mosi = SDCARD_SPI_PARAM_MOSI,
.miso = SDCARD_SPI_PARAM_MISO,
.power = SDCARD_SPI_PARAM_POWER,
.power_act_high = SDCARD_SPI_PARAM_POWER_AH
},
};
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SDCARD_SPI_PARAMS_H */
/** @} */

14
boards/arduino-due/include/w5100_params.h

@ -28,10 +28,10 @@ extern "C" {
* @{
*/
#ifndef W5100_PARAM_SPI
#define W5100_PARAM_SPI (SPI_0)
#define W5100_PARAM_SPI (SPI_DEV(0))
#endif
#ifndef W5100_PARAM_SPI_SPEED
#define W5100_PARAM_SPI_SPEED (SPI_SPEED_5MHZ)
#ifndef W5100_PARAM_SPI_CLK
#define W5100_PARAM_SPI_CLK (SPI_CLK_5MHZ)
#endif
#ifndef W5100_PARAM_CS
#define W5100_PARAM_CS (GPIO_PIN(2, 29))
@ -46,10 +46,10 @@ extern "C" {
*/
static const w5100_params_t w5100_params[] = {
{
.spi = W5100_PARAM_SPI,
.spi_speed = W5100_PARAM_SPI_SPEED,
.cs = W5100_PARAM_CS,
.evt = W5100_PARAM_EVT
.spi = W5100_PARAM_SPI,
.clk = W5100_PARAM_SPI_CLK,
.cs = W5100_PARAM_CS,
.evt = W5100_PARAM_EVT
},
};
/** @} */

30
boards/arduino-zero/include/periph_conf.h

@ -183,23 +183,21 @@ static const pwm_conf_t pwm_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN 1
/* SPI0 */
#define SPI_0_DEV SERCOM4->SPI
#define SPI_IRQ_0 SERCOM4_IRQn
#define SPI_0_GCLK_ID SERCOM4_GCLK_ID_CORE
/* SPI 0 pin configuration */
#define SPI_0_SCLK GPIO_PIN(PB, 11)
#define SPI_0_SCLK_MUX GPIO_MUX_D
#define SPI_0_MISO GPIO_PIN(PA, 12)
#define SPI_0_MISO_MUX GPIO_MUX_D
#define SPI_0_MISO_PAD SPI_PAD_MISO_0
#define SPI_0_MOSI GPIO_PIN(PB, 10)
#define SPI_0_MOSI_MUX GPIO_MUX_D
#define SPI_0_MOSI_PAD SPI_PAD_MOSI_2_SCK_3
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM4->SPI,
.miso_pin = GPIO_PIN(PA, 12),
.mosi_pin = GPIO_PIN(PB, 10),
.clk_pin = GPIO_PIN(PB, 11),
.miso_mux = GPIO_MUX_D,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

27
boards/cc2538dk/include/periph_conf.h

@ -58,7 +58,6 @@ static const timer_conf_t timer_config[] = {
#define TIMER_IRQ_PRIO 1
/** @} */
/**
* @name UART configuration
* @{
@ -112,22 +111,36 @@ static const i2c_conf_t i2c_config[I2C_NUMOF] = {
};
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 1
#define SPI_0_EN 1
static const periph_spi_conf_t spi_config[SPI_NUMOF] = {
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,
.mosi_pin = GPIO_PA4,
.miso_pin = GPIO_PA5,
.sck_pin = GPIO_PA2,
.cs_pin = GPIO_PD0,
},
.cs_pin = GPIO_PD0
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

4
boards/fox/include/board.h

@ -43,8 +43,8 @@ extern "C" {
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 1), \
.int_pin = GPIO_PIN(PORT_C, 2), \
.sleep_pin = GPIO_PIN(PORT_A, 0), \

47
boards/fox/include/periph_conf.h

@ -115,21 +115,42 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
/* SPI 0 device configuration */
#define SPI_0_DEV SPI2
#define SPI_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_B,13)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_B,15)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_B,14)
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

86
boards/frdm-k64f/include/periph_conf.h

@ -147,35 +147,67 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
* @name SPI configuration
*
* Clock configuration values based on the configured 30Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
#define KINETIS_SPI_USE_HW_CS 1
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_FREQ CLOCK_CORECLOCK
/* SPI 0 pin configuration */
#define SPI_0_PORT PORTD
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define SPI_0_AF 2
#define SPI_0_PCS0_PIN 0
#define SPI_0_SCK_PIN 1
#define SPI_0_SOUT_PIN 2
#define SPI_0_SIN_PIN 3
#define SPI_0_PCS0_ACTIVE_LOW 1
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
)
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

25
boards/iotlab-a8-m3/include/periph_conf.h

@ -31,18 +31,19 @@ extern "C" {
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
/* SPI 0 device configuration */
#define SPI_0_DEV SPI2
#define SPI_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_B,13)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_B,14)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_B,15)
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

8
boards/iotlab-common/include/board_common.h

@ -53,10 +53,10 @@ extern "C" {
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 4), \
.int_pin = GPIO_PIN(PORT_C, 4), \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_A, 4), \
.int_pin = GPIO_PIN(PORT_C, 4), \
.sleep_pin = GPIO_PIN(PORT_A, 2), \
.reset_pin = GPIO_PIN(PORT_C, 1)}

23
boards/iotlab-common/include/periph_conf_common.h

@ -159,6 +159,29 @@ static const uart_conf_t uart_config[] = {
#define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
#ifdef __cplusplus
}
#endif

2
boards/iotlab-m3/include/board.h

@ -38,7 +38,7 @@ extern "C" {
* @name Define the interface for the connected flash memory
* @{
*/
#define EXTFLASH_SPI SPI_1
#define EXTFLASH_SPI SPI_DEV(1)
#define EXTFLASH_CS GPIO_PIN(PORT_A,11)
#define EXTFLASH_WRITE GPIO_PIN(PORT_C,6)
#define EXTFLASH_HOLD GPIO_PIN(PORT_C,9)

33
boards/iotlab-m3/include/periph_conf.h

@ -1,9 +1,9 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
@ -31,18 +31,19 @@ extern "C" {
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A,5)
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A,7)
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A,6)
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

77
boards/limifrog-v1/include/periph_conf.h

@ -109,40 +109,53 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @brief SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1 /* Densitron DD-160128FC-1a OLED display; external pins */
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_ISR isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define SPI_0_PORT GPIOA
#define SPI_0_PIN_SCK 5
#define SPI_0_PIN_MOSI 7
#define SPI_0_PIN_MISO 6
#define SPI_0_PIN_AF 5
/* SPI 1 device configuration */
#define SPI_1_DEV SPI3 /* Adesto AT45DB641E data flash */
#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI3EN))
#define SPI_1_IRQ SPI3_IRQn
#define SPI_1_ISR isr_spi3
/* SPI 1 pin configuration */
#define SPI_1_PORT_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
#define SPI_1_PORT GPIOB
#define SPI_1_PIN_SCK 3
#define SPI_1_PIN_MOSI 5
#define SPI_1_PIN_MISO 4
#define SPI_1_PIN_AF 6
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI3,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF6,
.rccmask = RCC_APB1ENR_SPI3EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

74
boards/maple-mini/include/periph_conf.h

@ -163,39 +163,55 @@ static const uart_conf_t uart_config[] = {
#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11) /* D0 */
/** @} */
/**
* @brief Shared SPI clock div table
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
#define SPI_0_BUS_DIV 1
/* SPI 0 pin configuration */
#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5) /* D6 */
#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6) /* D5 */
#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7) /* D4 */
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
#define SPI_1_BUS_DIV 1
/* SPI 1 pin configuration */
#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13) /* D30 */
#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14) /* D29 */
#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15) /* D28 */
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus

1
boards/msb-430/Makefile.features

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

2
boards/msb-430/include/periph_conf.h

@ -75,7 +75,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

2
boards/msb-430h/include/periph_conf.h

@ -77,7 +77,7 @@ extern "C" {
#define SPI_0_EN (1U)
/* SPI configuration */
#define SPI_DEV (USART_0)
#define SPI_BASE (USART_0)
#define SPI_IE (SFR->IE1)
#define SPI_IF (SFR->IFG1)
#define SPI_IE_RX_BIT (1 << 6)

4
boards/msba2/include/periph_conf.h

@ -82,10 +82,12 @@ extern "C" {
/**
* @brief SPI configuration
*
* The SPI implementation is very much fixed, so we don't need to configure
* anything besides the mandatory SPI_NUMOF.
* @{
*/
#define SPI_NUMOF (1)
#define SPI_0_EN (1)
/** @} */
#ifdef __cplusplus

2
boards/msbiot/include/board.h

@ -32,7 +32,7 @@ extern "C" {
* @name Configure connected CC1101 (radio) device
* @{
*/
#define CC110X_SPI SPI_0
#define CC110X_SPI SPI_DEV(0)
#define CC110X_CS GPIO_PIN(PORT_B, 12)
#define CC110X_GDO0 GPIO_PIN(PORT_C, 4)
#define CC110X_GDO1 GPIO_PIN(PORT_A, 6)

61
boards/msbiot/include/periph_conf.h

@ -187,34 +187,43 @@ static const uart_conf_t uart_config[] = {
/** @} */
/**
* @name SPI configuration
* @brief SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
#define SPI_NUMOF 1
#define SPI_0_EN 1
#define SPI_1_EN 0
#define SPI_IRQ_PRIO 1
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**

5
boards/mulle/board.c

@ -34,6 +34,7 @@ static nvram_t mulle_nvram_dev;
nvram_t *mulle_nvram = &mulle_nvram_dev;
static nvram_spi_params_t nvram_spi_params = {
.spi = MULLE_NVRAM_SPI_DEV,
.clk = MULLE_NVRAM_SPI_CLK,
.cs = MULLE_NVRAM_SPI_CS,
.address_count = MULLE_NVRAM_SPI_ADDRESS_COUNT,
};
@ -184,10 +185,6 @@ static int mulle_nvram_init(void)
} rec;
rec.u32 = 0;
if (spi_init_master(MULLE_NVRAM_SPI_DEV, SPI_CONF_FIRST_RISING, SPI_SPEED_5MHZ) != 0) {
return -1;
}
if (nvram_spi_init(mulle_nvram, &nvram_spi_params, MULLE_NVRAM_CAPACITY) != 0) {
return -2;
}

30
boards/mulle/include/board.h

@ -108,8 +108,8 @@ void board_init(void);
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_D, 4), \
.int_pin = GPIO_PIN(PORT_B, 9), \
.sleep_pin = GPIO_PIN(PORT_E, 6), \
@ -121,31 +121,31 @@ void board_init(void);
* @{
*/
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_SPI SPI_2
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_CLK SPI_CLK_5MHZ
#define LIS3DH_SPI SPI_DEV(0)
/** @} */
/**
* @name Mulle power control configuration
*/
/** @{ */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
/** @} */
/**
* @name Mulle NVRAM hardware configuration
*/
/** @{ */
/** FRAM SPI bus, SPI_2 in RIOT is mapped to hardware bus SPI0, see periph_conf.h */
#define MULLE_NVRAM_SPI_DEV SPI_2
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
/** @} */
/**

1
boards/mulle/include/lis3dh_params.h

@ -33,6 +33,7 @@ static const lis3dh_params_t lis3dh_params[] =
{
{
.spi = LIS3DH_SPI,
.clk = LIS3DH_CLK,
.cs = LIS3DH_CS,
.int1 = LIS3DH_INT1,
.int2 = LIS3DH_INT2,

229
boards/mulle/include/periph_conf.h

@ -216,159 +216,83 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* Clock configuration values based on the configured 47988736Hz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF 3
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_2_EN 1
#define SPI_3_EN 0
#define SPI_4_EN 0
#define SPI_5_EN 0
#define SPI_6_EN 0
#define SPI_7_EN 0
#define MULLE_PASTE_PARTS(left, index, right) MULLE_PASTE_PARTS2(left, index, right)
#define MULLE_PASTE_PARTS2(left, index, right) left##index##right
/* SPI 0 device config */
/* SPI_0 (in RIOT) is mapped to SPI0, CTAS=0 in hardware */
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
#define SPI_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_0_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
#define SPI_0_SCK_PIN 1
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_AF 2
#define SPI_0_SIN_PORT PORTD
#define SPI_0_SIN_PIN 3
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_AF 2
#define SPI_0_SOUT_PORT PORTD
#define SPI_0_SOUT_PIN 2
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_AF 2
#define SPI_0_PCS0_PORT PORTD
#define SPI_0_PCS0_PIN 0
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_0_PCS0_ACTIVE_LOW 1
#define SPI_0_PCS1_ACTIVE_LOW 1
#define SPI_0_PCS2_ACTIVE_LOW 1
#define SPI_0_PCS3_ACTIVE_LOW 1
/* SPI 1 device config */
/* SPI_1 (in RIOT) is mapped to SPI1, CTAS=0 in hardware */
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
#define SPI_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_1_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
#define SPI_1_SCK_PIN 2
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_AF 2
#define SPI_1_SIN_PORT PORTE
#define SPI_1_SIN_PIN 3
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_AF 2
#define SPI_1_SOUT_PORT PORTE
#define SPI_1_SOUT_PIN 1
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_AF 2
#define SPI_1_PCS0_PORT PORTE
#define SPI_1_PCS0_PIN 4
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_1_PCS0_ACTIVE_LOW 1
#define SPI_1_PCS1_ACTIVE_LOW 1
#define SPI_1_PCS2_ACTIVE_LOW 1
#define SPI_1_PCS3_ACTIVE_LOW 1
/* SPI 2 device config */
/* SPI_2 (in RIOT) is mapped to SPI0, CTAS=1 in hardware */
#define SPI_2_INDEX 0
#define SPI_2_CTAS 1
#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
#define SPI_2_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_2_FREQ SystemBusClock
/* SPI 2 pin configuration, must be the same as the other RIOT device using this
* hardware module */
#define SPI_2_SCK_PORT PORTD
#define SPI_2_SCK_PIN 1
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_AF 2
#define SPI_2_SIN_PORT PORTD
#define SPI_2_SIN_PIN 3
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_AF 2
#define SPI_2_SOUT_PORT PORTD
#define SPI_2_SOUT_PIN 2
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_AF 2
#define SPI_2_PCS0_PORT PORTD
#define SPI_2_PCS0_PIN 0
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_2_PCS0_ACTIVE_LOW 1
#define SPI_2_PCS1_ACTIVE_LOW 1
#define SPI_2_PCS2_ACTIVE_LOW 1
#define SPI_2_PCS3_ACTIVE_LOW 1
/**
* @name SPI delay timing configuration
* @{ */
/* These values are necessary for communicating with the AT86RF212B when running
* the MCU core at high clock frequencies. */
/* NB: The given values are the reciprocals of the time, in order to compute the
* scalers using only integer math. */
#define SPI_0_TCSC_FREQ (5555555) /* It looks silly, but this is correct. 1/180e-9 */
#define SPI_0_TASC_FREQ (5454545) /* It looks silly, but this is correct. 1/183e-9 */
#define SPI_0_TDT_FREQ (4000000) /* 1/250e-9 */
/* SPI_1 timings */
#define SPI_1_TCSC_FREQ (0)
#define SPI_1_TASC_FREQ (0)
#define SPI_1_TDT_FREQ (0)
/* SPI_2 timings */
#define SPI_2_TCSC_FREQ (0)
#define SPI_2_TASC_FREQ (0)
#define SPI_2_TDT_FREQ (0)
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};
/** @} */
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
},
{
.dev = SPI1,
.pin_miso = GPIO_PIN(PORT_E, 3),
.pin_mosi = GPIO_PIN(PORT_E, 1),
.pin_clk = GPIO_PIN(PORT_E, 2),
.pin_cs = {
GPIO_PIN(PORT_E, 4),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI1_MASK
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/**
* @name I2C baud rate configuration
* @{
@ -387,6 +311,16 @@ static const pwm_conf_t pwm_config[] = {
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
/* I2C 0 device configuration */
#define I2C_0_DEV I2C0
#define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
@ -402,7 +336,6 @@ static const pwm_conf_t pwm_config[] = {
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
/** @} */
/**
* @name GPIO configuration
* @{

1
boards/nrf52dk/Makefile.features

@ -4,6 +4,7 @@ FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

15
boards/nrf52dk/include/periph_conf.h

@ -74,6 +74,21 @@ static const timer_conf_t timer_config[] = {
#define UART_PIN_TX 6
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 15,
.mosi = 13,
.miso = 14 }
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus
}
#endif

32
boards/nrf6310/include/periph_conf.h

@ -100,22 +100,22 @@ static const timer_conf_t timer_config[] = {
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
/* SPI Master 0 pin configuration */
#define SPI_0_DEV NRF_SPI0
#define SPI_0_PIN_SCK 23
#define SPI_0_PIN_MISO 22
#define SPI_0_PIN_MOSI 20
/* SPI Master 1 pin configuration */
#define SPI_1_DEV NRF_SPI1
#define SPI_1_PIN_SCK 16
#define SPI_1_PIN_MISO 17
#define SPI_1_PIN_MOSI 18