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@ -94,11 +94,8 @@ extern "C" {
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#define UART_0_ISR isr_usart2
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#define UART_0_BUS_FREQ 36000000
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define UART_0_RX_PIN 3
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#define UART_0_TX_PIN 2
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#define UART_0_AF 1
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#define UART_0_RX_PIN GPIO(PORT_A,3)
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#define UART_0_TX_PIN GPIO(PORT_A,2)
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/* UART 1 device configuration */
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#define UART_1_DEV USART1
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@ -107,11 +104,8 @@ extern "C" {
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#define UART_1_ISR isr_usart1
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#define UART_1_BUS_FREQ 72000000
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOA
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#define UART_1_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
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#define UART_1_RX_PIN 10
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#define UART_1_TX_PIN 9
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#define UART_1_AF 0
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#define UART_1_RX_PIN GPIO(PORT_A,10)
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#define UART_1_TX_PIN GPIO(PORT_A,9)
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/** @} */
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/**
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@ -127,15 +121,9 @@ extern "C" {
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#define SPI_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
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#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
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/* SPI 0 pin configuration */
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#define SPI_0_CLK_PORT GPIOB
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#define SPI_0_CLK_PIN 13
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#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define SPI_0_MOSI_PORT GPIOB
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#define SPI_0_MOSI_PIN 15
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define SPI_0_MISO_PORT GPIOB
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#define SPI_0_MISO_PIN 14
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#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define SPI_0_CLK_PIN GPIO(PORT_B,13)
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#define SPI_0_MOSI_PIN GPIO(PORT_B,15)
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#define SPI_0_MISO_PIN GPIO(PORT_B,14)
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/** @} */
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/**
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@ -171,12 +159,8 @@ extern "C" {
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
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#define I2C_0_SCL_PIN GPIO(PORT_B,6)
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#define I2C_0_SDA_PIN GPIO(PORT_B,7)
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/** @} */
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#ifdef __cplusplus
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