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cpu/kinetis+boards: adapted to new SPI API

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- adapted the SPI driver
- adapted all boards using the CPU
pr/spi.typo
Hauke Petersen 7 years ago
parent ca5f1befb3
commit 5880d0edda
10 changed files with 403 additions and 1741 deletions
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86
boards/frdm-k64f/include/periph_conf.h
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@ -147,35 +147,67 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
* @name SPI configuration
*
* Clock configuration values based on the configured 30Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
#define SPI_IRQ_PRIO 1
#define KINETIS_SPI_USE_HW_CS 1
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_FREQ CLOCK_CORECLOCK
/* SPI 0 pin configuration */
#define SPI_0_PORT PORTD
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
#define SPI_0_AF 2
#define SPI_0_PCS0_PIN 0
#define SPI_0_SCK_PIN 1
#define SPI_0_SOUT_PIN 2
#define SPI_0_SIN_PIN 3
#define SPI_0_PCS0_ACTIVE_LOW 1
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
)
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

5
boards/mulle/board.c
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@ -34,6 +34,7 @@ static nvram_t mulle_nvram_dev;
nvram_t *mulle_nvram = &mulle_nvram_dev;
static nvram_spi_params_t nvram_spi_params = {
.spi = MULLE_NVRAM_SPI_DEV,
.clk = MULLE_NVRAM_SPI_CLK,
.cs = MULLE_NVRAM_SPI_CS,
.address_count = MULLE_NVRAM_SPI_ADDRESS_COUNT,
};
@ -184,10 +185,6 @@ static int mulle_nvram_init(void)
} rec;
rec.u32 = 0;
if (spi_init_master(MULLE_NVRAM_SPI_DEV, SPI_CONF_FIRST_RISING, SPI_SPEED_5MHZ) != 0) {
return -1;
}
if (nvram_spi_init(mulle_nvram, &nvram_spi_params, MULLE_NVRAM_CAPACITY) != 0) {
return -2;
}

30
boards/mulle/include/board.h
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@ -108,8 +108,8 @@ void board_init(void);
*
* {spi bus, spi speed, cs pin, int pin, reset pin, sleep pin}
*/
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_0, \
.spi_speed = SPI_SPEED_5MHZ, \
#define AT86RF2XX_PARAMS_BOARD {.spi = SPI_DEV(0), \
.spi_clk = SPI_CLK_5MHZ, \
.cs_pin = GPIO_PIN(PORT_D, 4), \
.int_pin = GPIO_PIN(PORT_B, 9), \
.sleep_pin = GPIO_PIN(PORT_E, 6), \
@ -121,31 +121,31 @@ void board_init(void);
* @{
*/
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_SPI SPI_2
#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
#define LIS3DH_CLK SPI_CLK_5MHZ
#define LIS3DH_SPI SPI_DEV(0)
/** @} */
/**
* @name Mulle power control configuration
*/
/** @{ */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
/** @} */
/**
* @name Mulle NVRAM hardware configuration
*/
/** @{ */
/** FRAM SPI bus, SPI_2 in RIOT is mapped to hardware bus SPI0, see periph_conf.h */
#define MULLE_NVRAM_SPI_DEV SPI_2
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
/** @} */
/**

1
boards/mulle/include/lis3dh_params.h
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@ -33,6 +33,7 @@ static const lis3dh_params_t lis3dh_params[] =
{
{
.spi = LIS3DH_SPI,
.clk = LIS3DH_CLK,
.cs = LIS3DH_CS,
.int1 = LIS3DH_INT1,
.int2 = LIS3DH_INT2,

208
boards/mulle/include/periph_conf.h
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@ -216,147 +216,81 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* Clock configuration values based on the configured 47988736Hz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF 3
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_2_EN 1
#define SPI_3_EN 0
#define SPI_4_EN 0
#define SPI_5_EN 0
#define SPI_6_EN 0
#define SPI_7_EN 0
#define MULLE_PASTE_PARTS(left, index, right) MULLE_PASTE_PARTS2(left, index, right)
#define MULLE_PASTE_PARTS2(left, index, right) left##index##right
/* SPI 0 device config */
/* SPI_0 (in RIOT) is mapped to SPI0, CTAS=0 in hardware */
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
#define SPI_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_0_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
#define SPI_0_SCK_PIN 1
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_AF 2
#define SPI_0_SIN_PORT PORTD
#define SPI_0_SIN_PIN 3
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_AF 2
#define SPI_0_SOUT_PORT PORTD
#define SPI_0_SOUT_PIN 2
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_AF 2
#define SPI_0_PCS0_PORT PORTD
#define SPI_0_PCS0_PIN 0
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_0_PCS0_ACTIVE_LOW 1
#define SPI_0_PCS1_ACTIVE_LOW 1
#define SPI_0_PCS2_ACTIVE_LOW 1
#define SPI_0_PCS3_ACTIVE_LOW 1
/* SPI 1 device config */
/* SPI_1 (in RIOT) is mapped to SPI1, CTAS=0 in hardware */
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
#define SPI_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_1_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
#define SPI_1_SCK_PIN 2
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_AF 2
#define SPI_1_SIN_PORT PORTE
#define SPI_1_SIN_PIN 3
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_AF 2
#define SPI_1_SOUT_PORT PORTE
#define SPI_1_SOUT_PIN 1
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_AF 2
#define SPI_1_PCS0_PORT PORTE
#define SPI_1_PCS0_PIN 4
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_1_PCS0_ACTIVE_LOW 1
#define SPI_1_PCS1_ACTIVE_LOW 1
#define SPI_1_PCS2_ACTIVE_LOW 1
#define SPI_1_PCS3_ACTIVE_LOW 1
/* SPI 2 device config */
/* SPI_2 (in RIOT) is mapped to SPI0, CTAS=1 in hardware */
#define SPI_2_INDEX 0
#define SPI_2_CTAS 1
#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
#define SPI_2_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
#define SPI_2_FREQ SystemBusClock
/* SPI 2 pin configuration, must be the same as the other RIOT device using this
* hardware module */
#define SPI_2_SCK_PORT PORTD
#define SPI_2_SCK_PIN 1
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_AF 2
#define SPI_2_SIN_PORT PORTD
#define SPI_2_SIN_PIN 3
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_AF 2
#define SPI_2_SOUT_PORT PORTD
#define SPI_2_SOUT_PIN 2
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_AF 2
#define SPI_2_PCS0_PORT PORTD
#define SPI_2_PCS0_PIN 0
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_2_PCS0_ACTIVE_LOW 1
#define SPI_2_PCS1_ACTIVE_LOW 1
#define SPI_2_PCS2_ACTIVE_LOW 1
#define SPI_2_PCS3_ACTIVE_LOW 1
/**
* @name SPI delay timing configuration
* @{ */
/* These values are necessary for communicating with the AT86RF212B when running
* the MCU core at high clock frequencies. */
/* NB: The given values are the reciprocals of the time, in order to compute the
* scalers using only integer math. */
#define SPI_0_TCSC_FREQ (5555555) /* It looks silly, but this is correct. 1/180e-9 */
#define SPI_0_TASC_FREQ (5454545) /* It looks silly, but this is correct. 1/183e-9 */
#define SPI_0_TDT_FREQ (4000000) /* 1/250e-9 */
/* SPI_1 timings */
#define SPI_1_TCSC_FREQ (0)
#define SPI_1_TASC_FREQ (0)
#define SPI_1_TDT_FREQ (0)
/* SPI_2 timings */
#define SPI_2_TCSC_FREQ (0)
#define SPI_2_TASC_FREQ (0)
#define SPI_2_TDT_FREQ (0)
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};
/** @} */
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_D, 3),
.pin_mosi = GPIO_PIN(PORT_D, 2),
.pin_clk = GPIO_PIN(PORT_D, 1),
.pin_cs = {
GPIO_PIN(PORT_D, 0),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI0_MASK
},
{
.dev = SPI1,
.pin_miso = GPIO_PIN(PORT_E, 3),
.pin_mosi = GPIO_PIN(PORT_E, 1),
.pin_clk = GPIO_PIN(PORT_E, 2),
.pin_cs = {
GPIO_PIN(PORT_E, 4),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.pcr = GPIO_AF_2,
.simmask = SIM_SCGC6_SPI1_MASK
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

4
boards/pba-d-01-kw2x/include/board.h
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@ -68,10 +68,10 @@ extern "C"
@name KW2XRF configuration
@{
*/
#define KW2XRF_SPI (SPI_1)
#define KW2XRF_SPI (SPI_DEV(1))
#define KW2XRF_CS (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_PCS0_PIN))
#define KW2XRF_INT (GPIO_PIN(KW2XDRF_PORT, KW2XDRF_IRQ_PIN))
#define KW2XRF_SPI_SPEED (SPI_SPEED_10MHZ)
#define KW2XRF_SPI_SPEED (SPI_CLK_10MHZ)
#define KW2XRF_SHARED_SPI 0
/** @}*/

123
boards/pba-d-01-kw2x/include/periph_conf.h
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@ -163,59 +163,82 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
* @name SPI device configuration
*
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
#define KINETIS_SPI_USE_HW_CS 1
/* SPI 0 device config */
#define SPI_0_DEV SPI0
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ SPI0_IRQn
#define SPI_0_IRQ_HANDLER isr_spi0
#define SPI_0_FREQ (48e6)
/* SPI 0 pin configuration */
#define SPI_0_PORT PORTC
#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_AF 2
#define SPI_0_PCS0_PIN 4
#define SPI_0_SCK_PIN 5
#define SPI_0_SOUT_PIN 6
#define SPI_0_SIN_PIN 7
#define SPI_0_PCS0_ACTIVE_LOW 1
/* SPI 1 device config */
#define SPI_1_DEV SPI1
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI1_MASK))
#define SPI_1_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI1_MASK))
#define SPI_1_IRQ SPI1_IRQn
#define SPI_1_IRQ_HANDLER isr_spi1
#define SPI_1_FREQ (48e6)
/* SPI 1 pin1configuration */
#define SPI_1_PORT KW2XDRF_PORT_DEV
#define SPI_1_PORT_CLKEN() KW2XDRF_PORT_CLKEN();
#define SPI_1_AF KW2XDRF_PIN_AF
#define SPI_1_PCS0_PIN KW2XDRF_PCS0_PIN
#define SPI_1_SCK_PIN KW2XDRF_SCK_PIN
#define SPI_1_SOUT_PIN KW2XDRF_SOUT_PIN
#define SPI_1_SIN_PIN KW2XDRF_SIN_PIN
#define SPI_1_PCS0_ACTIVE_LOW 1
static const uint32_t spi_clk_config[] = {
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
),
(
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
),
(
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
),
(
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
)
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI0,
.pin_miso = GPIO_PIN(PORT_C, 7),
.pin_mosi = GPIO_PIN(PORT_C, 6),
.pin_clk = GPIO_PIN(PORT_C, 5),
.pin_cs = {
GPIO_PIN(PORT_C, 4),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.simmask = SIM_SCGC6_SPI0_MASK,
.pcr = GPIO_AF_2
},
{
.dev = SPI1,
.pin_miso = GPIO_PIN(PORT_B, 17),
.pin_mosi = GPIO_PIN(PORT_B, 16),
.pin_clk = GPIO_PIN(PORT_B, 11),
.pin_cs = {
GPIO_PIN(PORT_B, 10),
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF,
GPIO_UNDEF
},
.simmask = SIM_SCGC6_SPI1_MASK,
.pcr = GPIO_AF_2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */

1
cpu/kinetis_common/Makefile.include
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@ -9,6 +9,7 @@ export UNDEF += $(BINDIR)/kinetis_common/fcfield.o
# include kinetis common periph drivers
export USEMODULE += kinetis_common_periph
export USEMODULE += periph_common
#include layered power mode module
USEMODULE += pm_layered

54
cpu/kinetis_common/include/periph_cpu.h
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@ -66,6 +66,28 @@ typedef uint16_t gpio_t;
*/
#define PWM_CHAN_MAX (4U)
/**
* @brief Define a CPU specific SPI hardware chip select line macro
*
* We simply map the 5 hardware channels to the numbers [0-4], this still allows
* us to differentiate between GPIP_PINs and SPI_HWSC lines.
*/
#define SPI_HWCS(x) (x)
/**
* @brief Kinetis CPUs have a maximum number of 5 hardware chip select lines
*/
#define SPI_HWCS_NUMOF (5)
/**
* @brief This CPU makes use of the following shared SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
#ifndef DOXYGEN
/**
* @brief Override GPIO modes
@ -88,7 +110,7 @@ typedef enum {
*
* To combine values just aggregate them using a logical OR.
*/
enum {
typedef enum {
GPIO_AF_ANALOG = PORT_PCR_MUX(0), /**< use pin as analog input */
GPIO_AF_GPIO = PORT_PCR_MUX(1), /**< use pin as GPIO */
GPIO_AF_2 = PORT_PCR_MUX(2), /**< use alternate function 2 */
@ -100,7 +122,7 @@ enum {
GPIO_PCR_OD = (PORT_PCR_ODE_MASK), /**< open-drain mode */
GPIO_PCR_PD = (PORT_PCR_PE_MASK), /**< enable pull-down */
GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK) /**< enable PU */
};
} gpio_pcr_t;
#ifndef DOXYGEN
/**
@ -161,6 +183,21 @@ typedef enum {
/** @} */
#endif /* ndef DOXYGEN */
#ifndef DOXYGEN
/**
* @brief Override default ADC resolution values
* @{
*/
#define HAVE_SPI_MODE_T
typedef enum {
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = (SPI_CTAR_CPHA_MASK), /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = (SPI_CTAR_CPOL_MASK), /**< CPOL=1, CPHA=0 */
SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK) /**< CPOL=1, CPHA=1 */
} spi_mode_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief CPU specific ADC configuration
*/
@ -217,6 +254,19 @@ typedef struct {
uint8_t ftm_num; /**< FTM number used */
} pwm_conf_t;
/**
* @brief SPI module configuration options
*/
typedef struct {
SPI_Type *dev; /**< SPI device to use */
gpio_t pin_miso; /**< MISO pin used */
gpio_t pin_mosi; /**< MOSI pin used */
gpio_t pin_clk; /**< CLK pin used */
gpio_t pin_cs[SPI_HWCS_NUMOF]; /**< pins used for HW cs lines */
gpio_pcr_t pcr; /**< alternate pin function values */
uint32_t simmask; /**< bit in the SIM register */
} spi_conf_t;
/**
* @brief Possible timer module types
*/

1632
cpu/kinetis_common/periph/spi.c
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