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Merge pull request #4943 from gebart/pr/while-loops

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Use {} notation for empty while loops
pr/gpio
Oleg Hahm 8 years ago
parent 114f2643fc c6a25605b8
commit 596c25daca
57 changed files with 295 additions and 302 deletions
Show Stats Download Patch File Download Diff File

106
boards/pttu/board_init.c
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@ -29,35 +29,35 @@
/*---------------------------------------------------------------------------*/
void init_clks1(void)
{
// Disconnect PLL
/* Disconnect PLL */
PLLCON &= ~0x0002;
pllfeed();
while (PLLSTAT & BIT25); // wait until PLL is disconnected before disabling - deadlock otherwise
while (PLLSTAT & BIT25) {} /* wait until PLL is disconnected before disabling - deadlock otherwise */
// Disable PLL
/* Disable PLL */
PLLCON &= ~0x0001;
pllfeed();
while (PLLSTAT & BIT24); // wait until PLL is disabled
while (PLLSTAT & BIT24) {} /* wait until PLL is disabled */
SCS |= 0x20; // Enable main OSC
while( !(SCS & 0x40) ); // Wait until main OSC is usable
SCS |= 0x20; /* Enable main OSC */
while( !(SCS & 0x40) ) {} /* Wait until main OSC is usable */
/* select main OSC, 16MHz, as the PLL clock source */
CLKSRCSEL = 0x0001;
// Setting Multiplier and Divider values
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
/* Setting Multiplier and Divider values */
PLLCFG = 0x0008; /* M=9 N=1 Fcco = 288 MHz */
pllfeed();
// Enabling the PLL */
/* Enabling the PLL */
PLLCON = 0x0001;
pllfeed();
/* Set clock divider to 4 (value+1) */
CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
CCLKCFG = CL_CPU_DIV - 1; /* Fcpu = 72 MHz */
#if USE_USB
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
#endif
}
@ -66,19 +66,19 @@ void bl_init_ports(void)
gpio_init_ports();
/* UART0 */
PINSEL0 |= BIT4 + BIT6; // RxD0 and TxD0
PINSEL0 |= BIT4 + BIT6; /* RxD0 and TxD0 */
PINSEL0 &= ~(BIT5 + BIT7);
/*Turn Board on*/
/* Turn Board on */
PINMODE0 |= BIT1;
FIO0DIR |= BIT27;
FIO0CLR = BIT27;
/* 5V*/
FIO1DIR |= BIT28; // Synch
FIO1SET = BIT28; // No Powersave
FIO1DIR |= BIT28; /* Synch */
FIO1SET = BIT28; /* No Powersave */
FIO1DIR |= BIT27; // 5V off
FIO1DIR |= BIT27; /* 5V off */
FIO1CLR = BIT27;
/* Disable Resistors on Buttons */
@ -92,77 +92,77 @@ void bl_init_ports(void)
FIO1SET = BIT0;
FIO3SET = BIT25 + BIT26;
// Config and Disable PA
/* Config and Disable PA */
FIO1DIR |= BIT25 + BIT26 + BIT22;
FIO1SET = BIT26;
FIO1CLR = BIT25;
FIO1CLR = BIT22; // PA /Shutdown
FIO0DIR |= BIT26; // ** // Important: First put this Port as DA 2.0V and then turn on PA!!
FIO0SET = BIT26; // **
FIO1CLR = BIT22; /* PA /Shutdown */
FIO0DIR |= BIT26; /* ** Important: First put this Port as DA 2.0V and then turn on PA!! */
FIO0SET = BIT26; /* ** */
// Configure GPS
PINMODE3 |= BIT3 + BIT7; // No Pullup on 1.17 & 1.19
PINMODE9 |= BIT27 + BIT25; // No Pullup for Uart
/* Configure GPS */
PINMODE3 |= BIT3 + BIT7; /* No Pullup on 1.17 & 1.19 */
PINMODE9 |= BIT27 + BIT25; /* No Pullup for Uart */
FIO1DIR |= BIT17;
FIO1CLR = BIT17; // Turn off GPS
FIO1CLR = BIT17; /* Turn off GPS */
FIO1DIR |= BIT19;
FIO1CLR = BIT19; // Hold in Reset
PINSEL9 |= BIT24 + BIT25 + BIT26 + BIT27; //4.28 & 4.29 as Uart3
FIO1CLR = BIT19; /* Hold in Reset */
PINSEL9 |= BIT24 + BIT25 + BIT26 + BIT27; /* 4.28 & 4.29 as Uart3 */
// Nanotron
FIO2DIR &= ~BIT8; // nanotron uC IRQ as input
FIO1DIR |= BIT15; // nanotron power on reset
FIO1DIR &= ~BIT14; // nanotron uC RESET as input
FIO1DIR &= ~BIT10; // nanotron uC Vcc as input
FIO1DIR |= BIT9; // nanotron ENABLE as output
FIO1DIR &= ~BIT4; // nanotron Rx/Tx as input
/* Nanotron */
FIO2DIR &= ~BIT8; /* nanotron uC IRQ as input */
FIO1DIR |= BIT15; /* nanotron power on reset */
FIO1DIR &= ~BIT14; /* nanotron uC RESET as input */
FIO1DIR &= ~BIT10; /* nanotron uC Vcc as input */
FIO1DIR |= BIT9; /* nanotron ENABLE as output */
FIO1DIR &= ~BIT4; /* nanotron Rx/Tx as input */
FIO1CLR = BIT15;
FIO1CLR = BIT9; // Enable power
FIO1CLR = BIT9; /* Enable power */
PINMODE1 |= BIT1; // No Pullup for CS
FIO0DIR |= BIT16; // CS as output
FIO0SET = BIT16; // drive cs inactive
FIO0DIR |= BIT18 + BIT15; // SPi Output
PINMODE1 |= BIT1; /* No Pullup for CS */
FIO0DIR |= BIT16; /* CS as output */
FIO0SET = BIT16; /* drive cs inactive */
FIO0DIR |= BIT18 + BIT15; /* SPi Output */
// RFID
FIO1DIR |= BIT1; // RFID Power
FIO1CLR = BIT1; //
/* RFID */
FIO1DIR |= BIT1; /* RFID Power */
FIO1CLR = BIT1; /* */
FIO0DIR |= BIT1; // RFID Reset
FIO0SET = BIT1; // Hold in Reset
FIO0DIR |= BIT1; /* RFID Reset */
FIO0SET = BIT1; /* Hold in Reset */
FIO0DIR &= ~BIT10; // LED as INPUT
FIO0DIR &= ~BIT11; // DATA as INPUT
PINMODE0 |= BIT19 + BIT21; // No Pullups
FIO0DIR &= ~BIT10; /* LED as INPUT */
FIO0DIR &= ~BIT11; /* DATA as INPUT */
PINMODE0 |= BIT19 + BIT21; /* No Pullups */
// LTC4150 ARM
/* LTC4150 ARM */
FIO0DIR |= BIT5;
FIO0CLR = BIT5;
// LTC4150 System
/* LTC4150 System */
FIO0DIR |= BIT24;
FIO0CLR = BIT24;
// Battery Voltage (AD)
/* Battery Voltage (AD) */
PINMODE1 |= BIT19;
PINSEL1 &= ~BIT19;
PINSEL1 |= BIT18;
//cc1100
/*cc1100 */
FIO0DIR |= BIT6 + BIT7 + BIT9;
FIO0SET = BIT6;
FIO0SET = BIT7 + BIT9;
//SD
/*SD */
FIO2DIR |= BIT12 + BIT13 + BIT11;
FIO0DIR |= BIT20 + BIT22 + BIT21;
//Tetra
/*Tetra */
FIO2DIR |= BIT0 + BIT7;
// No Pullups on any port
/* No Pullups on any port */
int nopullup = BIT1 + BIT3 + BIT5 + BIT7 + BIT9 + BIT11 + BIT13 + BIT15 + BIT17 + BIT19 + BIT21 + BIT23 + BIT25 + BIT27 + BIT29 + BIT31;
PINMODE0 = nopullup - BIT13 - BIT15 - BIT17 - BIT19;
PINMODE1 = BIT1 + BIT3 + BIT5 + BIT7 + BIT9 + BIT11 + BIT13 + BIT15 + BIT17 + BIT19 + BIT21;

6
cpu/lpc11u34/periph/spi.c
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@ -93,7 +93,7 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
spi->CR1 |= (1 << 1);
/* Wait while the BUSY flag is set */
while(spi->SR & (1 << 4));
while(spi->SR & (1 << 4)) {}
/* Clear the RX FIFO */
while(spi->SR & (1 << 2)) {
spi->DR;
@ -176,11 +176,11 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
}
/* Wait while the BUSY flag is set */
while(spi->SR & (1 << 4));
while(spi->SR & (1 << 4)) {}
/* Put byte in the TX Fifo */
*((volatile uint8_t *)(&spi->DR)) = (uint8_t)out;
/* Wait until the current byte is transfered */
while(!(spi->SR & (1 << 2)) );
while(!(spi->SR & (1 << 2)) ) {}
/* Read the returned byte */
tmp = *((volatile uint8_t *)(&spi->DR));
/* 'return' response byte if wished for */

2
cpu/lpc2387/cpu.c
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@ -92,7 +92,7 @@ __attribute__((naked,noreturn)) void arm_reset(void)
WDMOD = 0x03;
WDFEED= 0xAA;
WDFEED= 0x55;
while(1);
while(1) {}
}
/** @} */

9
cpu/lpc2387/i2c/i2c.c
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@ -164,8 +164,7 @@ bool i2c_stop(uint8_t i2c_interface)
I20CONCLR = I2CONCLR_SIC; /* Clear SI flag */
/*--- Wait for STOP detected ---*/
while (I20CONSET & I2CONSET_STO)
;
while (I20CONSET & I2CONSET_STO) {}
break;
@ -175,8 +174,7 @@ bool i2c_stop(uint8_t i2c_interface)
I21CONCLR = I2CONCLR_SIC; /* Clear SI flag */
/*--- Wait for STOP detected ---*/
while (I21CONSET & I2CONSET_STO)
;
while (I21CONSET & I2CONSET_STO) {}
break;
@ -185,8 +183,7 @@ bool i2c_stop(uint8_t i2c_interface)
I22CONCLR = I2CONCLR_SIC; /* Clear SI flag */
/*--- Wait for STOP detected ---*/
while (I22CONSET & I2CONSET_STO)
;
while (I22CONSET & I2CONSET_STO) {}
}
// puts("...i2c_stop ended\n");

19
cpu/lpc2387/mci/lpc2387-mci.c
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@ -555,9 +555,10 @@ DSTATUS MCI_initialize(void)
/* The card can work at vdd range of 2.7-3.6V */
DEBUG("SDC Ver. 2\n");
do { /* Wait while card is busy state (use ACMD41 with HCS bit) */
do {
/* Wait while card is busy state (use ACMD41 with HCS bit) */
/* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */
if (xtimer_now() > start + 1000000/*!Timer[0]*/) {
if (xtimer_now() > start + 1000000/* !Timer[0] */) {
DEBUG("%s, %d: Timeout #1\n", RIOT_FILE_RELATIVE, __LINE__);
goto di_fail;
}
@ -578,11 +579,12 @@ DSTATUS MCI_initialize(void)
cmd = CMD1; /* ACMD41 is rejected -> MMC */
}
do { /* Wait while card is busy state (use ACMD41 or CMD1) */
do {
/* Wait while card is busy state (use ACMD41 or CMD1) */
DEBUG("%s, %d: %lX\n", RIOT_FILE_RELATIVE, __LINE__, resp[0]);
/* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */
if (xtimer_now() > start + 1000000/*!Timer[0]*/) {
if (xtimer_now() > start + 1000000/* !Timer[0] */) {
DEBUG("now: %lu, started at: %lu\n", xtimer_now(), start);
DEBUG("%s, %d: Timeout #2\n", RIOT_FILE_RELATIVE, __LINE__);
goto di_fail;
@ -745,8 +747,7 @@ DRESULT MCI_read(unsigned char *buff, unsigned long sector, unsigned char count)
}
buff += 512; /* Next user buffer address */
}
while (--count);
} while (--count);
if (cmd == CMD18) { /* Terminate to read (MB) */
send_cmd(CMD12, 0, 1, &resp);
@ -846,10 +847,10 @@ DRESULT MCI_write(const unsigned char *buff, unsigned long sector, unsigned char
}
count--;
buff += 512; /* Next user buffer address */
buff += 512; /* Next user buffer address */
}
while (!(XferStat & 0xC)); /* Wait for all blocks sent (block underrun) */
while (!(XferStat & 0xC)) {} /* Wait for all blocks sent (block underrun) */
if (XferStat & 0x8) {
count = 1; /* Abort if any MCI error has occured */
@ -996,7 +997,7 @@ DRESULT MCI_ioctl(
if (send_cmd(ACMD13, 0, 1, resp) /* Start to read */
&& !(resp[0] & 0xC0580000)) {
while ((XferWp == 0) && !(XferStat & 0xC));
while ((XferWp == 0) && !(XferStat & 0xC)) {}
if (!(XferStat & 0xC)) {
Copy_al2un((unsigned char *)buff, DmaBuff[0], 64);

6
cpu/lpc2387/periph/spi.c
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@ -172,10 +172,10 @@ int spi_release(spi_t dev)
int spi_transfer_byte(spi_t dev, char out, char *in)
{
(void) dev;
while (!SPI_TX_EMPTY);
while (!SPI_TX_EMPTY) {}
SSP0DR = out;
while (SPI_BUSY);
while (!SPI_RX_AVAIL);
while (SPI_BUSY) {}
while (!SPI_RX_AVAIL) {}
char tmp = (char)SSP0DR;

5
cpu/lpc2387/periph/uart.c
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@ -73,7 +73,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
(void) uart;
for (size_t i = 0; i < len; i++) {
while (!(U0LSR & BIT5));
while (!(U0LSR & BIT5)) {}
U0THR = data[i];
}
}
@ -86,8 +86,7 @@ void UART0_IRQHandler(void)
do {
char c = (char)U0RBR;
_rx_cb(_cb_arg, c);
}
while (U0LSR & ULSR_RDR);
} while (U0LSR & ULSR_RDR);
break;
default:

4
cpu/msp430fxyz/periph/spi.c
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@ -202,9 +202,9 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
{
(void)dev;
char tmp;
while (!(SPI_IF & SPI_IE_TX_BIT));
while (!(SPI_IF & SPI_IE_TX_BIT)) {}
SPI_DEV->TXBUF = (uint8_t)out;
while (!(SPI_IF & SPI_IE_RX_BIT));
while (!(SPI_IF & SPI_IE_RX_BIT)) {}
tmp = (char)SPI_DEV->RXBUF;
if (in) {
*in = tmp;

4
cpu/msp430fxyz/periph/uart.c
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@ -94,7 +94,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
msp_usart_t *dev = UART_BASE;
for (size_t i = 0; i < len; i++) {
while (!(dev->TCTL & USART_TCTL_TXEPT));
while (!(dev->TCTL & USART_TCTL_TXEPT)) {}
dev->TXBUF = data[i];
}
}
@ -182,7 +182,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
(void)uart;
for (size_t i = 0; i < len; i++) {
while (!(UART_IF & UART_IE_TX_BIT));
while (!(UART_IF & UART_IE_TX_BIT)) {}
UART_BASE->ATXBUF = data[i];
}
}

4
cpu/nrf51/cpu.c
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@ -32,11 +32,11 @@ void cpu_init(void)
NRF_CLOCK->XTALFREQ = CLOCK_XTALFREQ_XTALFREQ_32MHz;
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0);
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {}
#elif CLOCK_CRYSTAL == 16
NRF_CLOCK->XTALFREQ = CLOCK_XTALFREQ_XTALFREQ_16MHz;
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0);
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {}
#endif
}

2
cpu/nrf51/periph/adc.c
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@ -99,7 +99,7 @@ int adc_sample(adc_t dev, int channel)
NRF_ADC->TASKS_START = 1;
/* wait for conversion to be complete */
while (((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) >> ADC_BUSY_BUSY_Pos) == ADC_BUSY_BUSY_Busy);
while (((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) >> ADC_BUSY_BUSY_Pos) == ADC_BUSY_BUSY_Busy) {}
NRF_ADC->EVENTS_END = 1;
/* return result */

2
cpu/nrf51/periph/spi.c
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@ -190,7 +190,7 @@ int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
char tmp = (out) ? out[i] : 0;
spi[dev]->EVENTS_READY = 0;
spi[dev]->TXD = (uint8_t)tmp;
while (spi[dev]->EVENTS_READY != 1);
while (spi[dev]->EVENTS_READY != 1) {}
tmp = (char)spi[dev]->RXD;
if (in) {
in[i] = tmp;

10
cpu/nrf51/radio/nrfmin/nrfmin.c
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@ -189,7 +189,7 @@ static void _switch_to_idle(void)
/* witch to idle state */
NRF_RADIO->EVENTS_DISABLED = 0;
NRF_RADIO->TASKS_DISABLE = 1;
while (NRF_RADIO->EVENTS_DISABLED == 0);
while (NRF_RADIO->EVENTS_DISABLED == 0) {}
_state = STATE_IDLE;
}
@ -279,7 +279,7 @@ int _set_address(uint8_t *val, size_t len)
return -EINVAL;
}
/* keep track of state */
while (_state == STATE_TX);
while (_state == STATE_TX) {}
if (_state == STATE_RX) {
is_rx = 1;
_switch_to_idle();
@ -316,7 +316,7 @@ int _set_channel(uint8_t *val, size_t len)
return -EINVAL;
}
/* remember state */
while (_state == STATE_TX);
while (_state == STATE_TX) {}
if (_state == STATE_RX) {
is_rx = 1;
_switch_to_idle();
@ -352,7 +352,7 @@ int _set_pan(uint8_t *val, size_t len)
return -EINVAL;
}
/* remember state */
while (_state == STATE_TX);
while (_state == STATE_TX) {}
if (_state == STATE_RX) {
is_rx = 1;
_switch_to_idle();
@ -610,7 +610,7 @@ int _send(gnrc_netdev_t *dev, gnrc_pktsnip_t *pkt)
dst_addr[0], dst_addr[1], size);
/* wait for any ongoing transmission to finish */
while (_state == STATE_TX);
while (_state == STATE_TX) {}
/* write data into TX buffer */
payload = pkt->next;
_tx_buf.length = 6 + size;

2
cpu/nrf5x_common/periph/uart.c
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@ -143,7 +143,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* write data into transmit register */
NRF_UART0->TXD = data[i];
/* wait for any transmission to be done */
while (NRF_UART0->EVENTS_TXDRDY == 0);
while (NRF_UART0->EVENTS_TXDRDY == 0) {}
/* reset ready flag */
NRF_UART0->EVENTS_TXDRDY = 0;
}

4
cpu/sam3/periph/cpuid.c
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@ -53,7 +53,7 @@ void cpuid_get(void *id)
EFC1->EEFC_FCR = EEFC_FCR_FKEY(EFC_KEY) | EFC_FCMD_STUI;
/* Wait for FRDY bit falls */
while (EFC1->EEFC_FSR & EEFC_FSR_FRDY);
while (EFC1->EEFC_FSR & EEFC_FSR_FRDY) {}
/* Read UID */
cpuid[0] = *(uint32_t *)IFLASH1_ADDR;
@ -65,7 +65,7 @@ void cpuid_get(void *id)
EFC1->EEFC_FCR = EEFC_FCR_FKEY(EFC_KEY) | EFC_FCMD_SPUI ;
/* Wait for FRDY bit rises. */
while (0 == (EFC1->EEFC_FSR & EEFC_FSR_FRDY));
while (0 == (EFC1->EEFC_FSR & EEFC_FSR_FRDY)) {}
memcpy(id, (void*)cpuid, CPUID_LEN);
}

2
cpu/sam3/periph/hwrng.c
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@ -43,7 +43,7 @@ void hwrng_read(uint8_t *buf, unsigned int num)
while (count < num) {
/* wait until new value is generated -> takes up to 84 cycles */
while (!(TRNG->TRNG_ISR & TRNG_ISR_DATRDY));
while (!(TRNG->TRNG_ISR & TRNG_ISR_DATRDY)) {}
/* read 4 byte of random data */
uint32_t tmp = TRNG->TRNG_ODATA;
/* extract copy bytes to result */

6
cpu/sam3/periph/spi.c
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@ -75,7 +75,7 @@ void spi_poweroff(spi_t dev)
switch (dev) {
#if SPI_0_EN
case SPI_0:
while (!(SPI_0_DEV->SPI_SR & SPI_SR_SPIENS)); /* not busy anymore */
while (!(SPI_0_DEV->SPI_SR & SPI_SR_SPIENS)) {} /* not busy anymore */
SPI_0_CLKDIS();
NVIC_DisableIRQ(SPI_0_IRQ);
break;
@ -324,11 +324,11 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
return -1;
}
while (!(spi_port->SPI_SR & SPI_SR_TDRE));
while (!(spi_port->SPI_SR & SPI_SR_TDRE)) {}
spi_port->SPI_TDR = SPI_TDR_TD(out);
while (!(spi_port->SPI_SR & SPI_SR_RDRF));
while (!(spi_port->SPI_SR & SPI_SR_RDRF)) {}
*in = spi_port->SPI_RDR & SPI_RDR_RD_Msk;

2
cpu/sam3/periph/uart.c
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@ -79,7 +79,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
Uart *dev = uart_config[uart].dev;
for (size_t i = 0; i < len; i++) {
while (!(dev->UART_SR & UART_SR_TXRDY));
while (!(dev->UART_SR & UART_SR_TXRDY)) {}
dev->UART_THR = data[i];
}
}

12
cpu/samd21/cpu.c
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@ -42,12 +42,12 @@ static void clk_init(void)
SYSCTRL->OSC8M.bit.ONDEMAND = 0;
SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
SYSCTRL->OSC8M.bit.ENABLE = 1;
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY));
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
#if CLOCK_USE_PLL
/* reset the GCLK module so it is in a known state */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* setup generic clock 1 to feed DPLL with 1MHz */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
@ -58,14 +58,14 @@ static void clk_init(void)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(1) |
GCLK_CLKCTRL_ID(1) |
GCLK_CLKCTRL_CLKEN);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* enable PLL */
SYSCTRL->DPLLRATIO.reg = (SYSCTRL_DPLLRATIO_LDR(CLOCK_PLL_MUL));
SYSCTRL->DPLLCTRLB.reg = (SYSCTRL_DPLLCTRLB_REFCLK_GCLK);
SYSCTRL->DPLLCTRLA.reg = (SYSCTRL_DPLLCTRLA_ENABLE);
while(!(SYSCTRL->DPLLSTATUS.reg &
(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)));
(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK))) {}
/* select the PLL as source for clock generator 0 (CPU core clock) */
GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_PLL_DIV) |
@ -82,12 +82,12 @@ static void clk_init(void)
#endif
/* make sure we synchronize clock generator 0 before we go on */
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
/* redirect all peripherals to a disabled clock generator (7) by default */
for (int i = 0x3; i <= 0x22; i++) {
GCLK->CLKCTRL.reg = ( GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN_GCLK7 );
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
}

4
cpu/samd21/periph/gpio.c
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@ -140,7 +140,7 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
GCLK->CLKCTRL.reg = (EIC_GCLK_ID |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0);
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* configure the active flank */
EIC->CONFIG[exti >> 3].reg &= ~(0xf << ((exti & 0x7) * 4));
EIC->CONFIG[exti >> 3].reg |= (flank << ((exti & 0x7) * 4));
@ -152,7 +152,7 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
EIC->INTENSET.reg = (1 << exti);
/* enable the EIC module*/
EIC->CTRL.reg = EIC_CTRL_ENABLE;
while (EIC->STATUS.reg & EIC_STATUS_SYNCBUSY);
while (EIC->STATUS.reg & EIC_STATUS_SYNCBUSY) {}
return 0;
}

20
cpu/samd21/periph/i2c.c
Unescape Escape View File

@ -96,7 +96,7 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
/* Reset I2C */
I2CSercom->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
while(I2CSercom->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(I2CSercom->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
/* Turn on power manager for sercom */
PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << (sercom_core - 20));
@ -105,12 +105,12 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(sercom_core));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(sercom_gclk_id_slow));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Check if module is enabled. */
@ -153,7 +153,7 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
/* I2C CONFIGURATION */
while(I2CSercom->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(I2CSercom->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
/* Set sercom module to operate in I2C master mode. */
I2CSercom->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER;
@ -338,7 +338,7 @@ void i2c_poweron(i2c_t dev)
switch (dev) {
#if I2C_0_EN
case I2C_0:
while(I2C_0_DEV.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(I2C_0_DEV.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
I2C_0_DEV.CTRLA.bit.ENABLE = 1;
break;
#endif
@ -352,7 +352,7 @@ void i2c_poweroff(i2c_t dev)
switch (dev) {
#if I2C_0_EN
case I2C_0:
while(I2C_0_DEV.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(I2C_0_DEV.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
I2C_0_DEV.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
break;
#endif
@ -367,7 +367,7 @@ static int _start(SercomI2cm *dev, uint8_t address, uint8_t rw_flag)
/* Wait for hardware module to sync */
DEBUG("Wait for device to be ready\n");
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
/* Set action to ACK. */
dev->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
@ -423,7 +423,7 @@ static inline int _write(SercomI2cm *dev, char *data, int length)
}
/* Wait for hardware module to sync */
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
DEBUG("Written %i byte to data reg, now waiting for DR to be empty again\n", buffer_counter);
dev->DATA.reg = data[buffer_counter++];
@ -463,7 +463,7 @@ static inline int _read(SercomI2cm *dev, char *data, int length)
}
/* Wait for hardware module to sync */
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
/* Save data to buffer. */
data[count] = dev->DATA.reg;
@ -486,7 +486,7 @@ static inline int _read(SercomI2cm *dev, char *data, int length)
static inline void _stop(SercomI2cm *dev)
{
/* Wait for hardware module to sync */
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
while(dev->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK) {}
/* Stop command */
dev->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
DEBUG("Stop sent\n");

14
cpu/samd21/periph/pwm.c
Unescape Escape View File

@ -117,7 +117,7 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
/* reset TCC module */
_tcc(dev)->CTRLA.reg = TCC_CTRLA_SWRST;
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) {}
/* set PWM mode */
switch (mode) {
case PWM_LEFT:
@ -130,17 +130,17 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
default:
return 0;
}
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {}
/* configure the TCC device */
_tcc(dev)->CTRLA.reg = (TCC_CTRLA_PRESCSYNC_GCLK_Val
| TCC_CTRLA_PRESCALER(prescaler));
/* select the waveform generation mode -> normal PWM */
_tcc(dev)->WAVE.reg = (TCC_WAVE_WAVEGEN_NPWM);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) {}
/* set the selected period */
_tcc(dev)->PER.reg = (res - 1);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_PER);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) {}
/* start PWM operation */
pwm_start(dev);
/* return the actual frequency the PWM is running at */
@ -159,7 +159,7 @@ void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
return;
}
_tcc(dev)->CC[_chan(dev, channel)].reg = value;
while (_tcc(dev)->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << _chan(dev, channel)));
while (_tcc(dev)->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << _chan(dev, channel))) {}
}
void pwm_start(pwm_t dev)
@ -182,7 +182,7 @@ void pwm_poweron(pwm_t dev)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_ID(_clk_id(dev)));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
}
void pwm_poweroff(pwm_t dev)
@ -194,5 +194,5 @@ void pwm_poweroff(pwm_t dev)
PM->APBCMASK.reg &= ~(PM_APBCMASK_TCC0 << num);
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN_GCLK7 |
GCLK_CLKCTRL_ID(_clk_id(dev)));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
}

32
cpu/samd21/periph/rtc.c
Unescape Escape View File

@ -53,26 +53,26 @@ void rtc_init(void)
/* Setup clock GCLK2 with OSC32K divided by 32 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)|GCLK_GENDIV_DIV(4);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_DIVSEL );
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
GCLK->CLKCTRL.reg = (uint32_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (RTC_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* DISABLE RTC MASTER */
while (rtcMode2->STATUS.reg & RTC_STATUS_SYNCBUSY);
while (rtcMode2->STATUS.reg & RTC_STATUS_SYNCBUSY) {}
rtc_poweroff();
/* Reset RTC */
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
rtcMode2->CTRL.reg= RTC_MODE2_CTRL_SWRST;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
/* RTC config with RTC_MODE2_CTRL_CLKREP = 0 (24h) */
rtcMode2->CTRL.reg = RTC_MODE2_CTRL_PRESCALER_DIV1024|RTC_MODE2_CTRL_MODE_CLOCK;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
rtcMode2->INTENSET.reg = RTC_MODE2_INTENSET_OVF;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
rtc_poweron();
}
@ -90,7 +90,7 @@ int rtc_set_time(struct tm *time)
| RTC_MODE2_CLOCK_MINUTE(time->tm_min)
| RTC_MODE2_CLOCK_SECOND(time->tm_sec);
}
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
return 0;
}
@ -106,7 +106,7 @@ int rtc_get_time(struct tm *time)
time->tm_hour = rtcMode2->CLOCK.bit.HOUR;
time->tm_min = rtcMode2->CLOCK.bit.MINUTE;
time->tm_sec = rtcMode2->CLOCK.bit.SECOND;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
return 0;
}
@ -126,7 +126,7 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
| RTC_MODE2_ALARM_SECOND(time->tm_sec);
rtcMode2->Mode2Alarm[0].MASK.reg = RTC_MODE2_MASK_SEL(6);
}
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
/* Setup interrupt */
NVIC_EnableIRQ(RTC_IRQn);
@ -135,9 +135,9 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
rtc_callback.cb = cb;
rtc_callback.arg = arg;
rtcMode2->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
rtcMode2->INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
return 0;
}
@ -154,7 +154,7 @@ int rtc_get_alarm(struct tm *time)
time->tm_hour = rtcMode2->Mode2Alarm[0].ALARM.bit.HOUR;
time->tm_min = rtcMode2->Mode2Alarm[0].ALARM.bit.MINUTE;
time->tm_sec = rtcMode2->Mode2Alarm[0].ALARM.bit.SECOND;
while(rtcMode2->STATUS.bit.SYNCBUSY);
while(rtcMode2->STATUS.bit.SYNCBUSY) {}
return 0;
}
@ -171,14 +171,14 @@ void rtc_poweron(void)
{
RtcMode2 *rtcMode2 = &(RTC_DEV);
rtcMode2->CTRL.bit.ENABLE = 1;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
}
void rtc_poweroff(void)
{
RtcMode2 *rtcMode2 = &(RTC_DEV);
rtcMode2->CTRL.bit.ENABLE = 0;
while (rtcMode2->STATUS.bit.SYNCBUSY);
while (rtcMode2->STATUS.bit.SYNCBUSY) {}
}
void isr_rtc(void)

20
cpu/samd21/periph/rtt.c
Unescape Escape View File

@ -72,7 +72,7 @@ void rtt_init(void)
/* Setup clock GCLK2 with divider 1 */
GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Enable GCLK2 with XOSC32K as source. Use divider without modification
* and keep running in standby. */
@ -82,24 +82,24 @@ void rtt_init(void)
GCLK_GENCTRL_RUNSTDBY |
#endif
GCLK_GENCTRL_SRC_XOSC32K;
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Connect GCLK2 to RTC */
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK2 |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_ID(RTC_GCLK_ID);
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Disable RTC */
rtt_poweroff();
/* Reset RTC */
rtcMode0->CTRL.bit.SWRST = 1;
while (rtcMode0->STATUS.bit.SYNCBUSY || rtcMode0->CTRL.bit.SWRST);
while (rtcMode0->STATUS.bit.SYNCBUSY || rtcMode0->CTRL.bit.SWRST) {}
/* Configure as 32bit counter with no prescaler and no clear on match compare */
rtcMode0->CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV1;
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
/* Setup interrupt */
NVIC_EnableIRQ(RTT_IRQ);
@ -132,7 +132,7 @@ void rtt_clear_overflow_cb(void)
uint32_t rtt_get_counter(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
return rtcMode0->COUNT.reg;
}
@ -140,7 +140,7 @@ void rtt_set_counter(uint32_t counter)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->COUNT.reg = counter;
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
@ -150,7 +150,7 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->COMP[0].reg = alarm;
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
/* Enable Compare Interrupt and clear flag */
rtcMode0->INTFLAG.bit.CMP0 = 1;
@ -177,14 +177,14 @@ void rtt_poweron(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->CTRL.bit.ENABLE = 1;
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void rtt_poweroff(void)
{
RtcMode0 *rtcMode0 = &(RTT_DEV);
rtcMode0->CTRL.bit.ENABLE = 0;
while (rtcMode0->STATUS.bit.SYNCBUSY);
while (rtcMode0->STATUS.bit.SYNCBUSY) {}
}
void RTT_ISR(void)

26
cpu/samd21/periph/spi.c
Unescape Escape View File

@ -112,7 +112,7 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
| (SERCOM4_GCLK_ID_CORE << GCLK_CLKCTRL_ID_Pos)));
/* Setup clock */
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* Mux enable*/
SPI_0_SCLK_DEV.PINCFG[ SPI_0_SCLK_PIN ].bit.PMUXEN = 1;
SPI_0_MISO_DEV.PINCFG[ SPI_0_MISO_PIN ].bit.PMUXEN = 1;
@ -178,9 +178,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
return -1;
}
spi_dev->CTRLA.bit.ENABLE = 0; /* Disable spi to write confs */
while (spi_dev->SYNCBUSY.reg);
while (spi_dev->SYNCBUSY.reg) {}
spi_dev->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE_SPI_MASTER;
while (spi_dev->SYNCBUSY.reg);
while (spi_dev->SYNCBUSY.reg) {}
spi_dev->BAUD.bit.BAUD = (uint8_t) (((uint32_t)CLOCK_CORECLOCK) / (2 * f_baud) - 1); /* Syncronous mode*/
@ -190,9 +190,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
| (cpha << SERCOM_SPI_CTRLA_CPHA_Pos)
| (cpol << SERCOM_SPI_CTRLA_CPOL_Pos);
while (spi_dev->SYNCBUSY.reg);
while (spi_dev->SYNCBUSY.reg) {}
spi_dev->CTRLB.reg = (SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN);
while(spi_dev->SYNCBUSY.reg);
while(spi_dev->SYNCBUSY.reg) {}
spi_poweron(dev);
return 0;
}
@ -245,10 +245,10 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
#endif
}
while (!spi_dev->INTFLAG.bit.DRE); /* while data register is not empty*/
while (!spi_dev->INTFLAG.bit.DRE) {} /* while data register is not empty*/
spi_dev->DATA.bit.DATA = out;
while (!spi_dev->INTFLAG.bit.RXC); /* while receive is not complete*/
while (!spi_dev->INTFLAG.bit.RXC) {} /* while receive is not complete*/
tmp = (char)spi_dev->DATA.bit.DATA;
if (in != NULL)
@ -264,13 +264,13 @@ void spi_poweron(spi_t dev)
#ifdef SPI_0_EN
case SPI_0:
SPI_0_DEV.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
while(SPI_0_DEV.SYNCBUSY.bit.ENABLE);
while(SPI_0_DEV.SYNCBUSY.bit.ENABLE) {}
break;
#endif
#ifdef SPI_1_EN
case SPI_1:
SPI_1_DEV.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
while(SPI_1_DEV.SYNCBUSY.bit.ENABLE);
while(SPI_1_DEV.SYNCBUSY.bit.ENABLE) {}
break;
#endif
}
@ -281,14 +281,14 @@ void spi_poweroff(spi_t dev)
switch(dev) {
#ifdef SPI_0_EN
case SPI_0:
SPI_0_DEV.CTRLA.bit.ENABLE = 0; /*Disable spi*/
while(SPI_0_DEV.SYNCBUSY.bit.ENABLE);
SPI_0_DEV.CTRLA.bit.ENABLE = 0; /* Disable spi */
while(SPI_0_DEV.SYNCBUSY.bit.ENABLE) {}
break;
#endif
#ifdef SPI_1_EN
case SPI_1:
SPI_1_DEV.CTRLA.bit.ENABLE = 0; /*Disable spi*/
while(SPI_1_DEV.SYNCBUSY.bit.ENABLE);
SPI_1_DEV.CTRLA.bit.ENABLE = 0; /* Disable spi */
while(SPI_1_DEV.SYNCBUSY.bit.ENABLE) {}
break;
#endif
}

14
cpu/samd21/periph/timer.c
Unescape Escape View File

@ -54,7 +54,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
#if CLOCK_USE_PLL
/* configure GCLK1 (configured to 1MHz) to feed TC3, TC4 and TC5 */;
GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK1 | (TC3_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
/* TC4 and TC5 share the same channel */
GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK1 | (TC4_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
#else
@ -63,7 +63,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
/* TC4 and TC5 share the same channel */
GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (TC4_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
#endif
while (GCLK->STATUS.bit.SYNCBUSY);
while (GCLK->STATUS.bit.SYNCBUSY) {}
switch (dev) {
#if TIMER_0_EN
@ -74,7 +74,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
PM->APBCMASK.reg |= PM_APBCMASK_TC3;
/* reset timer */
TIMER_0_DEV.CTRLA.bit.SWRST = 1;
while (TIMER_0_DEV.CTRLA.bit.SWRST);
while (TIMER_0_DEV.CTRLA.bit.SWRST) {}
/* choosing 16 bit mode */
TIMER_0_DEV.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT16_Val;
#if CLOCK_USE_PLL
@ -97,7 +97,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
/* reset timer */
TIMER_1_DEV.CTRLA.bit.SWRST = 1;
while (TIMER_1_DEV.CTRLA.bit.SWRST);
while (TIMER_1_DEV.CTRLA.bit.SWRST) {}
TIMER_1_DEV.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT32_Val;
@ -237,17 +237,15 @@ unsigned int timer_read(tim_t dev)
case TIMER_0:
/* request syncronisation */
TIMER_0_DEV.READREQ.reg = TC_READREQ_RREQ | TC_READREQ_ADDR(0x10);
while (TIMER_0_DEV.STATUS.bit.SYNCBUSY);
while (TIMER_0_DEV.STATUS.bit.SYNCBUSY) {}
return TIMER_0_DEV.COUNT.reg;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
/* request syncronisation */
TIMER_1_DEV.READREQ.reg = TC_READREQ_RREQ | TC_READREQ_ADDR(0x10);
while (TIMER_1_DEV.STATUS.bit.SYNCBUSY);
while (TIMER_1_DEV.STATUS.bit.SYNCBUSY) {}
return TIMER_1_DEV.COUNT.reg;
break;
#endif
default:
return 0;

10
cpu/samd21/periph/uart.c
Unescape Escape View File

@ -85,7 +85,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
/* reset the UART device */
dev->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST);
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
/* set asynchronous mode w/o parity, LSB first, PAD0 to TX, PAD1 to RX and
* use internal clock */
dev->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
@ -97,7 +97,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
dev->BAUD.FRAC.BAUD = (baud / 10);
/* enable receiver and transmitter, use 1 stop bit */
dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB);
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
/* finally, enable the device */
dev->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
return 0;
@ -106,7 +106,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
for (size_t i = 0; i < len; i++) {
while (!(_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE));
while (!(_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
_uart(uart)->DATA.reg = data[i];
}
}
@ -118,7 +118,7 @@ void uart_poweron(uart_t uart)
GCLK_CLKCTRL_GEN_GCLK0 |
(SERCOM0_GCLK_ID_CORE + _sercom_id(_uart(uart))) <<
GCLK_CLKCTRL_ID_Pos);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
}
void uart_poweroff(uart_t uart)
@ -126,7 +126,7 @@ void uart_poweroff(uart_t uart)
PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << _sercom_id(_uart(uart)));
GCLK->CLKCTRL.reg = ((SERCOM0_GCLK_ID_CORE + _sercom_id(_uart(uart))) <<
GCLK_CLKCTRL_ID_Pos);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
}
static inline void irq_handler(int dev)

6
cpu/saml21/cpu.c
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@ -24,7 +24,7 @@
static void _gclk_setup(int gclk, uint32_t reg)
{
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk));
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(gclk)) {}
GCLK->GENCTRL[gclk].reg = reg;
}
@ -57,8 +57,8 @@ void cpu_init(void)
/* Software reset the GCLK module to ensure it is re-initialized correctly */
GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST);
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST);
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
/* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3;

2
cpu/saml21/lpm_arch.c
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@ -62,7 +62,7 @@ enum lpm_mode lpm_arch_set(enum lpm_mode target)
PM->SLEEPCFG.bit.SLEEPMODE = mode;
/* make sure value has been set */
while (PM->SLEEPCFG.bit.SLEEPMODE != mode);
while (PM->SLEEPCFG.bit.SLEEPMODE != mode) {}
/* ensure all memory accesses have completed */
__DSB();

2
cpu/saml21/periph/gpio.c
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