From 5d70656343daa1c896f34c45c72d07989afeccab Mon Sep 17 00:00:00 2001 From: Oliver Hahm Date: Fri, 21 Jun 2013 03:52:57 +0200 Subject: [PATCH] fixed coding conventions (mostly by astyle) --- cpu/arm_common/VIC.c | 65 +- cpu/arm_common/arm_cpu.c | 31 +- cpu/arm_common/bootloader.c | 94 +- cpu/arm_common/hwtimer_cpu.c | 172 ++-- cpu/arm_common/iap.c | 228 ++--- cpu/arm_common/include/VIC.h | 2 +- cpu/arm_common/include/arm_cpu.h | 2 +- cpu/arm_common/include/iap.h | 4 +- cpu/arm_common/profiling.c | 61 +- cpu/arm_common/syscalls.c | 107 ++- cpu/cc430/cc110x_cc430.c | 283 +++--- cpu/cc430/cc430-adc.c | 121 +-- cpu/cc430/cc430-gpioint.c | 107 ++- cpu/cc430/cc430-rtc.c | 73 +- cpu/cc430/hwtimer_cc430.c | 36 +- cpu/cc430/include/cc430-adc.h | 38 +- cpu/cc430/include/cc430-rtc.h | 10 +- cpu/lpc214x/cpu.c | 28 +- cpu/lpc214x/include/lpc214x.h | 2 +- cpu/lpc2387/cpu.c | 81 +- cpu/lpc2387/gpioint/lpc2387-gpioint.c | 184 ++-- cpu/lpc2387/include/cpu.h | 4 +- cpu/lpc2387/include/lpc2387-rtc.h | 24 +- cpu/lpc2387/include/lpc23xx.h | 480 +++++----- cpu/lpc2387/lpc2387-adc.c | 166 ++-- cpu/lpc2387/lpc2387-lpm.c | 103 +- cpu/lpc2387/lpc23xx-iap.c | 125 ++- cpu/lpc2387/mci/lpc2387-mci.c | 1168 +++++++++++++---------- cpu/lpc2387/rtc/lpc2387-rtc.c | 273 +++--- cpu/msp430-common/atomic.c | 3 +- cpu/msp430-common/cpu.c | 72 +- cpu/msp430-common/flashrom.c | 40 +- cpu/msp430-common/hwtimer_cpu.c | 44 +- cpu/msp430-common/include/cpu.h | 40 +- cpu/msp430-common/include/hwtimer_cpu.h | 4 +- cpu/msp430-common/include/malloc.h | 2 +- cpu/msp430-common/include/time.h | 17 +- cpu/msp430-common/irq.c | 33 +- cpu/msp430-common/msp430-main.c | 112 +-- cpu/msp430-common/startup.c | 3 +- cpu/msp430x16x/flashrom.c | 38 +- cpu/msp430x16x/hwtimer_msp430.c | 36 +- cpu/native/atomic_cpu.c | 2 +- cpu/native/cc110x_ng/cc110x_ng_cpu.c | 4 +- cpu/native/hwtimer_cpu.c | 65 +- cpu/native/irq_cpu.c | 149 +-- cpu/native/lpm_cpu.c | 13 +- cpu/native/native_cpu.c | 29 +- cpu/native/rtc/posix-rtc.c | 8 +- cpu/native/startup.c | 2 +- 50 files changed, 2596 insertions(+), 2192 deletions(-) diff --git a/cpu/arm_common/VIC.c b/cpu/arm_common/VIC.c index 7a5fccc0a..4f69deec4 100644 --- a/cpu/arm_common/VIC.c +++ b/cpu/arm_common/VIC.c @@ -26,42 +26,43 @@ Boston, MA 02111-1307, USA. */ static inline unsigned __get_cpsr(void) { - unsigned long retval; - asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ ); - return retval; + unsigned long retval; + asm volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */); + return retval; } int inISR(void) { - int retval; - asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ ); - return (retval & INTMode) == 18; + int retval; + asm volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */); + return (retval & INTMode) == 18; } static inline void __set_cpsr(unsigned val) { - asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) ); + asm volatile(" msr cpsr, %0" : /* no outputs */ : "r"(val)); } unsigned disableIRQ(void) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr | IRQ_MASK); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr(_cpsr | IRQ_MASK); + return _cpsr; } unsigned restoreIRQ(unsigned oldCPSR) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK)); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK)); + return _cpsr; } -unsigned IRQenabled(void) { +unsigned IRQenabled(void) +{ unsigned _cpsr; _cpsr = __get_cpsr(); @@ -70,38 +71,38 @@ unsigned IRQenabled(void) { unsigned enableIRQ(void) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr & ~IRQ_MASK); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr(_cpsr & ~IRQ_MASK); + return _cpsr; } unsigned disableFIQ(void) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr | FIQ_MASK); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr(_cpsr | FIQ_MASK); + return _cpsr; } unsigned restoreFIQ(unsigned oldCPSR) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK)); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK)); + return _cpsr; } unsigned enableFIQ(void) { - unsigned _cpsr; + unsigned _cpsr; - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr & ~FIQ_MASK); - return _cpsr; + _cpsr = __get_cpsr(); + __set_cpsr(_cpsr & ~FIQ_MASK); + return _cpsr; } diff --git a/cpu/arm_common/arm_cpu.c b/cpu/arm_common/arm_cpu.c index 8283d1588..c9384dd3a 100644 --- a/cpu/arm_common/arm_cpu.c +++ b/cpu/arm_common/arm_cpu.c @@ -16,7 +16,7 @@ * @} */ /** - * + * * * */ @@ -41,7 +41,7 @@ void thread_yield(void) char *thread_stack_init(void *task_func, void *stack_start, int stack_size) { unsigned int *stk; - stk = (unsigned int *) (stack_start + stack_size); + stk = (unsigned int *)(stack_start + stack_size); stk--; *stk = STACK_MARKER; @@ -52,10 +52,10 @@ char *thread_stack_init(void *task_func, void *stack_start, int stack_size) /* set the stack pointer (SP) */ stk--; - *stk = (unsigned int) (stack_start + stack_size) - 4; + *stk = (unsigned int)(stack_start + stack_size) - 4; /* build base stack */ - for (int i = REGISTER_CNT; i>= 0 ; i--) { + for(int i = REGISTER_CNT; i >= 0 ; i--) { stk--; *stk = i; } @@ -67,32 +67,35 @@ char *thread_stack_init(void *task_func, void *stack_start, int stack_size) stk--; *stk = (unsigned int) NEW_TASK_CPSR; - return (char*) stk; + return (char *)stk; } void thread_print_stack(void) { register void *stack = 0; - asm( "mov %0, sp" : "=r" (stack)); + asm("mov %0, sp" : "=r"(stack)); - register unsigned int *s = (unsigned int*) stack; + register unsigned int *s = (unsigned int *)stack; printf("task: %X SP: %X\n", (unsigned int) active_thread, (unsigned int) stack); register int i = 0; s += 5; - while (*s != STACK_MARKER) { + + while(*s != STACK_MARKER) { printf("STACK (%u) addr=%X = %X \n", i, (unsigned int) s, (unsigned int) *s); s++; i++; } - printf("STACK (%u)= %X \n",i,*s); + + printf("STACK (%u)= %X \n", i, *s); } -__attribute__((naked,noreturn)) void arm_reset(void) +__attribute__((naked, noreturn)) void arm_reset(void) { dINT(); - WDTC = 0x00FFF; - WDMOD = 0x03; - WDFEED= 0xAA; - WDFEED= 0x55; + WDTC = 0x00FFF; + WDMOD = 0x03; + WDFEED = 0xAA; + WDFEED = 0x55; + while(1); } diff --git a/cpu/arm_common/bootloader.c b/cpu/arm_common/bootloader.c index 56bfc3995..9c367e98b 100644 --- a/cpu/arm_common/bootloader.c +++ b/cpu/arm_common/bootloader.c @@ -48,58 +48,67 @@ and the mailinglist (subscription via web site) #include #include -void FIQ_Routine (void) __attribute__ ((interrupt("FIQ"))); +void FIQ_Routine(void) __attribute__((interrupt("FIQ"))); //void SWI_Routine (void) __attribute__ ((interrupt("SWI"))); -void UNDEF_Routine (void) __attribute__ ((interrupt("UNDEF"))); +void UNDEF_Routine(void) __attribute__((interrupt("UNDEF"))); -void IRQ_Routine (void) { +void IRQ_Routine(void) +{ printf("Kernel Panic,\nEarly IRQ call\n"); - while(1){}; + + while(1) {}; } /*-----------------------------------------------------------------------------------*/ -void FIQ_Routine (void) { +void FIQ_Routine(void) +{ printf("Kernel Panic,\nEarly FIQ call\n"); - while(1){}; + + while(1) {}; } /*-----------------------------------------------------------------------------------*/ -void SWI_Routine (void) { +void SWI_Routine(void) +{ printf("Kernel Panic,\nEarly SWI call\n"); - while(1){}; + + while(1) {}; } /*-----------------------------------------------------------------------------------*/ -void DEBUG_Routine (void) { +void DEBUG_Routine(void) +{ printf("DEBUG hit."); - while(1){}; + + while(1) {}; } /*-----------------------------------------------------------------------------------*/ volatile int arm_abortflag = 0; -void abtorigin(const char* vector, u_long* lnk_ptr1) +void abtorigin(const char *vector, u_long *lnk_ptr1) { - register u_long* lnk_ptr2; - register unsigned long* sp; + register u_long *lnk_ptr2; + register unsigned long *sp; register unsigned int cpsr, spsr; - __asm__ __volatile__("mrs %0, cpsr" : "=r" (cpsr) ); // copy current mode - __asm__ __volatile__("mrs %0, spsr" : "=r" (spsr) ); // copy dabt generating mode - __asm__ __volatile__("msr cpsr_c, %0" :: "r" (spsr) ); // switch to dabt generating mode - __asm__ __volatile__("mov %0, lr" : "=r" (lnk_ptr2)); // copy lr - __asm__ __volatile__("mov %0, sp" : "=r" (sp)); // copy sp - __asm__ __volatile__("msr cpsr_c, %0" :: "r" (cpsr) ); // switch back to abt mode + __asm__ __volatile__("mrs %0, cpsr" : "=r"(cpsr)); // copy current mode + __asm__ __volatile__("mrs %0, spsr" : "=r"(spsr)); // copy dabt generating mode + __asm__ __volatile__("msr cpsr_c, %0" :: "r"(spsr)); // switch to dabt generating mode + __asm__ __volatile__("mov %0, lr" : "=r"(lnk_ptr2)); // copy lr + __asm__ __volatile__("mov %0, sp" : "=r"(sp)); // copy sp + __asm__ __volatile__("msr cpsr_c, %0" :: "r"(cpsr)); // switch back to abt mode printf("#! %s abort at %p (0x%08lX) originating from %p (0x%08lX) in mode 0x%X\n", - vector, (void*)lnk_ptr1, *(lnk_ptr1), (void*)lnk_ptr2, *(lnk_ptr2), spsr - ); + vector, (void *)lnk_ptr1, *(lnk_ptr1), (void *)lnk_ptr2, *(lnk_ptr2), spsr + ); stdio_flush(); exit(1); } /*-----------------------------------------------------------------------------------*/ -void UNDEF_Routine (void) { - register u_long* lnk_ptr; - __asm__ __volatile__("sub %0, lr, #8" : "=r" (lnk_ptr) ); // get aborting instruction +void UNDEF_Routine(void) +{ + register u_long *lnk_ptr; + __asm__ __volatile__("sub %0, lr, #8" : "=r"(lnk_ptr)); // get aborting instruction - if( arm_abortflag == 0 ) { + if(arm_abortflag == 0) { arm_abortflag = 1; // remember state (if printing should fail again) abtorigin("undef", lnk_ptr); } @@ -107,11 +116,12 @@ void UNDEF_Routine (void) { exit(1); } /*-----------------------------------------------------------------------------------*/ -void PABT_Routine (void) { - register u_long* lnk_ptr; - __asm__ __volatile__("sub %0, lr, #8" : "=r" (lnk_ptr) ); // get aborting instruction +void PABT_Routine(void) +{ + register u_long *lnk_ptr; + __asm__ __volatile__("sub %0, lr, #8" : "=r"(lnk_ptr)); // get aborting instruction - if( arm_abortflag == 0 ) { + if(arm_abortflag == 0) { arm_abortflag = 1; // remember state (if printing should fail again) abtorigin("pabt", lnk_ptr); } @@ -119,11 +129,12 @@ void PABT_Routine (void) { exit(1); } /*-----------------------------------------------------------------------------------*/ -void DABT_Routine (void) { - register u_long* lnk_ptr; - __asm__ __volatile__("sub %0, lr, #8" : "=r" (lnk_ptr) ); // get aborting instruction +void DABT_Routine(void) +{ + register u_long *lnk_ptr; + __asm__ __volatile__("sub %0, lr, #8" : "=r"(lnk_ptr)); // get aborting instruction - if( arm_abortflag == 0 ) { + if(arm_abortflag == 0) { arm_abortflag = 1; // remember state (if printing should fail again) abtorigin("data", lnk_ptr); } @@ -140,27 +151,32 @@ bl_init_data(void) extern unsigned int __bss_start; extern unsigned int __bss_end; - register unsigned int* p1; - register unsigned int* p2; - register unsigned int* p3; + register unsigned int *p1; + register unsigned int *p2; + register unsigned int *p3; // initialize data from flash // (linker script ensures that data is 32-bit aligned) p1 = &_etext; p2 = &_data; p3 = &_edata; - while( p2 < p3 ) + + while(p2 < p3) { *p2++ = *p1++; + } // clear bss // (linker script ensures that bss is 32-bit aligned) p1 = &__bss_start; p2 = &__bss_end; - while( p1 < p2 ) + + while(p1 < p2) { *p1++ = 0; + } } /*-----------------------------------------------------------------------------------*/ -void bootloader(void) { +void bootloader(void) +{ extern void bl_uart_init(void); extern void bl_init_ports(void); extern void bl_init_clks(void); diff --git a/cpu/arm_common/hwtimer_cpu.c b/cpu/arm_common/hwtimer_cpu.c index beadde760..5767ff702 100644 --- a/cpu/arm_common/hwtimer_cpu.c +++ b/cpu/arm_common/hwtimer_cpu.c @@ -5,8 +5,10 @@ * @brief ARM kernel timer CPU dependent functions implementation * * @author Freie Universität Berlin, Computer Systems & Telematics + * @author INRIA * @author Thomas Hillebrandt * @author Heiko Will + * @author Oliver Hahm * */ @@ -18,87 +20,98 @@ #define VULP(x) ((volatile unsigned long*) (x)) -/// High level interrupt handler +/*/ High level interrupt handler */ static void (*int_handler)(int); -/// Timer 0-3 interrupt handler +/*/ Timer 0-3 interrupt handler */ static void timer_irq(void) __attribute__((interrupt("IRQ"))); -inline static unsigned long get_base_address(short timer) { - return (volatile unsigned long)(TMR0_BASE_ADDR + (timer / 8) * 0x6C000 + (timer/4 - (timer/8)*2) * 0x4000); +inline static unsigned long get_base_address(short timer) +{ + return (volatile unsigned long)(TMR0_BASE_ADDR + (timer / 8) * 0x6C000 + (timer / 4 - (timer / 8) * 2) * 0x4000); } static void timer_irq(void) { short timer = 0; - if (T0IR) { + + if(T0IR) { timer = 0; - } else if (T1IR) { + } + else if(T1IR) { timer = 4; - } else if (T2IR) { + } + else if(T2IR) { timer = 8; } volatile unsigned long base = get_base_address(timer); - if (*VULP(base+TXIR) & BIT0) { - *VULP(base+TXMCR) &= ~BIT0; - *VULP(base+TXIR) = BIT0; + if(*VULP(base + TXIR) & BIT0) { + *VULP(base + TXMCR) &= ~BIT0; + *VULP(base + TXIR) = BIT0; int_handler(timer); } - if (*VULP(base+TXIR) & BIT1) { - *VULP(base+TXMCR) &= ~BIT3; - *VULP(base+TXIR) = BIT1; + + if(*VULP(base + TXIR) & BIT1) { + *VULP(base + TXMCR) &= ~BIT3; + *VULP(base + TXIR) = BIT1; int_handler(timer + 1); } - if (*VULP(base+TXIR) & BIT2) { - *VULP(base+TXMCR) &= ~BIT6; - *VULP(base+TXIR) = BIT2; + + if(*VULP(base + TXIR) & BIT2) { + *VULP(base + TXMCR) &= ~BIT6; + *VULP(base + TXIR) = BIT2; int_handler(timer + 2); } - if (*VULP(base+TXIR) & BIT3) { - *VULP(base+TXMCR) &= ~BIT9; - *VULP(base+TXIR) = BIT3; + + if(*VULP(base + TXIR) & BIT3) { + *VULP(base + TXMCR) &= ~BIT9; + *VULP(base + TXIR) = BIT3; int_handler(timer + 3); } - VICVectAddr = 0; // acknowledge interrupt (if using VIC IRQ) + VICVectAddr = 0; /* acknowledge interrupt (if using VIC IRQ) */ } -static void timer0_init(uint32_t cpsr) { - PCONP |= PCTIM0; // power up timer - T0TCR = 2; // disable and reset timer - T0MCR = 0; // disable compare - T0CCR = 0; // capture is disabled - T0EMR = 0; // no external match output - T0PR = cpsr; // set prescaler +static void timer0_init(uint32_t cpsr) +{ + PCONP |= PCTIM0; /* power up timer */ + T0TCR = 2; /* disable and reset timer */ + T0MCR = 0; /* disable compare */ + T0CCR = 0; /* capture is disabled */ + T0EMR = 0; /* no external match output */ + T0PR = cpsr; /* set prescaler */ install_irq(TIMER0_INT, &timer_irq, 1); - T0TCR = 1; // reset counter + T0TCR = 1; /* reset counter */ } -static void timer1_init(uint32_t cpsr) { - PCONP |= PCTIM1; // power up timer - T1TCR = 2; // disable and reset timer - T1MCR = 0; // disable compare - T1CCR = 0; // capture is disabled - T1EMR = 0; // no external match output - T1PR = cpsr; // set prescaler +static void timer1_init(uint32_t cpsr) +{ + PCONP |= PCTIM1; /* power up timer */ + T1TCR = 2; /* disable and reset timer */ + T1MCR = 0; /* disable compare */ + T1CCR = 0; /* capture is disabled */ + T1EMR = 0; /* no external match output */ + T1PR = cpsr; /* set prescaler */ install_irq(TIMER1_INT, &timer_irq, 1); - T1TCR = 1; // reset counter + T1TCR = 1; /* reset counter */ } -static void timer2_init(uint32_t cpsr) { - PCONP |= PCTIM2; // power up timer - T2TCR = 2; // disable and reset timer - T2MCR = 0; // disable compare - T2CCR = 0; // capture is disabled - T2EMR = 0; // no external match output - T2PR = cpsr; // set prescaler +static void timer2_init(uint32_t cpsr) +{ + PCONP |= PCTIM2; /* power up timer */ + T2TCR = 2; /* disable and reset timer */ + T2MCR = 0; /* disable compare */ + T2CCR = 0; /* capture is disabled */ + T2EMR = 0; /* no external match output */ + T2PR = cpsr; /* set prescaler */ install_irq(TIMER2_INT, &timer_irq, 1); - T2TCR = 1; // reset counter + T2TCR = 1; /* reset counter */ } -void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) { +void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) +{ uint32_t cpsr; int_handler = handler; cpu_clock_scale(fcpu, HWTIMER_SPEED, &cpsr); @@ -109,7 +122,8 @@ void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) { /*---------------------------------------------------------------------------*/ -void hwtimer_arch_enable_interrupt(void) { +void hwtimer_arch_enable_interrupt(void) +{ VICIntEnable = 1 << TIMER0_INT; /* Enable Interrupt */ VICIntEnable = 1 << TIMER1_INT; /* Enable Interrupt */ VICIntEnable = 1 << TIMER2_INT; /* Enable Interrupt */ @@ -117,7 +131,8 @@ void hwtimer_arch_enable_interrupt(void) { /*---------------------------------------------------------------------------*/ -void hwtimer_arch_disable_interrupt(void) { +void hwtimer_arch_disable_interrupt(void) +{ VICIntEnClr = 1 << TIMER0_INT; /* Disable Interrupt */ VICIntEnClr = 1 << TIMER1_INT; /* Disable Interrupt */ VICIntEnClr = 1 << TIMER2_INT; /* Disable Interrupt */ @@ -125,56 +140,61 @@ void hwtimer_arch_disable_interrupt(void) { /*---------------------------------------------------------------------------*/ -void hwtimer_arch_set(unsigned long offset, short timer) { - // Calculate base address of timer register - // Timer 0-3 are matched to TIMER0 - // Timer 4-7 are matched to TIMER1 - // Timer 8-11 are matched to TIMER2 +void hwtimer_arch_set(unsigned long offset, short timer) +{ + /* Calculate base address of timer register */ + /* Timer 0-3 are matched to TIMER0 */ + /* Timer 4-7 are matched to TIMER1 */ + /* Timer 8-11 are matched to TIMER2 */ volatile unsigned long base = get_base_address(timer); - // Calculate match register address of corresponding timer + /* Calculate match register address of corresponding timer */ timer %= 4; unsigned long cpsr = disableIRQ(); - volatile unsigned long* addr = VULP(base + TXMR0 + 4 * timer); - // Calculate match register value + volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer); + /* Calculate match register value */ unsigned long value = *VULP(base + TXTC) + offset; - *addr = value; // set match register - *VULP(base+TXIR) = 0x01 << timer; // reset interrupt register value for corresponding match register - *VULP(base+TXMCR) &= ~(7 << (3 * timer)); // Clear all bits - *VULP(base+TXMCR) |= (MR0I << (3 * timer)); // enable interrupt for match register + *addr = value; /* set match register */ + *VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */ + *VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */ + *VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */ restoreIRQ(cpsr); } -void hwtimer_arch_set_absolute(unsigned long value, short timer) { - // Calculate base address of timer register - // Timer 0-3 are matched to TIMER0 - // Timer 4-7 are matched to TIMER1 - // Timer 8-11 are matched to TIMER2 +void hwtimer_arch_set_absolute(unsigned long value, short timer) +{ + /* Calculate base address of timer register */ + /* Timer 0-3 are matched to TIMER0 */ + /* Timer 4-7 are matched to TIMER1 */ + /* Timer 8-11 are matched to TIMER2 */ volatile unsigned long base = get_base_address(timer); - // Calculate match register address of corresponding timer + /* Calculate match register address of corresponding timer */ timer %= 4; - volatile unsigned long* addr = VULP(base + TXMR0 + 4 * timer); - // Calculate match register value - *addr = value; // set match register - *VULP(base+TXIR) = 0x01 << timer; // reset interrupt register value for corresponding match register - *VULP(base+TXMCR) &= ~(7 << (3 * timer)); // Clear all bits - *VULP(base+TXMCR) |= (MR0I << (3 * timer)); // enable interrupt for match register + volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer); + /* Calculate match register value */ + *addr = value; /* set match register */ + *VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */ + *VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */ + *VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */ } /*---------------------------------------------------------------------------*/ -void hwtimer_arch_unset(short timer) { +void hwtimer_arch_unset(short timer) +{ volatile unsigned long base = get_base_address(timer); timer %= 4; - *VULP(base+TXMCR) &= ~(MR0I << (3 * timer)); // disable interrupt for match register - *VULP(base+TXIR) = 0x01 << timer; // reset interrupt register value for corresponding match register + *VULP(base + TXMCR) &= ~(MR0I << (3 * timer)); /* disable interrupt for match register */ + *VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */ } /*---------------------------------------------------------------------------*/ -unsigned long hwtimer_arch_now(void) { +unsigned long hwtimer_arch_now(void) +{ return T0TC; } -void hwtimer_arch_setcounter(unsigned int val) { +void hwtimer_arch_setcounter(unsigned int val) +{ T0TC = val; } diff --git a/cpu/arm_common/iap.c b/cpu/arm_common/iap.c index 0f0b418ab..2b90ce1b0 100644 --- a/cpu/arm_common/iap.c +++ b/cpu/arm_common/iap.c @@ -1,8 +1,7 @@ /* iap driver - * + * * based on iap driver for LPC2148 Controller made by Andreas Weschenfelder, 2008 - * see: - * + * */ #include @@ -14,11 +13,11 @@ #include /* pointer to reserved flash rom section for configuration data */ -__attribute ((aligned(256))) char configmem[256] __attribute__ ((section (".configmem"))); +__attribute((aligned(256))) char configmem[256] __attribute__((section(".configmem"))); static unsigned int iap_command[5]; // contains parameters for IAP command static unsigned int iap_result[2]; // contains results -typedef void (*IAP) (unsigned int[],unsigned int[]); // typedefinition for IAP entry function +typedef void (*IAP)(unsigned int[], unsigned int[]); // typedefinition for IAP entry function IAP IAP_Entry; /* some function prototypes */ @@ -32,100 +31,101 @@ static uint32_t iap(uint32_t code, uint32_t p1, uint32_t p2, uint32_t p3, uint32 /****************************************************************************** * P U B L I C F U N C T I O N S *****************************************************************************/ -uint8_t flashrom_write(uint8_t *dst, char *src, size_t size) { - char err; - unsigned intstate; - uint8_t sec; - - //buffer_vic = VICIntEnable; // save interrupt enable - //VICIntEnClr = 0xFFFFFFFF; // clear vic - - sec = iap_get_sector((uint32_t) dst); - if (sec == INVALID_ADDRESS) { +uint8_t flashrom_write(uint8_t *dst, char *src, size_t size) +{ + char err; + unsigned intstate; + uint8_t sec; + + sec = iap_get_sector((uint32_t) dst); + + if(sec == INVALID_ADDRESS) { DEBUG("Invalid address\n"); return 0; } /* check sector */ - if(blank_check_sector(sec, sec) == SECTOR_NOT_BLANK) { - DEBUG("Warning: Sector %i not blank\n", sec); - } + if(blank_check_sector(sec, sec) == SECTOR_NOT_BLANK) { + DEBUG("Warning: Sector %i not blank\n", sec); + } /* prepare sector */ - err = prepare_sectors(sec, sec); - if (err) { - DEBUG("\n-- ERROR: PREPARE_SECTOR_FOR_WRITE_OPERATION: %u\n", err); - /* set interrupts back and return */ -// VICIntEnable = buffer_vic; - return 0; - } + err = prepare_sectors(sec, sec); + + if(err) { + DEBUG("\n-- ERROR: PREPARE_SECTOR_FOR_WRITE_OPERATION: %u\n", err); + return 0; + } /* write flash */ - else { + else { intstate = disableIRQ(); - err = copy_ram_to_flash((uint32_t) dst, (uint32_t) src, 256); + err = copy_ram_to_flash((uint32_t) dst, (uint32_t) src, 256); restoreIRQ(intstate); - if(err) { - DEBUG("ERROR: COPY_RAM_TO_FLASH: %u\n", err); + + if(err) { + DEBUG("ERROR: COPY_RAM_TO_FLASH: %u\n", err); /* set interrupts back and return */ restoreIRQ(intstate); -// VICIntEnable = buffer_vic; - return 0; - } + return 0; + } /* check result */ - else { - err = compare((uint32_t) dst, (uint32_t) src, 256); - if (err) { - DEBUG("ERROR: COMPARE: %i (at position %u)\n", err, iap_result[1]); - /* set interrupts back and return */ -// VICIntEnable = buffer_vic; - return 0; - } - else - { - DEBUG("Data successfully written!\n"); - /* set interrupts back and return */ -// VICIntEnable = buffer_vic; - return 1; - } - } - } + else { + err = compare((uint32_t) dst, (uint32_t) src, 256); + + if(err) { + DEBUG("ERROR: COMPARE: %i (at position %u)\n", err, iap_result[1]); + return 0; + } + else { + DEBUG("Data successfully written!\n"); + return 1; + } + } + } } -uint8_t flashrom_erase(uint8_t *addr) { +uint8_t flashrom_erase(uint8_t *addr) +{ uint8_t sec = iap_get_sector((uint32_t) addr); unsigned intstate; - - if (sec == INVALID_ADDRESS) { + + if(sec == INVALID_ADDRESS) { DEBUG("Invalid address\n"); return 0; } /* check sector */ - if (!blank_check_sector(sec, sec)) { - DEBUG("Sector already blank!\n"); - return 1; - } - /* prepare sector */ - if (prepare_sectors(sec, sec)) { - DEBUG("-- ERROR: PREPARE_SECTOR_FOR_WRITE_OPERATION --\n"); - return 0; - } + if(!blank_check_sector(sec, sec)) { + DEBUG("Sector already blank!\n"); + return 1; + } + + /* prepare sector */ + if(prepare_sectors(sec, sec)) { + DEBUG("-- ERROR: PREPARE_SECTOR_FOR_WRITE_OPERATION --\n"); + return 0; + } + intstate = disableIRQ(); + /* erase sector */ - if (erase_sectors(sec, sec)) { - DEBUG("-- ERROR: ERASE SECTOR --\n"); + if(erase_sectors(sec, sec)) { + DEBUG("-- ERROR: ERASE SECTOR --\n"); restoreIRQ(intstate); - return 0; - } + return 0; + } + restoreIRQ(intstate); + /* check again */ - if (blank_check_sector(sec, sec)) { - DEBUG("-- ERROR: BLANK_CHECK_SECTOR\n"); - return 0; - } - DEBUG("Sector successfully erased.\n"); - return 1; + if(blank_check_sector(sec, sec)) { + DEBUG("-- ERROR: BLANK_CHECK_SECTOR\n"); + return 0; + } + + DEBUG("Sector successfully erased.\n"); + return 1; } @@ -133,31 +133,32 @@ uint8_t flashrom_erase(uint8_t *addr) { * PRIVATE FUNCTIONS *****************************************************************************/ -static uint32_t iap(uint32_t code, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) { - iap_command[0] = code; // set command code - iap_command[1] = p1; // set 1st param - iap_command[2] = p2; // set 2nd param - iap_command[3] = p3; // set 3rd param - iap_command[4] = p4; // set 4th param - - ((void (*)())0x7ffffff1)(iap_command, iap_result); // IAP entry point - return *iap_result; +static uint32_t iap(uint32_t code, uint32_t p1, uint32_t p2, uint32_t p3, uint32_t p4) +{ + iap_command[0] = code; // set command code + iap_command[1] = p1; // set 1st param + iap_command[2] = p2; // set 2nd param + iap_command[3] = p3; // set 3rd param + iap_command[4] = p4; // set 4th param + + ((void (*)())0x7ffffff1)(iap_command, iap_result); // IAP entry point + return *iap_result; } /****************************************************************************** * Function: blank_check_sector - * - * Description: This command is used to blank check a sector or multiple sectors + * + * Description: This command is used to blank check a sector or multiple sectors * of on-chip Flash memory. To blank check a single sector use the * same "Start" and "End" sector numbers. * Command: 53 * Param0: Start Sector Number - * Param1: End Sector Number (should be greater than equal to the start + * Param1: End Sector Number (should be greater than equal to the start * sector number) - * + * * Parameters: long tmp_sect1: Param0 * long tmp_sect2: Param1 - * + * * Return: Code CMD_SUCCESS | * BUSY | * SECTOR_NOT_BLANK | @@ -165,29 +166,30 @@ static uint32_t iap(uint32_t code, uint32_t p1, uint32_t p2, uint32_t p3, uint32 * Result0: Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK. * Result1: Contents of non blank wird location. *****************************************************************************/ -uint32_t blank_check_sector(uint32_t tmp_sect1, uint32_t tmp_sect2) { - return iap(BLANK_CHECK_SECTOR, tmp_sect1, tmp_sect2, 0 , 0); +uint32_t blank_check_sector(uint32_t tmp_sect1, uint32_t tmp_sect2) +{ + return iap(BLANK_CHECK_SECTOR, tmp_sect1, tmp_sect2, 0 , 0); } /****************************************************************************** * Function: copy_ram_to_flash - * - * Description: This command is used to programm the flash memory. the affected should be - * prepared first by calling "Prepare Sector for Write Operation" command. the + * + * Description: This command is used to programm the flash memory. the affected should be + * prepared first by calling "Prepare Sector for Write Operation" command. the * affected sectors are automatically protected again once the copy command is * successfully executed. the boot sector cannot be written by this command. * Command: 51 - * Param0: (DST) Destination Flash adress where data bytes are to be written. + * Param0: (DST) Destination Flash adress where data bytes are to be written. * This address should be a 512 byte boundary. * Param1: (SRC) Source RAM adress from which data byre are to be read. * Param2: Number of bytes to be written. Should be 512 | 1024 | 4096 | 8192. * Param3: System Clock Frequency (CCLK) in KHz. - * + * * Parameters: long tmp_adr_dst: Param0 * long tmp_adr_src: Param1 * long tmp_size: Param2 - * + * * Return: Code CMD_SUCCESS | * SRC_ADDR_ERROR (Address not on word boundary) | * DST_ADDR_ERROR (Address not on correct boundary) | @@ -197,14 +199,15 @@ uint32_t blank_check_sector(uint32_t tmp_sect1, uint32_t tmp_sect2) { * SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | * BUSY *****************************************************************************/ -uint32_t copy_ram_to_flash(uint32_t tmp_adr_dst, uint32_t tmp_adr_src, uint32_t tmp_size) { - return iap(COPY_RAM_TO_FLASH, tmp_adr_dst, tmp_adr_src, tmp_size, _XTAL); +uint32_t copy_ram_to_flash(uint32_t tmp_adr_dst, uint32_t tmp_adr_src, uint32_t tmp_size) +{ + return iap(COPY_RAM_TO_FLASH, tmp_adr_dst, tmp_adr_src, tmp_size, _XTAL); } /****************************************************************************** * Function: Prepare_Sector - * + * * Description: This command must be executed before executing "Copy RAM to Flash" or "Erase Sector(s)" * command. Successful execution of the "Copy RAM to Flash" or "Erase Sector(s)" command causes * relevant sectors to be protected again. The boot sector can not be prepared by this command. To @@ -212,22 +215,23 @@ uint32_t copy_ram_to_flash(uint32_t tmp_adr_dst, uint32_t tmp_adr_src, uint32_t * Command code: 50 * Param0: Start Sector Number * Param1: End Sector Number: Should be greater than or equal to start sector number. - * + * * Parameters: long tmp_sect1: Param0 * long tmp_sect2: Param1 - * + * * Return: Code CMD_SUCCESS | * BUSY | * INVALID_SECTOR *****************************************************************************/ -uint32_t prepare_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) { - return iap(PREPARE_SECTOR_FOR_WRITE_OPERATION, tmp_sect1, tmp_sect2, 0 , 0); +uint32_t prepare_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) +{ + return iap(PREPARE_SECTOR_FOR_WRITE_OPERATION, tmp_sect1, tmp_sect2, 0 , 0); } /****************************************************************************** * Function: erase_sectors - * + * * Description: This command is used to erase a sector or multiple sectors of on-chip Flash memory. The boot * sector can not be erased by this command. To erase a single sector use the same "Start" and "End" * sector numbers. @@ -235,23 +239,24 @@ uint32_t prepare_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) { * Param0: Start Sector Number * Param1: End Sector Number: Should be greater than or equal to start sector number. * Param2: System Clock Frequency (CCLK) in KHz. - * + * * Parameters: long tmp_sect1: Param0 * long tmp_sect2: Param1 - * + * * Return: Code CMD_SUCCESS | * BUSY | * SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | * INVALID_SECTOR *****************************************************************************/ -uint32_t erase_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) { - return iap(ERASE_SECTOR, tmp_sect1, tmp_sect2, _XTAL, 0); +uint32_t erase_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) +{ + return iap(ERASE_SECTOR, tmp_sect1, tmp_sect2, _XTAL, 0); } /****************************************************************************** * Function: compare - * + * * Description: This command is used to compare the memory contents at two locations. compare result may not * be correct when source or destination address contains any of the first 64 bytes starting * from address zero. First 64 bytes can be re-mapped to RAM. @@ -261,11 +266,11 @@ uint32_t erase_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) { * Param1(SRC): Starting Flash or RAM address from where data bytes are to be * address should be a word boundary. * Param2: Number of bytes to be compared. Count should be in multiple of 4. - * + * * Parameters: long tmp_adr_dst - * long tmp_adr_src + * long tmp_adr_src * long tmp_size - * + * * Return: Code CMD_SUCCESS | * COMPARE_ERROR | * COUNT_ERROR (Byte count is not multiple of 4) | @@ -273,6 +278,7 @@ uint32_t erase_sectors(uint32_t tmp_sect1, uint32_t tmp_sect2) { * ADDR_NOT_MAPPED * Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR. *****************************************************************************/ -uint32_t compare(uint32_t tmp_adr_dst, uint32_t tmp_adr_src, uint32_t tmp_size) { - return iap(COMPARE, tmp_adr_dst, tmp_adr_src, tmp_size, 0); +uint32_t compare(uint32_t tmp_adr_dst, uint32_t tmp_adr_src, uint32_t tmp_size) +{ + return iap(COMPARE, tmp_adr_dst, tmp_adr_src, tmp_size, 0); } diff --git a/cpu/arm_common/include/VIC.h b/cpu/arm_common/include/VIC.h index 953734374..1a3ccee2b 100644 --- a/cpu/arm_common/include/VIC.h +++ b/cpu/arm_common/include/VIC.h @@ -90,7 +90,7 @@ Boston, MA 02111-1307, USA. */ #include #include "cpu.h" -bool cpu_install_irq( int IntNumber, void *HandlerAddr, int Priority ); +bool cpu_install_irq(int IntNumber, void *HandlerAddr, int Priority); /** @} */ #endif /*ARMVIC_H_*/ diff --git a/cpu/arm_common/include/arm_cpu.h b/cpu/arm_common/include/arm_cpu.h index 91944ab81..84ed4cc1a 100644 --- a/cpu/arm_common/include/arm_cpu.h +++ b/cpu/arm_common/include/arm_cpu.h @@ -13,7 +13,7 @@ extern void eINT(void); void thread_yield(void); uint32_t get_system_speed(void); -void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale); +void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale); void arm_reset(void); void stdio_flush(void); diff --git a/cpu/arm_common/include/iap.h b/cpu/arm_common/include/iap.h index d2672f594..c4c14f848 100644 --- a/cpu/arm_common/include/iap.h +++ b/cpu/arm_common/include/iap.h @@ -40,9 +40,9 @@ /* * @brief: Converts 'addr' to sector number * @note: Sector table (Users Manual P. 610) - * + * * @param addr Flash address - * + * * @return Sector number. 0xFF on error */ uint8_t iap_get_sector(uint32_t addr); diff --git a/cpu/arm_common/profiling.c b/cpu/arm_common/profiling.c index c06f48dab..561fc8fec 100644 --- a/cpu/arm_common/profiling.c +++ b/cpu/arm_common/profiling.c @@ -23,50 +23,59 @@ static uint8_t function_pending = 0; static uint16_t traced_functions = 0; static uint8_t profiling = 0; -void __attribute__((__no_instrument_function__)) profiling_init(void) { +void __attribute__((__no_instrument_function__)) profiling_init(void) +{ uint16_t i; - for (i = 0; i < MAX_TRACED_FUNCTIONS; i++) { + + for(i = 0; i < MAX_TRACED_FUNCTIONS; i++) { functions[i].address = 0; functions[i].time = 0; functions[i].consumption = 0; functions[i].counter = 0; } - for (i = 0; i < PROFILING_STACK_SIZE; i++) { + + for(i = 0; i < PROFILING_STACK_SIZE; i++) { profiling_stack[i] = 0; } ltc4150_start(); - + profiling = 1; } -static int16_t __attribute__((__no_instrument_function__)) get_function_index(uint32_t addr) { +static int16_t __attribute__((__no_instrument_function__)) get_function_index(uint32_t addr) +{ uint16_t i; - for (i = 0; i < MAX_TRACED_FUNCTIONS; i++) { - if (functions[i].address == addr) { + + for(i = 0; i < MAX_TRACED_FUNCTIONS; i++) { + if(functions[i].address == addr) { return i; } } + return -1; } -void __attribute__((__no_instrument_function__)) __cyg_profile_func_enter (void *func, void *caller) { - if (!profiling) { +void __attribute__((__no_instrument_function__)) __cyg_profile_func_enter(void *func, void *caller) +{ + if(!profiling) { return; } + int16_t idx = get_function_index((uint32_t) func); + /* if function is not yet on traced */ - if ((idx < 0) && (traced_functions < MAX_TRACED_FUNCTIONS)) { + if((idx < 0) && (traced_functions < MAX_TRACED_FUNCTIONS)) { idx = traced_functions++; functions[idx].address = (uint32_t) func; } /* maximu of traceable functions reached */ - else if (idx < 0) { + else if(idx < 0) { return; } /* check if a profiled function is pending */ - if (function_pending && (profiling_stack[profiling_sp] != idx)) { + if(function_pending && (profiling_stack[profiling_sp] != idx)) { functions[idx].time += T0TC - functions[idx].start_time; //functions[idx].consumption += ltc4150_get_intcount() - functions[idx].consumption_start; functions[idx].consumption += ltc4150_get_total_mAh() - functions[idx].consumption_start; @@ -82,33 +91,41 @@ void __attribute__((__no_instrument_function__)) __cyg_profile_func_enter (void functions[idx].consumption_start = ltc4150_get_total_mAh(); // functions[idx].consumption_start = ltc4150_get_intcount(); } - -void __attribute__((__no_instrument_function__)) __cyg_profile_func_exit (void *func, void *caller) { - if (!profiling) { + +void __attribute__((__no_instrument_function__)) __cyg_profile_func_exit(void *func, void *caller) +{ + if(!profiling) { return; } + int16_t idx = get_function_index((uint32_t) func); - if (idx >= 0) { + + if(idx >= 0) { functions[idx].time += T0TC - functions[idx].start_time; //functions[idx].consumption += ltc4150_get_intcount() - functions[idx].consumption_start; functions[idx].consumption += ltc4150_get_total_mAh() - functions[idx].consumption_start; } + /* reset pending flag */ function_pending = 0; + /* if another function is pending */ - if (profiling_sp) { - if (--profiling_sp) { + if(profiling_sp) { + if(--profiling_sp) { functions[profiling_stack[profiling_sp]].start_time = T0TC; functions[profiling_stack[profiling_sp]].consumption_start = ltc4150_get_total_mAh(); } } } -void profiling_stats(void) { +void profiling_stats(void) +{ uint16_t i; - for (i = 0; i < traced_functions; i++) { -// printf("Function @%04lX was running %u times for %lu ticks, consuming %li ltc-ticks\n", functions[i].address, functions[i].counter, functions[i].time, functions[i].consumption); - printf("Function @%04lX was running %u times for %lu ticks, consuming %lf mAh\n", functions[i].address, functions[i].counter, functions[i].time, functions[i].consumption); + + for(i = 0; i < traced_functions; i++) { + // printf("Function @%04lX was running %u times for %lu ticks, consuming %li ltc-ticks\n", functions[i].address, functions[i].counter, functions[i].time, functions[i].consumption); + printf("Function @%04lX was running %u times for %lu ticks, consuming %lf mAh\n", functions[i].address, functions[i].counter, functions[i].time, functions[i].consumption); } + puts("________________________________________________________"); } diff --git a/cpu/arm_common/syscalls.c b/cpu/arm_common/syscalls.c index 1ed9d54fb..50d137118 100644 --- a/cpu/arm_common/syscalls.c +++ b/cpu/arm_common/syscalls.c @@ -74,23 +74,23 @@ extern uintptr_t __heap3_start; ///< start of heap memory space extern uintptr_t __heap3_max; ///< maximum for end of heap memory space -/// current position in heap -static caddr_t heap[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start}; // add heap3 before heap2 cause Heap3 address is lower then addr of heap2 -/// maximum position in heap -static const caddr_t heap_max[NUM_HEAPS] = {(caddr_t)&__heap1_max,(caddr_t)&__heap3_max,(caddr_t)&__heap2_max}; -// start position in heap -static const caddr_t heap_start[NUM_HEAPS] = {(caddr_t)&__heap1_start,(caddr_t)&__heap3_start,(caddr_t)&__heap2_start}; -// current heap in use +/* current position in heap */ +static caddr_t heap[NUM_HEAPS] = {(caddr_t) &__heap1_start, (caddr_t) &__heap3_start, (caddr_t) &__heap2_start}; // add heap3 before heap2 cause Heap3 address is lower then addr of heap2 +/* maximum position in heap */ +static const caddr_t heap_max[NUM_HEAPS] = {(caddr_t) &__heap1_max, (caddr_t) &__heap3_max, (caddr_t) &__heap2_max}; +/* start position in heap */ +static const caddr_t heap_start[NUM_HEAPS] = {(caddr_t) &__heap1_start, (caddr_t) &__heap3_start, (caddr_t) &__heap2_start}; +/* current heap in use */ volatile static uint8_t iUsedHeap = 0; /** @} */ /*-----------------------------------------------------------------------------------*/ -void heap_stats(void) +void heap_stats(void) { for(int i = 0; i < NUM_HEAPS; i++) printf("# heap %i: %p -- %p -> %p (%li of %li free)\n", i, heap_start[i], heap[i], heap_max[i], - (uint32_t)heap_max[i] - (uint32_t)heap[i], (uint32_t)heap_max[i] - (uint32_t)heap_start[i]); + (uint32_t)heap_max[i] - (uint32_t)heap[i], (uint32_t)heap_max[i] - (uint32_t)heap_start[i]); } /*-----------------------------------------------------------------------------------*/ @@ -100,7 +100,7 @@ void __assert_func(const char *file, int line, const char *func, const char *fai trace_number(TRACELOG_EV_ASSERTION, line); syslog(SL_EMERGENCY, "assert", "%s() in %s:%u\n", func, file, line); #endif - printf("#! assertion %s failed\n\t%s() in %s:%u\n", failedexpr, func, file, line ); + printf("#! assertion %s failed\n\t%s() in %s:%u\n", failedexpr, func, file, line); _exit(3); } /*-----------------------------------------------------------------------------------*/ @@ -111,8 +111,7 @@ void __assert(const char *file, int line, const char *failedexpr) /*-----------------------------------------------------------------------------------*/ caddr_t _sbrk_r(struct _reent *r, size_t incr) { - if(incr < 0) - { + if(incr < 0) { puts("[syscalls] Negative Values for _sbrk_r are not supported"); r->_errno = ENOMEM; return NULL; @@ -121,17 +120,18 @@ caddr_t _sbrk_r(struct _reent *r, size_t incr) uint32_t cpsr = disableIRQ(); /* check all heaps for a chunk of the requested size */ - for (; iUsedHeap < NUM_HEAPS; iUsedHeap++ ) { + for(; iUsedHeap < NUM_HEAPS; iUsedHeap++) { caddr_t new_heap = heap[iUsedHeap] + incr; - #ifdef MODULE_TRACELOG +#ifdef MODULE_TRACELOG trace_pointer(TRACELOG_EV_MEMORY, heap[iUsedHeap]); - #endif - if( new_heap <= heap_max[iUsedHeap] ) { +#endif + + if(new_heap <= heap_max[iUsedHeap]) { caddr_t prev_heap = heap[iUsedHeap]; - #ifdef MODULE_TRACELOG +#ifdef MODULE_TRACELOG trace_pointer(TRACELOG_EV_MEMORY, new_heap); - #endif +#endif heap[iUsedHeap] = new_heap; r->_errno = 0; @@ -139,10 +139,11 @@ caddr_t _sbrk_r(struct _reent *r, size_t incr) return prev_heap; } } + restoreIRQ(cpsr); - #ifdef MODULE_TRACELOG +#ifdef MODULE_TRACELOG trace_string(TRACELOG_EV_MEMORY, "heap!"); // heap full - #endif +#endif r->_errno = ENOMEM; return NULL; @@ -151,10 +152,13 @@ caddr_t _sbrk_r(struct _reent *r, size_t incr) int _isatty_r(struct _reent *r, int fd) { r->_errno = 0; - if( fd == STDOUT_FILENO || fd == STDERR_FILENO ) + + if(fd == STDOUT_FILENO || fd == STDERR_FILENO) { return 1; - else + } + else { return 0; + } } /*---------------------------------------------------------------------------*/ _off_t _lseek_r(struct _reent *r, int fd, _off_t pos, int whence) @@ -178,7 +182,7 @@ int _open_r(struct _reent *r, const char *name, int mode) r->_errno = ENODEV; // no such device #ifdef MODULE_FAT - ret = ff_open_r(r,name,mode); + ret = ff_open_r(r, name, mode); #endif PRINTF("open [%i] errno %i\n", ret, r->_errno); @@ -191,33 +195,36 @@ int _stat_r(struct _reent *r, char *name, struct stat *st) PRINTF("_stat_r '%s' \n", name); r->_errno = ENODEV; // no such device #ifdef MODULE_FAT - ret = ff_stat_r(r,name,st); + ret = ff_stat_r(r, name, st); #endif PRINTF("_stat_r [%i] errno %i\n", ret, r->_errno); return ret; } /*---------------------------------------------------------------------------*/ -int _fstat_r(struct _reent *r, int fd, struct stat * st) +int _fstat_r(struct _reent *r, int fd, struct stat *st) { int ret = -1; r->_errno = 0; memset(st, 0, sizeof(*st)); - if( fd == STDOUT_FILENO || fd == STDERR_FILENO ) { + + if(fd == STDOUT_FILENO || fd == STDERR_FILENO) { st->st_mode = S_IFCHR; ret = 0; - } else { + } + else { #ifdef MODULE_FAT PRINTF("_fstat_r '%i' \n", fd); - ret = ff_fstat_r(r,fd,st); + ret = ff_fstat_r(r, fd, st); PRINTF("_fstat_r [%i] errno %i\n", ret, r->_errno); #else r->_errno = ENODEV; #endif } + return ret; } /*---------------------------------------------------------------------------*/ @@ -229,20 +236,23 @@ int _write_r(struct _reent *r, int fd, const void *data, unsigned int count) switch(fd) { case STDOUT_FILENO: case STDERR_FILENO: - #if FEUERWARE_CONF_ENABLE_HAL - if( stdio != NULL ) - result = chardevice_write(stdio, (char*)data, count); - else if( hal_state == HAL_NOT_INITIALIZED ) - result = fw_puts((char*)data, count); - #else - result = fw_puts((char*)data, count); - #endif +#if FEUERWARE_CONF_ENABLE_HAL + if(stdio != NULL) { + result = chardevice_write(stdio, (char *)data, count); + } + else if(hal_state == HAL_NOT_INITIALIZED) { + result = fw_puts((char *)data, count); + } + +#else + result = fw_puts((char *)data, count); +#endif break; default: - #ifdef MODULE_FAT - result = ff_write_r(r, fd, data, count); - #endif +#ifdef MODULE_FAT + result = ff_write_r(r, fd, data, count); +#endif PRINTF("write [%i] data @%p count %i\n", fd, data, count); PRINTF("write [%i] returned %i errno %i\n", fd, result, r->_errno); @@ -261,7 +271,7 @@ int _read_r(struct _reent *r, int fd, void *buffer, unsigned int count) #endif PRINTF("read [%i] buffer @%p count %i\n", fd, buffer, count); PRINTF("read [%i] returned %i\n", fd, result); - + return result; } /*---------------------------------------------------------------------------*/ @@ -269,16 +279,16 @@ int _close_r(struct _reent *r, int fd) { int result = -1; r->_errno = EBADF; - #ifdef MODULE_FAT - ret = ff_close_r(r, fd); - #endif +#ifdef MODULE_FAT + ret = ff_close_r(r, fd); +#endif PRINTF("close [%i]\n", fd); PRINTF("close returned %i errno %i\n", result, errno); - + return result; } /*---------------------------------------------------------------------------*/ -int _unlink_r(struct _reent *r, char* path) +int _unlink_r(struct _reent *r, char *path) { int result = -1; r->_errno = ENODEV; @@ -287,7 +297,7 @@ int _unlink_r(struct _reent *r, char* path) #endif PRINTF("unlink '%s'\n", path); PRINTF("unlink returned %i errno %i\n", result, errno); - + return result; } /*---------------------------------------------------------------------------*/ @@ -300,6 +310,7 @@ void _exit(int n) stdio_flush(); arm_reset(); + while(1); } /*---------------------------------------------------------------------------*/ @@ -315,5 +326,5 @@ int _kill_r(struct _reent *r, int pid, int sig) return -1; } /*---------------------------------------------------------------------------*/ -void _init(void){} -void _fini(void){} +void _init(void) {} +void _fini(void) {} diff --git a/cpu/cc430/cc110x_cc430.c b/cpu/cc430/cc110x_cc430.c index 66b0d09dd..1c35b6474 100644 --- a/cpu/cc430/cc110x_cc430.c +++ b/cpu/cc430/cc110x_cc430.c @@ -5,180 +5,197 @@ #include #include -// ************************************************************************************************* -// @fn Strobe -// @brief Send command to radio. -// @param none -// @return none -// ************************************************************************************************* -uint8_t cc110x_strobe(uint8_t c) { - uint8_t statusByte = 0; - uint16_t int_state, gdo_state; - - // Check for valid strobe command - if((c == 0xBD) || ((c > RF_SRES) && (c < RF_SNOP))) { - int_state = disableIRQ(); - - // Clear the Status read flag - RF1AIFCTL1 &= ~(RFSTATIFG); - - // Wait for radio to be ready for next instruction - while( !(RF1AIFCTL1 & RFINSTRIFG)); - - // Write the strobe instruction - if ((c > RF_SRES) && (c < RF_SNOP)) - { - - gdo_state = cc110x_read_reg(IOCFG2); // buffer IOCFG2 state - cc110x_write_reg(IOCFG2, 0x29); // c-ready to GDO2 - - RF1AINSTRB = c; - if ((RF1AIN & 0x04) == 0x04 ) // chip at sleep mode - { - if ((c == RF_SXOFF) || (c == RF_SPWD) || (c == RF_SWOR) ) { } - else - { - while ((RF1AIN&0x04)== 0x04); // c-ready ? - hwtimer_wait(RTIMER_TICKS(9800)); // Delay for ~810usec at 12MHz CPU clock - } - } - cc110x_write_reg(IOCFG2, gdo_state); // restore IOCFG2 setting - } - else // chip active mode - { - RF1AINSTRB = c; - } - statusByte = RF1ASTATB; - while( !(RF1AIFCTL1 & RFSTATIFG) ); - restoreIRQ(int_state); - } - return statusByte; +/************************************************************************************************** + * @fn Strobe + * @brief Send command to radio. + * @param none + * @return none + *************************************************************************************************/ +uint8_t cc110x_strobe(uint8_t c) +{ + uint8_t statusByte = 0; + uint16_t int_state, gdo_state; + + /* Check for valid strobe command */ + if((c == 0xBD) || ((c > RF_SRES) && (c < RF_SNOP))) { + int_state = disableIRQ(); + + /* Clear the Status read flag */ + RF1AIFCTL1 &= ~(RFSTATIFG); + + /* Wait for radio to be ready for next instruction */ + while(!(RF1AIFCTL1 & RFINSTRIFG)); + + /* Write the strobe instruction */ + if((c > RF_SRES) && (c < RF_SNOP)) { + + gdo_state = cc110x_read_reg(IOCFG2); /* buffer IOCFG2 state */ + cc110x_write_reg(IOCFG2, 0x29); /* c-ready to GDO2 */ + + RF1AINSTRB = c; + + if((RF1AIN & 0x04) == 0x04) { /* chip at sleep mode */ + if((c == RF_SXOFF) || (c == RF_SPWD) || (c == RF_SWOR)) { } + else { + while((RF1AIN & 0x04) == 0x04); /* c-ready ? */ + + hwtimer_wait(RTIMER_TICKS(9800)); /* Delay for ~810usec at 12MHz CPU clock */ + } + } + + cc110x_write_reg(IOCFG2, gdo_state); /* restore IOCFG2 setting */ + } + else { /* chip active mode */ + RF1AINSTRB = c; + } + + statusByte = RF1ASTATB; + + while(!(RF1AIFCTL1 & RFSTATIFG)); + + restoreIRQ(int_state); + } + + return statusByte; } -// ************************************************************************************************* -// @fn cc110x_read_reg -// @brief Read byte from register. -// @param none -// @return none -// ************************************************************************************************* -uint8_t cc110x_read_reg(uint8_t addr) { - unsigned char x; - uint16_t int_state; +/*************************************************************************************************** + * @fn cc110x_read_reg + * @brief Read byte from register. + * @param none + * @return none + ***************************************************************************************************/ +uint8_t cc110x_read_reg(uint8_t addr) +{ + unsigned char x; + uint16_t int_state; - int_state = disableIRQ(); + int_state = disableIRQ(); - RF1AINSTR1B = (addr | RF_REGRD); - x = RF1ADOUT1B; + RF1AINSTR1B = (addr | RF_REGRD); + x = RF1ADOUT1B; restoreIRQ(int_state); - return x; + return x; } -// ************************************************************************************************* -// @fn cc110x_write_reg -// @brief Write byte to register. -// @param none -// @return none -// ************************************************************************************************* -void cc110x_write_reg(uint8_t addr, uint8_t value) { - volatile unsigned int i; - uint16_t int_state; +/************************************************************************************************** + * @fn cc110x_write_reg + * @brief Write byte to register. + * @param none + * @return none + **************************************************************************************************/ +void cc110x_write_reg(uint8_t addr, uint8_t value) +{ + volatile unsigned int i; + uint16_t int_state; int_state = disableIRQ(); - - while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for the next instruction - - RF1AINSTRW = ((addr | RF_REGWR)<<8 ) + value; // Send address + Instruction - while (!(RFDINIFG & RF1AIFCTL1)); - i = RF1ADOUTB; // Reset RFDOUTIFG flag which contains status byte + while(!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for the next instruction */ + + RF1AINSTRW = ((addr | RF_REGWR) << 8) + value; /* Send address + Instruction */ + + while(!(RFDINIFG & RF1AIFCTL1)); + + i = RF1ADOUTB; /* Reset RFDOUTIFG flag which contains status byte */ restoreIRQ(int_state); } -uint8_t cc110x_read_status(uint8_t addr) { +uint8_t cc110x_read_status(uint8_t addr) +{ unsigned char x; uint16_t int_state; int_state = disableIRQ(); - RF1AINSTR1B = (addr | RF_STATREGRD); + RF1AINSTR1B = (addr | RF_STATREGRD); x = RF1ADOUT1B; restoreIRQ(int_state); return x; } -// ************************************************************************************************* -// @fn cc110x_readburst_reg -// @brief Read sequence of bytes from register. -// @param none -// @return none -// ************************************************************************************************* -void cc110x_readburst_reg(uint8_t addr, char *buffer, uint8_t count) { - unsigned int i; - uint16_t int_state; +/**************************************************************************************************** + * @fn cc110x_readburst_reg + * @brief Read sequence of bytes from register. + * @param none + * @return none + ***************************************************************************************************/ +void cc110x_readburst_reg(uint8_t addr, char *buffer, uint8_t count) +{ + unsigned int i; + uint16_t int_state; int_state = disableIRQ(); - - while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for next instruction - RF1AINSTR1B = (addr | RF_REGRD); // Send address + Instruction - - for (i = 0; i < (count-1); i++) - { - while (!(RFDOUTIFG&RF1AIFCTL1)); // Wait for the Radio Core to update the RF1ADOUTB reg - buffer[i] = RF1ADOUT1B; // Read DOUT from Radio Core + clears RFDOUTIFG - // Also initiates auo-read for next DOUT byte - } - buffer[count-1] = RF1ADOUT0B; // Store the last DOUT from Radio Core + + while(!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */ + + RF1AINSTR1B = (addr | RF_REGRD); /* Send address + Instruction */ + + for(i = 0; i < (count - 1); i++) { + while(!(RFDOUTIFG & RF1AIFCTL1)); /* Wait for the Radio Core to update the RF1ADOUTB reg */ + + buffer[i] = RF1ADOUT1B; /* Read DOUT from Radio Core + clears RFDOUTIFG */ + /* Also initiates auo-read for next DOUT byte */ + } + + buffer[count - 1] = RF1ADOUT0B; /* Store the last DOUT from Radio Core */ restoreIRQ(int_state); -} - -void cc110x_read_fifo(char *buffer, uint8_t count) { - unsigned int i; - uint16_t int_state; +} + +void cc110x_read_fifo(char *buffer, uint8_t count) +{ + unsigned int i; + uint16_t int_state; int_state = disableIRQ(); - - while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for next instruction - RF1AINSTR1B = (RF_RXFIFORD); // Send address + Instruction - - for (i = 0; i < (count-1); i++) - { - while (!(RFDOUTIFG&RF1AIFCTL1)); // Wait for the Radio Core to update the RF1ADOUTB reg - buffer[i] = RF1ADOUT1B; // Read DOUT from Radio Core + clears RFDOUTIFG - // Also initiates auo-read for next DOUT byte - } - buffer[count-1] = RF1ADOUT0B; // Store the last DOUT from Radio Core + + while(!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */ + + RF1AINSTR1B = (RF_RXFIFORD); /* Send address + Instruction */ + + for(i = 0; i < (count - 1); i++) { + while(!(RFDOUTIFG & RF1AIFCTL1)); /* Wait for the Radio Core to update the RF1ADOUTB reg */ + + buffer[i] = RF1ADOUT1B; /* Read DOUT from Radio Core + clears RFDOUTIFG */ + /* Also initiates auo-read for next DOUT byte */ + } + + buffer[count - 1] = RF1ADOUT0B; /* Store the last DOUT from Radio Core */ restoreIRQ(int_state); } -// ************************************************************************************************* -// @fn cc110x_writeburst_reg -// @brief Write sequence of bytes to register. -// @param none -// @return none -// ************************************************************************************************* -uint8_t cc110x_writeburst_reg(uint8_t addr, char *buffer, uint8_t count) { - // Write Burst works wordwise not bytewise - bug known already - unsigned char i; - uint16_t int_state; +/*************************************************************************************************** + * @fn cc110x_writeburst_reg + * @brief Write sequence of bytes to register. + * @param none + * @return none + **************************************************************************************************/ +uint8_t cc110x_writeburst_reg(uint8_t addr, char *buffer, uint8_t count) +{ + /* Write Burst works wordwise not bytewise - bug known already */ + unsigned char i; + uint16_t int_state; int_state = disableIRQ(); - while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for next instruction - RF1AINSTRW = ((addr | RF_REGWR)<<8 ) + buffer[0]; // Send address + Instruction + while(!(RF1AIFCTL1 & RFINSTRIFG)); /* Wait for the Radio to be ready for next instruction */ + + RF1AINSTRW = ((addr | RF_REGWR) << 8) + buffer[0]; /* Send address + Instruction */ + + for(i = 1; i < count; i++) { + RF1ADINB = buffer[i]; /* Send data */ + + while(!(RFDINIFG & RF1AIFCTL1)); /* Wait for TX to finish */ + } + + i = RF1ADOUTB; /* Reset RFDOUTIFG flag which contains status byte */ - for (i = 1; i < count; i++) - { - RF1ADINB = buffer[i]; // Send data - while (!(RFDINIFG & RF1AIFCTL1)); // Wait for TX to finish - } - i = RF1ADOUTB; // Reset RFDOUTIFG flag which contains status byte - restoreIRQ(int_state); return count; } diff --git a/cpu/cc430/cc430-adc.c b/cpu/cc430/cc430-adc.c index 8621cbce3..e38f5cd8a 100644 --- a/cpu/cc430/cc430-adc.c +++ b/cpu/cc430/cc430-adc.c @@ -1,34 +1,34 @@ /* ************************************************************************************************* * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions * are met: - * - * Redistributions of source code must retain the above copyright + * + * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the * distribution. - * + * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * ************************************************************************************************* @@ -44,60 +44,64 @@ uint16_t adc12_result; uint8_t adc12_data_ready; -/* ************************************************************************************************* +/************************************************************************************************ * @fn adc12_single_conversion * @brief Init ADC12. Do single conversion. Turn off ADC12. * @param none * @return none - * ************************************************************************************************/ -uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel) { - /* Initialize the shared reference module */ - REFCTL0 |= REFMSTR + ref + REFON; /* Enable internal reference (1.5V or 2.5V) */ - - /* Initialize ADC12_A */ - ADC12CTL0 = sht + ADC12ON; /* Set sample time */ - ADC12CTL1 = ADC12SHP; /* Enable sample timer */ - ADC12MCTL0 = ADC12SREF_1 + channel; /* ADC input channel */ - ADC12IE = 0x001; /* ADC_IFG upon conv result-ADCMEMO */ + ************************************************************************************************/ +uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel) +{ + /* Initialize the shared reference module */ + REFCTL0 |= REFMSTR + ref + REFON; /* Enable internal reference (1.5V or 2.5V) */ + + /* Initialize ADC12_A */ + ADC12CTL0 = sht + ADC12ON; /* Set sample time */ + ADC12CTL1 = ADC12SHP; /* Enable sample timer */ + ADC12MCTL0 = ADC12SREF_1 + channel; /* ADC input channel */ + ADC12IE = 0x001; /* ADC_IFG upon conv result-ADCMEMO */ eINT(); - /* Wait 2 ticks (66us) to allow internal reference to settle */ + /* Wait 2 ticks (66us) to allow internal reference to settle */ hwtimer_wait(2); - - /* Start ADC12 */ - ADC12CTL0 |= ADC12ENC; - - /* Clear data ready flag */ - adc12_data_ready = 0; - - /* Sampling and conversion start */ - ADC12CTL0 |= ADC12SC; - + + /* Start ADC12 */ + ADC12CTL0 |= ADC12ENC; + + /* Clear data ready flag */ + adc12_data_ready = 0; + + /* Sampling and conversion start */ + ADC12CTL0 |= ADC12SC; + /* Wait until ADC12 has finished */ hwtimer_wait(5); - while (!adc12_data_ready); - - /* Shut down ADC12 */ - ADC12CTL0 &= ~(ADC12ENC | ADC12SC | sht); - ADC12CTL0 &= ~ADC12ON; - - /* Shut down reference voltage */ - REFCTL0 &= ~(REFMSTR + ref + REFON); - - ADC12IE = 0; - - /* Return ADC result */ - return adc12_result; + + while(!adc12_data_ready); + + /* Shut down ADC12 */ + ADC12CTL0 &= ~(ADC12ENC | ADC12SC | sht); + ADC12CTL0 &= ~ADC12ON; + + /* Shut down reference voltage */ + REFCTL0 &= ~(REFMSTR + ref + REFON); + + ADC12IE = 0; + + /* Return ADC result */ + return adc12_result; } -/* ************************************************************************************************* +/************************************************************************************************* * @fn ADC12ISR * @brief Store ADC12 conversion result. Set flag to indicate data ready. * @param none * @return none - * ************************************************************************************************/ -interrupt (ADC12_VECTOR) __attribute__ ((naked)) adc_isr (void) { + *************************************************************************************************/ +interrupt(ADC12_VECTOR) __attribute__((naked)) adc_isr(void) +{ __enter_isr(); + switch(ADC12IV) { case 0: break; /* Vector 0: No interrupt */ @@ -108,7 +112,7 @@ interrupt (ADC12_VECTOR) __attribute__ ((naked)) adc_isr (void) { case 6: /* Vector 6: ADC12IFG0 */ adc12_result = ADC12MEM0; /* Move results, IFG is cleared */ - adc12_data_ready = 1; + adc12_data_ready = 1; break; case 8: break; /* Vector 8: ADC12IFG1 */ @@ -141,6 +145,7 @@ interrupt (ADC12_VECTOR) __attribute__ ((naked)) adc_isr (void) { default: break; } + __exit_isr(); } diff --git a/cpu/cc430/cc430-gpioint.c b/cpu/cc430/cc430-gpioint.c index 9cd0da0b1..dc83081d7 100644 --- a/cpu/cc430/cc430-gpioint.c +++ b/cpu/cc430/cc430-gpioint.c @@ -51,178 +51,195 @@ uint16_t debounce_time[INT_PORTS][BITMASK_SIZE]; uint16_t c1 = 0, c2 = 0; -void gpioint_init(void) { +void gpioint_init(void) +{ uint8_t i, j; - for (i = 0; i < INT_PORTS; i++) { - for (j = 0; j < BITMASK_SIZE; j++) { + + for(i = 0; i < INT_PORTS; i++) { + for(j = 0; j < BITMASK_SIZE; j++) { cb[i][j] = NULL; debounce_time[i][j] = 0; } } } -bool gpioint_set(int port, uint32_t bitmask, int flags, fp_irqcb callback) { +bool gpioint_set(int port, uint32_t bitmask, int flags, fp_irqcb callback) +{ int8_t base; - if ((port >= PORTINT_MIN) && (port <= PORTINT_MAX)) { - /* set the callback function */ + if((port >= PORTINT_MIN) && (port <= PORTINT_MAX)) { + /* set the callback function */ base = number_of_highest_bit(bitmask); - if (base >= 0) { + + if(base >= 0) { cb[port - PORTINT_MIN][base] = callback; } else { return false; } - if (flags & GPIOINT_DEBOUNCE) { + + if(flags & GPIOINT_DEBOUNCE) { debounce_flags[port - PORTINT_MIN] |= bitmask; } else { debounce_flags[port - PORTINT_MIN] &= ~bitmask; } - } + } - switch (port) { + switch(port) { case 1: /* set port to input */ P1DIR &= ~bitmask; /* enable internal pull-down */ P1OUT &= ~bitmask; P1REN |= bitmask; - + /* reset IRQ flag */ P1IFG &= ~bitmask; /* trigger on rising... */ - if (flags & GPIOINT_RISING_EDGE) { + if(flags & GPIOINT_RISING_EDGE) { P1IES &= bitmask; } + /* ...or falling edge */ - if (flags & GPIOINT_FALLING_EDGE) { + if(flags & GPIOINT_FALLING_EDGE) { P1IES |= bitmask; } - + /* disable interrupt */ - if (flags == GPIOINT_DISABLE) { - P1IE &= ~bitmask; + if(flags == GPIOINT_DISABLE) { + P1IE &= ~bitmask; } + /* enable interrupt */ P1IE |= bitmask; break; + case 2: /* set port to input */ P2DIR &= ~bitmask; /* enable internal pull-down */ P2OUT &= ~bitmask; P2REN |= bitmask; - + /* reset IRQ flag */ P2IFG &= ~bitmask; /* trigger on rising... */ - if (flags == GPIOINT_RISING_EDGE) { + if(flags == GPIOINT_RISING_EDGE) { P2IES &= bitmask; } /* ...or falling edge */ - else if (flags == GPIOINT_FALLING_EDGE) { + else if(flags == GPIOINT_FALLING_EDGE) { P2IES |= bitmask; } /* or disable interrupt */ else { - P2IE &= ~bitmask; + P2IE &= ~bitmask; } + /* enable interrupt */ P2IE |= bitmask; break; - default: + + default: return false; } + return 1; } -interrupt (PORT1_VECTOR) __attribute__ ((naked)) port1_isr(void) { +interrupt(PORT1_VECTOR) __attribute__((naked)) port1_isr(void) +{ uint8_t int_enable, ifg_num, p1ifg; uint16_t p1iv; uint16_t diff; __enter_isr(); /* Debounce - * Disable PORT1 IRQ + * Disable PORT1 IRQ */ p1ifg = P1IFG; p1iv = P1IV; int_enable = P1IE; - P1IE = 0x00; + P1IE = 0x00; ifg_num = (p1iv >> 1) - 1; + /* check interrupt source */ - if (debounce_flags[0] & p1ifg) { + if(debounce_flags[0] & p1ifg) { /* check if bouncing */ diff = hwtimer_now() - debounce_time[0][ifg_num]; - if (diff > DEBOUNCE_TIMEOUT) { + + if(diff > DEBOUNCE_TIMEOUT) { debounce_time[0][ifg_num] = hwtimer_now(); - if (cb[0][ifg_num] != NULL) { + + if(cb[0][ifg_num] != NULL) { cb[0][ifg_num](); } } else { /* TODO: check for long duration irq */ - asm volatile (" nop "); + asm volatile(" nop "); } } else { - if (cb[0][ifg_num] != NULL) { + if(cb[0][ifg_num] != NULL) { cb[0][ifg_num](); } } - P1IFG = 0x00; - P1IE = int_enable; + + P1IFG = 0x00; + P1IE = int_enable; __exit_isr(); } -interrupt (PORT2_VECTOR) __attribute__ ((naked)) port2_isr(void) { +interrupt(PORT2_VECTOR) __attribute__((naked)) port2_isr(void) +{ uint8_t int_enable, ifg_num, p2ifg; uint16_t p2iv; uint16_t diff; __enter_isr(); /* Debounce - * Disable PORT2 IRQ + * Disable PORT2 IRQ */ p2ifg = P2IFG; p2iv = P2IV; int_enable = P2IE; - P2IE = 0x00; + P2IE = 0x00; ifg_num = (p2iv >> 1) - 1; + /* check interrupt source */ - if (debounce_flags[1] & p2ifg) { + if(debounce_flags[1] & p2ifg) { /* check if bouncing */ diff = hwtimer_now() - debounce_time[1][ifg_num]; - if (diff > DEBOUNCE_TIMEOUT) { + + if(diff > DEBOUNCE_TIMEOUT) { debounce_time[1][ifg_num] = hwtimer_now(); c1++; - if (cb[1][ifg_num] != NULL) { + + if(cb[1][ifg_num] != NULL) { cb[1][ifg_num](); } } else { c2++; /* TODO: check for long duration irq */ - asm volatile (" nop "); + asm volatile(" nop "); } } else { - if (cb[1][ifg_num] != NULL) { + if(cb[1][ifg_num] != NULL) { cb[1][ifg_num](); } } - - //else { - // cb[1][ifg_num](); - //} - P2IFG = 0x00; - P2IE = int_enable; + + P2IFG = 0x00; + P2IE = int_enable; __exit_isr(); } diff --git a/cpu/cc430/cc430-rtc.c b/cpu/cc430/cc430-rtc.c index 8c1caef25..2000acde9 100644 --- a/cpu/cc430/cc430-rtc.c +++ b/cpu/cc430/cc430-rtc.c @@ -31,7 +31,8 @@ static int set_time = 0; int rtc_second_pid = 0; /*---------------------------------------------------------------------------*/ -void rtc_init(void) { +void rtc_init(void) +{ /* Set to calendar mode */ RTCCTL1 |= RTCMODE_H; @@ -42,25 +43,26 @@ void rtc_init(void) { } /*---------------------------------------------------------------------------*/ -void rtc_enable(void) { +void rtc_enable(void) +{ /* Set RTC operational */ RTCCTL1 &= ~RTCHOLD_H; } /*---------------------------------------------------------------------------*/ -void rtc_disable(void) { +void rtc_disable(void) +{ /* Stop RTC */ RTCCTL1 |= RTCHOLD_H; } /*---------------------------------------------------------------------------*/ -void rtc_set_localtime(struct tm* localt) { - if(localt == NULL) { - return; +void rtc_set_localtime(struct tm *localt) +{ + if(localt == NULL) { + return; } /* copy time to be set */ memcpy(&time_to_set, localt, sizeof(struct tm)); - /* set interrupt to set this time after the next transition */ -// RTCCTL0 |= RTCRDYIE; set_time = 1; } @@ -83,45 +85,54 @@ time_t rtc_time(void) { } */ /*---------------------------------------------------------------------------*/ -void rtc_get_localtime(struct tm* localt) { +void rtc_get_localtime(struct tm *localt) +{ uint8_t success = 0; uint8_t i; uint16_t tmpyear; - if( localt == NULL ) { + if(localt == NULL) { return; } - while (!success) { - for (i = 0; i < 8; i++) { + while(!success) { + for(i = 0; i < 8; i++) { /* try again when RTC is in transition */ - if (!(RTCCTL1 & RTCRDY_H)) { + if(!(RTCCTL1 & RTCRDY_H)) { break; } - switch (i) { + + switch(i) { case 0: localt->tm_sec = RTCSEC; break; + case 1: localt->tm_min = RTCMIN; break; + case 2: localt->tm_hour = RTCHOUR; break; + case 3: localt->tm_mday = RTCDAY; break; + case 4: localt->tm_wday = RTCDOW; break; + case 5: localt->tm_mon = RTCMON - 1; break; + case 6: tmpyear = RTCYEARL; tmpyear |= (RTCYEARH << 0x08); localt->tm_year = tmpyear - 1900; break; + default: success = 1; break; @@ -131,28 +142,34 @@ void rtc_get_localtime(struct tm* localt) { } /*---------------------------------------------------------------------------*/ -void rtc_set_alarm(struct tm* localt, rtc_alarm_mask_t mask) { - if (mask & RTC_ALARM_MIN) { +void rtc_set_alarm(struct tm *localt, rtc_alarm_mask_t mask) +{ + if(mask & RTC_ALARM_MIN) { RTCAMIN = localt->tm_min; RTCAMIN |= BIT7; } - if (mask & RTC_ALARM_HOUR) { + + if(mask & RTC_ALARM_HOUR) { RTCAHOUR = localt->tm_hour; RTCAHOUR |= BIT7; } - if (mask & RTC_ALARM_DOW) { + + if(mask & RTC_ALARM_DOW) { RTCADOW = localt->tm_wday; RTCADOW |= BIT7; } - if (mask & RTC_ALARM_DOM) { + + if(mask & RTC_ALARM_DOM) { RTCADAY = localt->tm_mday; RTCADAY |= BIT7; } + RTCCTL0 |= RTCAIE; } /*---------------------------------------------------------------------------*/ -void rtc_remove_alarm(void) { +void rtc_remove_alarm(void) +{ /* reset all AE bits */ RTCAHOUR &= ~BIT7; RTCAMIN &= ~BIT7; @@ -163,16 +180,18 @@ void rtc_remove_alarm(void) { RTCCTL0 &= ~RTCAIE; } /*---------------------------------------------------------------------------*/ -interrupt(RTC_VECTOR) __attribute__ ((naked)) rtc_isr(void) { +interrupt(RTC_VECTOR) __attribute__((naked)) rtc_isr(void) +{ __enter_isr(); + /* RTC is save to write for up to one second now */ - if (RTCIV == RTC_RTCRDYIFG) { + if(RTCIV == RTC_RTCRDYIFG) { /* disable interrupt */ //RTCCTL0 &= ~RTCRDYIE; - if (set_time) { + if(set_time) { set_time = 0; - /* set previous set time and reset it */ + /* set previous set time and reset it */ RTCSEC = time_to_set.tm_sec; RTCMIN = time_to_set.tm_min; RTCHOUR = time_to_set.tm_hour; @@ -182,14 +201,16 @@ interrupt(RTC_VECTOR) __attribute__ ((naked)) rtc_isr(void) { RTCYEARL = (time_to_set.tm_year + 1900) & 0xFF; RTCYEARH = (time_to_set.tm_year + 1900) >> 0x08; } - if (rtc_second_pid) { + + if(rtc_second_pid) { msg_t m; m.type = RTC_SECOND; msg_send_int(&m, rtc_second_pid); } } /* RTC alarm */ - else if (RTCIV == RTC_RTCAIFG) { + else if(RTCIV == RTC_RTCAIFG) { } + __exit_isr(); } diff --git a/cpu/cc430/hwtimer_cc430.c b/cpu/cc430/hwtimer_cc430.c index 2469b4e20..3cfc758a5 100644 --- a/cpu/cc430/hwtimer_cc430.c +++ b/cpu/cc430/hwtimer_cc430.c @@ -14,44 +14,46 @@ extern void TA0_unset(short timer); void timerA_init(void) { - ticks = 0; // Set tick counter value to 0 - TA0CTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK - TA0CTL &= ~TAIE; // Clear the IFG - + ticks = 0; // Set tick counter value to 0 + TA0CTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK + TA0CTL &= ~TAIE; // Clear the IFG + volatile unsigned int *ccr = &TA0CCR0; volatile unsigned int *ctl = &TA0CCTL0; - for (int i = 0; i < ARCH_MAXTIMERS; i++) { - *(ccr+i) = 0; - *(ctl+i) &= ~(CCIFG); - *(ctl+i) &= ~(CCIE); + for(int i = 0; i < ARCH_MAXTIMERS; i++) { + *(ccr + i) = 0; + *(ctl + i) &= ~(CCIFG); + *(ctl + i) &= ~(CCIE); } TA0CTL |= MC_2; } -interrupt(TIMER0_A0_VECTOR) __attribute__ ((naked)) timer0_a0_isr(void) { +interrupt(TIMER0_A0_VECTOR) __attribute__((naked)) timer0_a0_isr(void) +{ __enter_isr(); - - TA0_unset(0); + + TA0_unset(0); int_handler(0); __exit_isr(); } -interrupt(TIMER0_A1_VECTOR) __attribute__ ((naked)) timer0_a1_5_isr(void) { +interrupt(TIMER0_A1_VECTOR) __attribute__((naked)) timer0_a1_5_isr(void) +{ __enter_isr(); - + short taiv = TA0IV; short timer; - if (taiv & TAIFG) { + if(taiv & TAIFG) { DEBUG("Overflow\n"); } else { - timer = (taiv/2); + timer = (taiv / 2); TA0_unset(timer); int_handler(timer); - } - + } + __exit_isr(); } diff --git a/cpu/cc430/include/cc430-adc.h b/cpu/cc430/include/cc430-adc.h index 8ac19a938..c5f49feb1 100644 --- a/cpu/cc430/include/cc430-adc.h +++ b/cpu/cc430/include/cc430-adc.h @@ -1,34 +1,34 @@ /* ************************************************************************************************* * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions * are met: - * - * Redistributions of source code must retain the above copyright + * + * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the * distribution. - * + * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * ************************************************************************************************/ diff --git a/cpu/cc430/include/cc430-rtc.h b/cpu/cc430/include/cc430-rtc.h index 2df63c0ec..4bfab5953 100644 --- a/cpu/cc430/include/cc430-rtc.h +++ b/cpu/cc430/include/cc430-rtc.h @@ -33,10 +33,10 @@ License. See the file LICENSE in the top level directory for more details. * @see ::rtc_set_alarm */ typedef enum { - RTC_ALARM_DISABLED = 0x00, ///< Alarm disables - RTC_ALARM_MIN = 0x01, ///< Alarm mask for Minutes - RTC_ALARM_HOUR = 0x02, ///< Alarm mask for Hours - RTC_ALARM_DOW = 0x04, ///< Alarm mask for Day of Week + RTC_ALARM_DISABLED = 0x00, ///< Alarm disables + RTC_ALARM_MIN = 0x01, ///< Alarm mask for Minutes + RTC_ALARM_HOUR = 0x02, ///< Alarm mask for Hours + RTC_ALARM_DOW = 0x04, ///< Alarm mask for Day of Week RTC_ALARM_DOM = 0x08 ///< Alarm mask for Day of Month } rtc_alarm_mask_t; @@ -50,7 +50,7 @@ typedef enum { * * @see ::rtc_alarm_mask */ -void rtc_set_alarm(struct tm* localti, rtc_alarm_mask_t mask); +void rtc_set_alarm(struct tm *localti, rtc_alarm_mask_t mask); /** * @brief Resets any set alarm diff --git a/cpu/lpc214x/cpu.c b/cpu/lpc214x/cpu.c index 322d289b0..df0d5e4a6 100644 --- a/cpu/lpc214x/cpu.c +++ b/cpu/lpc214x/cpu.c @@ -2,7 +2,8 @@ #include "bits.h" #include "VIC.h" -void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale) { +void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale) +{ *prescale = source / PCLK_DIV / target; } @@ -17,25 +18,24 @@ void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale) { ******************************************************************************/ #define VIC_BASE_ADDR 0xFFFFF000 -bool cpu_install_irq( int IntNumber, void *HandlerAddr, int Priority ) +bool cpu_install_irq(int IntNumber, void *HandlerAddr, int Priority) { int *vect_addr; int *vect_cntl; VICIntEnClear = 1 << IntNumber; /* Disable Interrupt */ - if ( IntNumber >= VIC_SIZE ) - { - return ( false ); + + if(IntNumber >= VIC_SIZE) { + return (false); } - else - { - /* find first un-assigned VIC address for the handler */ - vect_addr = (int *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + Priority*4); - vect_cntl = (int *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + Priority*4); + else { + /* find first un-assigned VIC address for the handler */ + vect_addr = (int *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + Priority * 4); + vect_cntl = (int *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + Priority * 4); - *vect_addr = (int)HandlerAddr; /* set interrupt vector */ - *vect_cntl = IntNumber + BIT5; - VICIntEnable = 1 << IntNumber; /* Enable Interrupt */ - return( true ); + *vect_addr = (int)HandlerAddr; /* set interrupt vector */ + *vect_cntl = IntNumber + BIT5; + VICIntEnable = 1 << IntNumber; /* Enable Interrupt */ + return(true); } } diff --git a/cpu/lpc214x/include/lpc214x.h b/cpu/lpc214x/include/lpc214x.h index fd57edf42..ce9e8c1f0 100644 --- a/cpu/lpc214x/include/lpc214x.h +++ b/cpu/lpc214x/include/lpc214x.h @@ -424,5 +424,5 @@ details. //inline void TurOffPeripheral(int p); //inline void TurOnPeripheral(int p); -#endif +#endif diff --git a/cpu/lpc2387/cpu.c b/cpu/lpc2387/cpu.c index 349f50725..cf14cfc91 100644 --- a/cpu/lpc2387/cpu.c +++ b/cpu/lpc2387/cpu.c @@ -19,38 +19,44 @@ License. See the file LICENSE in the top level directory for more details. #include #include "VIC.h" -void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t* pclksel, uint32_t* prescale) +void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t *pclksel, uint32_t *prescale) { - uint32_t pclkdiv; - *prescale = source / target; - - if( (*prescale % 16) == 0 ) { - *pclksel = 3; - pclkdiv = 8; - } else if( (*prescale % 8) == 0 ) { - *pclksel = 0; - pclkdiv = 4; - } else if( (*prescale % 4) == 0 ) { - *pclksel = 2; - pclkdiv = 2; - } else { - *pclksel = 1; - pclkdiv = 1; - } - *prescale /= pclkdiv; - - if( *prescale % 2 ) - (*prescale)++; + uint32_t pclkdiv; + *prescale = source / target; + + if((*prescale % 16) == 0) { + *pclksel = 3; + pclkdiv = 8; + } + else if((*prescale % 8) == 0) { + *pclksel = 0; + pclkdiv = 4; + } + else if((*prescale % 4) == 0) { + *pclksel = 2; + pclkdiv = 2; + } + else { + *pclksel = 1; + pclkdiv = 1; + } + + *prescale /= pclkdiv; + + if(*prescale % 2) { + (*prescale)++; + } } -void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale) { +void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale) +{ uint32_t pclksel; lpc2387_pclk_scale(source, target, &pclksel, prescale); - PCLKSEL0 = (PCLKSEL0 & ~(BIT2|BIT3)) | (pclksel << 2); // timer 0 - PCLKSEL0 = (PCLKSEL0 & ~(BIT4|BIT5)) | (pclksel << 4); // timer 1 - PCLKSEL1 = (PCLKSEL1 & ~(BIT12|BIT13)) | (pclksel << 12); // timer 2 + PCLKSEL0 = (PCLKSEL0 & ~(BIT2 | BIT3)) | (pclksel << 2); // timer 0 + PCLKSEL0 = (PCLKSEL0 & ~(BIT4 | BIT5)) | (pclksel << 4); // timer 1 + PCLKSEL1 = (PCLKSEL1 & ~(BIT12 | BIT13)) | (pclksel << 12); // timer 2 } /****************************************************************************** @@ -64,25 +70,24 @@ void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t* prescale) { ******************************************************************************/ #define VIC_BASE_ADDR 0xFFFFF000 -bool install_irq( int IntNumber, void *HandlerAddr, int Priority ) +bool install_irq(int IntNumber, void *HandlerAddr, int Priority) { int *vect_addr; int *vect_cntl; VICIntEnClr = 1 << IntNumber; /* Disable Interrupt */ - if ( IntNumber >= VIC_SIZE ) - { - return ( false ); + + if(IntNumber >= VIC_SIZE) { + return (false); } - else - { - /* find first un-assigned VIC address for the handler */ - vect_addr = (int *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + IntNumber*4); - vect_cntl = (int *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + IntNumber*4); - *vect_addr = (int)HandlerAddr; /* set interrupt vector */ - *vect_cntl = Priority; - VICIntEnable = 1 << IntNumber; /* Enable Interrupt */ - return( true ); + else { + /* find first un-assigned VIC address for the handler */ + vect_addr = (int *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + IntNumber * 4); + vect_cntl = (int *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + IntNumber * 4); + *vect_addr = (int)HandlerAddr; /* set interrupt vector */ + *vect_cntl = Priority; + VICIntEnable = 1 << IntNumber; /* Enable Interrupt */ + return(true); } } diff --git a/cpu/lpc2387/gpioint/lpc2387-gpioint.c b/cpu/lpc2387/gpioint/lpc2387-gpioint.c index b132ca5da..c4f2467ae 100644 --- a/cpu/lpc2387/gpioint/lpc2387-gpioint.c +++ b/cpu/lpc2387/gpioint/lpc2387-gpioint.c @@ -35,95 +35,101 @@ License. See the file LICENSE in the top level directory for more details. #include struct irq_callback_t { - fp_irqcb callback; + fp_irqcb callback; }; static struct irq_callback_t gpioint0[32]; static struct irq_callback_t gpioint2[32]; -void gpioint_init(void) { +void gpioint_init(void) +{ extern void GPIO_IRQHandler(void); - /* GPIO Init */ - INTWAKE |= GPIO0WAKE | GPIO2WAKE; // allow GPIO to wake up from power down - install_irq(GPIO_INT, &GPIO_IRQHandler, IRQP_GPIO); // install irq handler + /* GPIO Init */ + INTWAKE |= GPIO0WAKE | GPIO2WAKE; /* allow GPIO to wake up from power down */ + install_irq(GPIO_INT, &GPIO_IRQHandler, IRQP_GPIO); /* install irq handler */ } /*---------------------------------------------------------------------------*/ bool gpioint_set(int port, uint32_t bitmask, int flags, fp_irqcb callback) { - struct irq_callback_t* cbdata; - unsigned long bit; - volatile unsigned long* en_f; - volatile unsigned long* en_r; - volatile unsigned long* en_clr; - - /* lookup registers */ - bit = number_of_highest_bit(bitmask); // get irq mapping table index - - switch( port ) { - case 0: // PORT0 - cbdata = gpioint0; - en_f = &IO0_INT_EN_F; - en_r = &IO0_INT_EN_R; - en_clr = &IO0_INT_CLR; - break; - - case 2: // PORT2 - cbdata = gpioint2; - en_f = &IO2_INT_EN_F; - en_r = &IO2_INT_EN_R; - en_clr = &IO2_INT_CLR; - break; - - default: // unsupported - return false; // fail - } - - /* reconfigure irq */ - unsigned long cpsr = disableIRQ(); - *en_clr |= bitmask; // clear interrupt - - if( (flags & GPIOINT_FALLING_EDGE) != 0 ) { - *en_f |= bitmask; // enable falling edge - } else { - *en_f &= ~bitmask; // disable falling edge - } - - if( (flags & GPIOINT_RISING_EDGE) != 0 ) { - *en_r |= bitmask; // enable rising edge - } else { - *en_r &= ~bitmask; // disable rising edge - } - - if( ((flags & (GPIOINT_FALLING_EDGE | GPIOINT_RISING_EDGE)) != 0) ) { - cbdata[bit].callback = callback; - - } else { - cbdata[bit].callback = NULL; // remove from interrupt mapping table - } - restoreIRQ(cpsr); - - return true; // success + struct irq_callback_t *cbdata; + unsigned long bit; + volatile unsigned long *en_f; + volatile unsigned long *en_r; + volatile unsigned long *en_clr; + + /* lookup registers */ + bit = number_of_highest_bit(bitmask); /* get irq mapping table index */ + + switch(port) { + case 0: /* PORT0 */ + cbdata = gpioint0; + en_f = &IO0_INT_EN_F; + en_r = &IO0_INT_EN_R; + en_clr = &IO0_INT_CLR; + break; + + case 2: /* PORT2 */ + cbdata = gpioint2; + en_f = &IO2_INT_EN_F; + en_r = &IO2_INT_EN_R; + en_clr = &IO2_INT_CLR; + break; + + default: /* unsupported */ + return false; /* fail */ + } + + /* reconfigure irq */ + unsigned long cpsr = disableIRQ(); + *en_clr |= bitmask; /* clear interrupt */ + + if((flags & GPIOINT_FALLING_EDGE) != 0) { + *en_f |= bitmask; /* enable falling edge */ + } + else { + *en_f &= ~bitmask; /* disable falling edge */ + } + + if((flags & GPIOINT_RISING_EDGE) != 0) { + *en_r |= bitmask; /* enable rising edge */ + } + else { + *en_r &= ~bitmask; /* disable rising edge */ + } + + if(((flags & (GPIOINT_FALLING_EDGE | GPIOINT_RISING_EDGE)) != 0)) { + cbdata[bit].callback = callback; + + } + else { + cbdata[bit].callback = NULL; /* remove from interrupt mapping table */ + } + + restoreIRQ(cpsr); + + return true; /* success */ } /*---------------------------------------------------------------------------*/ -static void __attribute__ ((__no_instrument_function__)) test_irq(int port, unsigned long f_mask, unsigned long r_mask, struct irq_callback_t* pcb) +static void __attribute__((__no_instrument_function__)) test_irq(int port, unsigned long f_mask, unsigned long r_mask, struct irq_callback_t *pcb) { - /* Test each bit of rising and falling masks, if set trigger interrupt - * on corresponding device */ - do { - if( (pcb->callback != NULL) ) { - if ((r_mask & 1) | (f_mask & 1)) { - pcb->callback(); // pass to handler - } - } - - f_mask >>= 1UL; - r_mask >>= 1UL; - pcb++; - } while( (f_mask != 0) || (r_mask != 0) ); + /* Test each bit of rising and falling masks, if set trigger interrupt + * on corresponding device */ + do { + if((pcb->callback != NULL)) { + if((r_mask & 1) | (f_mask & 1)) { + pcb->callback(); /* pass to handler */ + } + } + + f_mask >>= 1UL; + r_mask >>= 1UL; + pcb++; + } + while((f_mask != 0) || (r_mask != 0)); } /*---------------------------------------------------------------------------*/ void GPIO_IRQHandler(void) __attribute__((interrupt("IRQ"))); @@ -134,27 +140,29 @@ void GPIO_IRQHandler(void) __attribute__((interrupt("IRQ"))); * Invoked whenever an activated gpio interrupt is triggered by a rising * or falling edge. */ -void __attribute__ ((__no_instrument_function__)) GPIO_IRQHandler(void) { - if( IO_INT_STAT & BIT0 ) { // interrupt(s) on PORT0 pending - unsigned long int_stat_f = IO0_INT_STAT_F; // save content - unsigned long int_stat_r = IO0_INT_STAT_R; // save content +void __attribute__((__no_instrument_function__)) GPIO_IRQHandler(void) +{ + if(IO_INT_STAT & BIT0) { /* interrupt(s) on PORT0 pending */ + unsigned long int_stat_f = IO0_INT_STAT_F; /* save content */ + unsigned long int_stat_r = IO0_INT_STAT_R; /* save content */ + + IO0_INT_CLR = int_stat_f; /* clear flags of fallen pins */ + IO0_INT_CLR = int_stat_r; /* clear flags of risen pins */ - IO0_INT_CLR = int_stat_f; // clear flags of fallen pins - IO0_INT_CLR = int_stat_r; // clear flags of risen pins + test_irq(0, int_stat_f, int_stat_r, gpioint0); + } - test_irq(0, int_stat_f, int_stat_r, gpioint0); - } + if(IO_INT_STAT & BIT2) { /* interrupt(s) on PORT2 pending */ + unsigned long int_stat_f = IO2_INT_STAT_F; /* save content */ + unsigned long int_stat_r = IO2_INT_STAT_R; /* save content */ - if( IO_INT_STAT & BIT2 ) { // interrupt(s) on PORT2 pending - unsigned long int_stat_f = IO2_INT_STAT_F; // save content - unsigned long int_stat_r = IO2_INT_STAT_R; // save content + IO2_INT_CLR = int_stat_f; /* clear flags of fallen pins */ + IO2_INT_CLR = int_stat_r; /* clear flags of risen pins */ - IO2_INT_CLR = int_stat_f; // clear flags of fallen pins - IO2_INT_CLR = int_stat_r; // clear flags of risen pins + test_irq(2, int_stat_f, int_stat_r, gpioint2); + } - test_irq(2, int_stat_f, int_stat_r, gpioint2); - } - VICVectAddr = 0; // Acknowledge Interrupt + VICVectAddr = 0; /* Acknowledge Interrupt */ } /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/cpu/lpc2387/include/cpu.h b/cpu/lpc2387/include/cpu.h index afe56b0c5..8f770db2d 100644 --- a/cpu/lpc2387/include/cpu.h +++ b/cpu/lpc2387/include/cpu.h @@ -25,8 +25,8 @@ License. See the file LICENSE in the top level directory for more details. extern uintptr_t __stack_start; ///< end of user stack memory space -void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t* pclksel, uint32_t* prescale); -bool install_irq( int IntNumber, void *HandlerAddr, int Priority ); +void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t *pclksel, uint32_t *prescale); +bool install_irq(int IntNumber, void *HandlerAddr, int Priority); /** @} */ #endif /* __CPU_H */ diff --git a/cpu/lpc2387/include/lpc2387-rtc.h b/cpu/lpc2387/include/lpc2387-rtc.h index cd0d7a3eb..caa3f2f5f 100644 --- a/cpu/lpc2387/include/lpc2387-rtc.h +++ b/cpu/lpc2387/include/lpc2387-rtc.h @@ -52,15 +52,15 @@ License. See the file LICENSE in the top level directory for more details. * @see ::rtc_set_alarm, ::rtc_get_alarm */ enum rtc_alarm_mask { - RTC_AMR_DISABLED = 0, ///< Alarm disables - RTC_AMR_SEC = AMRSEC, ///< Alarm mask for Seconds - RTC_AMR_MIN = AMRMIN, ///< Alarm mask for Minutes - RTC_AMR_HOUR= AMRHOUR, ///< Alarm mask for Hours - RTC_AMR_DOM = AMRDOM, ///< Alarm mask for Day of Month - RTC_AMR_DOW = AMRDOW, ///< Alarm mask for Day of Week - RTC_AMR_DOY = AMRDOY, ///< Alarm mask for Day of Year - RTC_AMR_MON = AMRMON, ///< Alarm mask for Month - RTC_AMR_YEAR= AMRYEAR, ///< Alarm mask for Year + RTC_AMR_DISABLED = 0, ///< Alarm disables + RTC_AMR_SEC = AMRSEC, ///< Alarm mask for Seconds + RTC_AMR_MIN = AMRMIN, ///< Alarm mask for Minutes + RTC_AMR_HOUR = AMRHOUR, ///< Alarm mask for Hours + RTC_AMR_DOM = AMRDOM, ///< Alarm mask for Day of Month + RTC_AMR_DOW = AMRDOW, ///< Alarm mask for Day of Week + RTC_AMR_DOY = AMRDOY, ///< Alarm mask for Day of Year + RTC_AMR_MON = AMRMON, ///< Alarm mask for Month + RTC_AMR_YEAR = AMRYEAR, ///< Alarm mask for Year }; void rtc_reset(void); @@ -76,7 +76,7 @@ time_t rtc_get_compile_time(void) __attribute__((noinline)); * @param[out] time optional return value * @return clock time in seconds */ -time_t rtc_time(struct timeval* time); +time_t rtc_time(struct timeval *time); /** * @brief Sets the current clock time @@ -95,7 +95,7 @@ void rtc_set(time_t time); * * @see ::rtc_alarm_mask */ -void rtc_set_alarm(struct tm* localt, enum rtc_alarm_mask mask); +void rtc_set_alarm(struct tm *localt, enum rtc_alarm_mask mask); /** * @brief Gets the current alarm setting @@ -106,7 +106,7 @@ void rtc_set_alarm(struct tm* localt, enum rtc_alarm_mask mask); * @see rtc_set_alarm * @see ::rtc_alarm_mask */ -enum rtc_alarm_mask _rtc_get_alarm(struct tm* localt); +enum rtc_alarm_mask _rtc_get_alarm(struct tm *localt); /** @} */ #endif /* end __RTC_H */ diff --git a/cpu/lpc2387/include/lpc23xx.h b/cpu/lpc2387/include/lpc23xx.h index 900fbb7fa..269393bdd 100644 --- a/cpu/lpc2387/include/lpc23xx.h +++ b/cpu/lpc2387/include/lpc23xx.h @@ -1,6 +1,6 @@ /****************************************************************************** * LPC23xx.h: Header file for NXP LPC23xx/24xx Family Microprocessors - * The header file is the super set of all hardware definition of the + * The header file is the super set of all hardware definition of the * peripherals for the LPC23xx/24xx family microprocessor. * * Copyright(C) 2006, NXP Semiconductor @@ -136,13 +136,13 @@ these registers are known as "VICVectPriority(x)". */ #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) /* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) @@ -151,224 +151,224 @@ these registers are known as "VICVectPriority(x)". */ #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) #define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) /* Fast I/O setup */ #define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) - -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) - -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) - -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) - -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) - -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) - -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) - -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) - -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) - -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) - -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) - -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) - -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) - -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) - -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) - -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) - -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) - -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) - -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) - -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) - -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ #define SCB_BASE_ADDR 0xE01FC000 @@ -394,7 +394,7 @@ Reset, and Code Security/Debugging */ #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - + /* External Interrupts */ #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) @@ -412,9 +412,9 @@ Reset, and Code Security/Debugging */ #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) /* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ #define STATIC_MEM0_BASE 0x80000000 #define STATIC_MEM1_BASE 0x81000000 @@ -819,72 +819,72 @@ are for LPC24xx only. */ /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ #define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) #define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) #define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) #define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) #define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) #define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) #define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) #define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) #define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) #define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) #define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) #define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) #define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) #define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) #define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) #define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) #define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) #define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) #define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) #define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) @@ -1046,7 +1046,7 @@ are for LPC24xx only. */ #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) @@ -1058,14 +1058,14 @@ are for LPC24xx only. */ #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ +with the spec. update in USB Device Section. */ #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) diff --git a/cpu/lpc2387/lpc2387-adc.c b/cpu/lpc2387/lpc2387-adc.c index 383bb9c55..10a929dad 100644 --- a/cpu/lpc2387/lpc2387-adc.c +++ b/cpu/lpc2387/lpc2387-adc.c @@ -37,105 +37,109 @@ License. See the file LICENSE in the top level directory for more details. void adc_init(void) { - // enable clock /Power for ADC - PCONP |= BIT12; - - // peripheral Clock Selection for ADC - PCLKSEL0 |= 0x03000000; // pclock = cclock/8 - - // set A/D control register AD0CR - AD0CR = ( 0x01 << 0 ) | /* SEL=1, select channel 0~7 on ADC0 */ - ( 0xff << 8 ) | /* CLKDIV = 1, ADC_CLK = PCLK/10 = 0.45 MHz */ - ( 0 << 16 ) | /* BURST = 0, no BURST, software controlled */ - ( 0 << 17 ) | /* CLKS = 0, 11 clocks/10 bits */ - ( 1 << 21 ) | /* PDN = 1, normal operation */ - ( 0 << 22 ) | /* TEST1:0 = 00 */ - ( 0 << 24 ) | /* START = 0 A/D conversion stops */ - ( 0 << 27 ); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ + // enable clock /Power for ADC + PCONP |= BIT12; + + // peripheral Clock Selection for ADC + PCLKSEL0 |= 0x03000000; // pclock = cclock/8 + + // set A/D control register AD0CR + AD0CR = (0x01 << 0) | /* SEL=1, select channel 0~7 on ADC0 */ + (0xff << 8) | /* CLKDIV = 1, ADC_CLK = PCLK/10 = 0.45 MHz */ + (0 << 16) | /* BURST = 0, no BURST, software controlled */ + (0 << 17) | /* CLKS = 0, 11 clocks/10 bits */ + (1 << 21) | /* PDN = 1, normal operation */ + (0 << 22) | /* TEST1:0 = 00 */ + (0 << 24) | /* START = 0 A/D conversion stops */ + (0 << 27); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ } /*---------------------------------------------------------------------------*/ void adc_init_1(void) { - // enable clock /Power for ADC - PCONP |= BIT12; - - //PIN0.24 function select AD0.1 - PINSEL1 |= BIT16; - - // peripheral Clock Selection for ADC - PCLKSEL0 |= 0x03000000; // pclock = cclock/8 - - // set A/D control register AD0CR - AD0CR = ( 0x01 << 0 ) | /* SEL=1, select channel 0~7 on ADC0 */ - ( 0x00 << 8 ) | /* CLKDIV = 1, ADC_CLK = PCLK/1 = 4.5 MHz */ - ( 0 << 16 ) | /* BURST = 0, no BURST, software controlled */ - ( 0 << 17 ) | /* CLKS = 0, 11 clocks/10 bits */ - ( 1 << 21 ) | /* PDN = 1, normal operation */ - ( 0 << 22 ) | /* TEST1:0 = 00 */ - ( 0 << 24 ) | /* START = 0 A/D conversion stops */ - ( 0 << 27 ); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ + // enable clock /Power for ADC + PCONP |= BIT12; + + //PIN0.24 function select AD0.1 + PINSEL1 |= BIT16; + + // peripheral Clock Selection for ADC + PCLKSEL0 |= 0x03000000; // pclock = cclock/8 + + // set A/D control register AD0CR + AD0CR = (0x01 << 0) | /* SEL=1, select channel 0~7 on ADC0 */ + (0x00 << 8) | /* CLKDIV = 1, ADC_CLK = PCLK/1 = 4.5 MHz */ + (0 << 16) | /* BURST = 0, no BURST, software controlled */ + (0 << 17) | /* CLKS = 0, 11 clocks/10 bits */ + (1 << 21) | /* PDN = 1, normal operation */ + (0 << 22) | /* TEST1:0 = 00 */ + (0 << 24) | /* START = 0 A/D conversion stops */ + (0 << 27); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ } /*---------------------------------------------------------------------------*/ void adc_init_2(void) { - // enable clock /Power for ADC - PCONP |= BIT12; - - // PIN0.23 function select to AD0.0 - PINSEL1 |= BIT14; - - // peripheral Clock Selection for ADC - PCLKSEL0 |= 0x03000000; // pclock = cclock/8 - - // set A/D control register AD0CR - AD0CR = ( 0x01 << 0 ) | /* SEL=1, select channel 0 on ADC0 */ - ( 0x00 << 8 ) | /* CLKDIV = 1, ADC_CLK = PCLK/1 = 4.5 MHz */ - ( 0 << 16 ) | /* BURST = 0, no BURST */ - ( 0 << 17 ) | /* CLKS = 0, 11 clocks/10 bits */ - ( 1 << 21 ) | /* PDN = 1, normal operation */ - ( 0 << 22 ) | /* TEST1:0 = 00 */ - ( 0 << 24 ) | /* START = 0 A/D conversion stops */ - ( 0 << 27 ); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ + // enable clock /Power for ADC + PCONP |= BIT12; + + // PIN0.23 function select to AD0.0 + PINSEL1 |= BIT14; + + // peripheral Clock Selection for ADC + PCLKSEL0 |= 0x03000000; // pclock = cclock/8 + + // set A/D control register AD0CR + AD0CR = (0x01 << 0) | /* SEL=1, select channel 0 on ADC0 */ + (0x00 << 8) | /* CLKDIV = 1, ADC_CLK = PCLK/1 = 4.5 MHz */ + (0 << 16) | /* BURST = 0, no BURST */ + (0 << 17) | /* CLKS = 0, 11 clocks/10 bits */ + (1 << 21) | /* PDN = 1, normal operation */ + (0 << 22) | /* TEST1:0 = 00 */ + (0 << 24) | /* START = 0 A/D conversion stops */ + (0 << 27); /* EDGE = 0 (CAP/MAT signal falling,trigger A/D conversion) */ } /*---------------------------------------------------------------------------*/ uint16_t adc_read(uint8_t channel) { #ifdef ENABLE_DEBUG - uint32_t t1, t2; + uint32_t t1, t2; #endif - uint32_t regVal, adc_data; - /* channel number is 0 through 7 */ - if (channel >= ADC_NUM) - { - channel = 0; /* reset channel number to 0 */ - } - - /* switch channel, start A/D convert */ - AD0CR &= 0xFFFFFF00; + uint32_t regVal, adc_data; + + /* channel number is 0 through 7 */ + if(channel >= ADC_NUM) { + channel = 0; /* reset channel number to 0 */ + } + + /* switch channel, start A/D convert */ + AD0CR &= 0xFFFFFF00; #ifdef ENABLE_DEBUG - t1 = hwtimer_now(); + t1 = hwtimer_now(); #endif - AD0CR |= (1 << 24) | (1 << channel); + AD0CR |= (1 << 24) | (1 << channel); #ifdef ENABLE_DEBUG - t2 = hwtimer_now(); + t2 = hwtimer_now(); #endif - while (1) - { - /* read result of A/D conversion */ - regVal = *(volatile unsigned long *)(AD0_BASE_ADDR + ADC_OFFSET + ADC_INDEX * channel); - - /* wait until end of A/D convert */ - if (regVal & ADC_DONE) break; - } - AD0CR &= 0xF8FFFFFF; /* stop ADC now */ - if (regVal & ADC_OVERRUN) /* save data when it's not overrun, otherwise, return zero */ - { - return 0; - } - adc_data = (regVal >> 6) & 0x3FF; - DEBUG("%s, %d: %lu\n", __FILE__, __LINE__, t1); - DEBUG("%s, %d: %lu\n", __FILE__, __LINE__, t2); - return (uint16_t) adc_data; /* return A/D conversion value */ + + while(1) { + /* read result of A/D conversion */ + regVal = *(volatile unsigned long *)(AD0_BASE_ADDR + ADC_OFFSET + ADC_INDEX * channel); + + /* wait until end of A/D convert */ + if(regVal & ADC_DONE) { + break; + } + } + + AD0CR &= 0xF8FFFFFF; /* stop ADC now */ + + if(regVal & ADC_OVERRUN) { /* save data when it's not overrun, otherwise, return zero */ + return 0; + } + + adc_data = (regVal >> 6) & 0x3FF; + DEBUG("%s, %d: %lu\n", __FILE__, __LINE__, t1); + DEBUG("%s, %d: %lu\n", __FILE__, __LINE__, t2); + return (uint16_t) adc_data; /* return A/D conversion value */ } diff --git a/cpu/lpc2387/lpc2387-lpm.c b/cpu/lpc2387/lpc2387-lpm.c index 14d7661c9..6cef44a72 100644 --- a/cpu/lpc2387/lpc2387-lpm.c +++ b/cpu/lpc2387/lpc2387-lpm.c @@ -44,69 +44,82 @@ extern void init_clks2(void); #define ENABLE_DEBUG 0 #include -void lpm_init(void) { - lpm = LPM_ON; +void lpm_init(void) +{ + lpm = LPM_ON; } #define LPM_DEBUG 1 -void lpm_begin_awake(void) { - if (lpm >= LPM_SLEEP ) { // wake up from deep sleep - init_clks1(); - } +void lpm_begin_awake(void) +{ + if(lpm >= LPM_SLEEP) { // wake up from deep sleep + init_clks1(); + } } -void lpm_end_awake(void) { - if( lpm >= LPM_SLEEP ) { // wake up from deep sleep - init_clks2(); - } - lpm = LPM_ON; +void lpm_end_awake(void) +{ + if(lpm >= LPM_SLEEP) { // wake up from deep sleep + init_clks2(); + } + + lpm = LPM_ON; } -void lpm_awake(void) { +void lpm_awake(void) +{ #if LPM_DEBUG - unsigned long usec = RTC_CTC; + unsigned long usec = RTC_CTC; #endif - if( lpm >= LPM_SLEEP ) { // wake up from deep sleep - //benchmark - init_clks1(); - init_clks2(); - // Debug tests + + if(lpm >= LPM_SLEEP) { // wake up from deep sleep + /* benchmark */ + init_clks1(); + init_clks2(); + /* Debug tests */ #if LPM_DEBUG - usec = RTC_CTC-usec; - DEBUG("Wakeup in %lu usecs\n",usec * 31); + usec = RTC_CTC - usec; + DEBUG("Wakeup in %lu usecs\n", usec * 31); #endif - } - lpm = LPM_ON; -} - -enum lpm_mode lpm_set(enum lpm_mode target) { - unsigned target_flags; - enum lpm_mode last_lpm = lpm; + } - /* calculate target mcu power mode */ - if( target == LPM_IDLE ) - target_flags = PM_IDLE; - else if( target == LPM_SLEEP ) - target_flags = PM_SLEEP; - else if( target == LPM_POWERDOWN ) - target_flags = PM_POWERDOWN; - else - target_flags = 0; - - lpm = target; + lpm = LPM_ON; +} - #if iENABLE_DEBUG - DEBUG("# LPM power down %u -> %u", lpm, target); - #endif +enum lpm_mode lpm_set(enum lpm_mode target) +{ + unsigned target_flags; + enum lpm_mode last_lpm = lpm; + + /* calculate target mcu power mode */ + if(target == LPM_IDLE) { + target_flags = PM_IDLE; + } + else if(target == LPM_SLEEP) { + target_flags = PM_SLEEP; + } + else if(target == LPM_POWERDOWN) { + target_flags = PM_POWERDOWN; + } + else { + target_flags = 0; + } + + lpm = target; + +#if iENABLE_DEBUG + DEBUG("# LPM power down %u -> %u", lpm, target); +#endif - PCON |= target_flags; // set target power mode - return last_lpm; + PCON |= target_flags; // set target power mode + return last_lpm; } /*---------------------------------------------------------------------------*/ enum lpm_mode -lpm_get(void) { - return lpm; +lpm_get(void) +{ + return lpm; } /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/cpu/lpc2387/lpc23xx-iap.c b/cpu/lpc2387/lpc23xx-iap.c index 7b49fe74e..4458bbf11 100644 --- a/cpu/lpc2387/lpc23xx-iap.c +++ b/cpu/lpc2387/lpc23xx-iap.c @@ -2,93 +2,120 @@ #include #include -uint8_t iap_get_sector(uint32_t addr) { - if ((addr >=0x00000000) && (addr <= 0x00000FFF)) { - return 0; +uint8_t iap_get_sector(uint32_t addr) +{ + if((addr >= 0x00000000) && (addr <= 0x00000FFF)) { + return 0; } - if ((addr >=0x00001000) && (addr <= 0x00001FFF)) { - return 1; + + if((addr >= 0x00001000) && (addr <= 0x00001FFF)) { + return 1; } - if ((addr >=0x00002000) && (addr <= 0x00002FFF)) { - return 2; + + if((addr >= 0x00002000) && (addr <= 0x00002FFF)) { + return 2; } - if ((addr >=0x00003000) && (addr <= 0x00003FFF)) { - return 3; + + if((addr >= 0x00003000) && (addr <= 0x00003FFF)) { + return 3; } - if ((addr >=0x00004000) && (addr <= 0x00004FFF)) { - return 4; + + if((addr >= 0x00004000) && (addr <= 0x00004FFF)) { + return 4; } - if ((addr >=0x00005000) && (addr <= 0x00005FFF)) { - return 5; + + if((addr >= 0x00005000) && (addr <= 0x00005FFF)) { + return 5; } - if ((addr >=0x00006000) && (addr <= 0x00006FFF)) { - return 6; + + if((addr >= 0x00006000) && (addr <= 0x00006FFF)) { + return 6; } - if ((addr >=0x00007000) && (addr <= 0x00007FFF)) { - return 7; + + if((addr >= 0x00007000) && (addr <= 0x00007FFF)) { + return 7; } - if ((addr >=0x00008000) && (addr <= 0x0000FFFF)) { - return 8; + if((addr >= 0x00008000) && (addr <= 0x0000FFFF)) { + return 8; } - if ((addr >=0x00010000) && (addr <= 0x00017FFF)) { - return 9; + + if((addr >= 0x00010000) && (addr <= 0x00017FFF)) { + return 9; } - if ((addr >=0x00018000) && (addr <= 0x0001FFFF)) { - return 10; + + if((addr >= 0x00018000) && (addr <= 0x0001FFFF)) { + return 10; } - if ((addr >=0x00020000) && (addr <= 0x00027FFF)) { - return 11; + + if((addr >= 0x00020000) && (addr <= 0x00027FFF)) { + return 11; } - if ((addr >=0x00028000) && (addr <= 0x0002FFFF)) { + + if((addr >= 0x00028000) && (addr <= 0x0002FFFF)) { return 12; } - if ((addr >=0x00030000) && (addr <= 0x00037FFF)) { - return 13; + + if((addr >= 0x00030000) && (addr <= 0x00037FFF)) { + return 13; } - if ((addr >=0x00038000) && (addr <= 0x0003FFFF)) { - return 14; + + if((addr >= 0x00038000) && (addr <= 0x0003FFFF)) { + return 14; } - if ((addr >=0x00040000) && (addr <= 0x00047FFF)) { - return 15; + + if((addr >= 0x00040000) && (addr <= 0x00047FFF)) { + return 15; } - if ((addr >=0x00048000) && (addr <= 0x0004FFFF)) { - return 16; + + if((addr >= 0x00048000) && (addr <= 0x0004FFFF)) { + return 16; } - if ((addr >=0x00050000) && (addr <= 0x00057FFF)) { - return 17; + + if((addr >= 0x00050000) && (addr <= 0x00057FFF)) { + return 17; } - if ((addr >=0x00058000) && (addr <= 0x0005FFFF)) { + + if((addr >= 0x00058000) && (addr <= 0x0005FFFF)) { return 18; } - if ((addr >=0x00060000) && (addr <= 0x00067FFF)) { + + if((addr >= 0x00060000) && (addr <= 0x00067FFF)) { return 19; } - if ((addr >=0x00068000) && (addr <= 0x0006FFFF)) { + + if((addr >= 0x00068000) && (addr <= 0x0006FFFF)) { return 20; } - if ((addr >=0x00070000) && (addr <= 0x00077FFF)) { + + if((addr >= 0x00070000) && (addr <= 0x00077FFF)) { return 21; } - if ((addr >=0x00078000) && (addr <= 0x00078FFF)) { + + if((addr >= 0x00078000) && (addr <= 0x00078FFF)) { return 22; } - if ((addr >=0x00079000) && (addr <= 0x00079FFF)) { + + if((addr >= 0x00079000) && (addr <= 0x00079FFF)) { return 23; } - if ((addr >=0x0007A000) && (addr <= 0x0007AFFF)) { + + if((addr >= 0x0007A000) && (addr <= 0x0007AFFF)) { return 24; } - if ((addr >=0x0007B000) && (addr <= 0x0007BFFF)) { + + if((addr >= 0x0007B000) && (addr <= 0x0007BFFF)) { return 25; } - if ((addr >=0x0007C000) && (addr <= 0x0007CFFF)) { + + if((addr >= 0x0007C000) && (addr <= 0x0007CFFF)) { return 26; } - if ((addr >=0x0007D000) && (addr <= 0x0007DFFF)) { - return 27; + + if((addr >= 0x0007D000) && (addr <= 0x0007DFFF)) { + return 27; } - + /* no valid address within flash */ - return INVALID_ADDRESS; + return INVALID_ADDRESS; } diff --git a/cpu/lpc2387/mci/lpc2387-mci.c b/cpu/lpc2387/mci/lpc2387-mci.c index 255853f78..7c2757eb6 100644 --- a/cpu/lpc2387/mci/lpc2387-mci.c +++ b/cpu/lpc2387/mci/lpc2387-mci.c @@ -84,72 +84,80 @@ static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */ static unsigned short CardRCA; /* Assigned RCA */ static unsigned char CardType, /* Card type flag */ - CardInfo[16+16+4]; /* CSD(16), CID(16), OCR(4) */ + CardInfo[16 + 16 + 4]; /* CSD(16), CID(16), OCR(4) */ static volatile unsigned char XferStat, /* b3:MCI error, b2:Overrun, b1:Write, b0:Read */ - XferWc, /* Write block counter */ - XferWp, XferRp; /* R/W index of block FIFO */ + XferWc, /* Write block counter */ + XferWp, XferRp; /* R/W index of block FIFO */ -static unsigned long DmaBuff[N_BUF][128] __attribute__ ((section(".usbdata"))); /* Block transfer FIFO */ -static unsigned long LinkList [N_BUF][4] __attribute__ ((section(".usbdata"))); /* DMA link list */ +static unsigned long DmaBuff[N_BUF][128] __attribute__((section(".usbdata"))); /* Block transfer FIFO */ +static unsigned long LinkList [N_BUF][4] __attribute__((section(".usbdata"))); /* DMA link list */ -void Isr_MCI (void) __attribute__ ((interrupt("IRQ"))); -void Isr_GPDMA (void) __attribute__ ((interrupt("IRQ"))); +void Isr_MCI(void) __attribute__((interrupt("IRQ"))); +void Isr_GPDMA(void) __attribute__((interrupt("IRQ"))); /*-----------------------------------------------------------------------*/ /* Interrupt service routine for data transfer */ /*-----------------------------------------------------------------------*/ -void Isr_MCI (void) { +void Isr_MCI(void) +{ unsigned long ms; - unsigned char n, xs; - - ms = MCI_STATUS & 0x073A; /* Clear MCI interrupt status */ - MCI_CLEAR = ms; - - xs = XferStat; - if (ms & 0x400) { /* A block transfer completed (DataBlockEnd) */ - if (xs & 1) { /* In card read operation */ - if (ms & 0x100) /* When last block is received (DataEnd), */ - GPDMA_SOFT_BREQ = 0x10; /* Pop off remaining data in the MCIFIFO */ - n = (XferWp + 1) % N_BUF; /* Next write buffer */ - XferWp = n; - if (n == XferRp) xs |= 4; /* Check block overrun */ - } - else { /* In card write operation */ - n = (XferRp + 1) % N_BUF; /* Next read buffer */ - XferRp = n; - if (n == XferWp) xs |= 4; /* Check block underrun */ - } - } + unsigned char n, xs; + + ms = MCI_STATUS & 0x073A; /* Clear MCI interrupt status */ + MCI_CLEAR = ms; + + xs = XferStat; + + if(ms & 0x400) { /* A block transfer completed (DataBlockEnd) */ + if(xs & 1) { /* In card read operation */ + if(ms & 0x100) { /* When last block is received (DataEnd), */ + GPDMA_SOFT_BREQ = 0x10; /* Pop off remaining data in the MCIFIFO */ + } + + n = (XferWp + 1) % N_BUF; /* Next write buffer */ + XferWp = n; + + if(n == XferRp) { + xs |= 4; /* Check block overrun */ + } + } + else { /* In card write operation */ + n = (XferRp + 1) % N_BUF; /* Next read buffer */ + XferRp = n; + + if(n == XferWp) { + xs |= 4; /* Check block underrun */ + } + } + } else { /* An MCI error occured (not DataBlockEnd) */ - xs |= 8; - } + xs |= 8; + } - XferStat = xs; + XferStat = xs; - VICVectAddr = 0; + VICVectAddr = 0; } -void Isr_GPDMA (void) { - if(GPDMA_INT_TCSTAT & BIT0) - { +void Isr_GPDMA(void) +{ + if(GPDMA_INT_TCSTAT & BIT0) { GPDMA_INT_TCCLR = 0x01; /* Clear GPDMA interrupt flag */ - if (XferStat & 2) - { + + if(XferStat & 2) { /* In write operation */ - if (--XferWc == N_BUF) /* Terminate LLI */ - { + if(--XferWc == N_BUF) { /* Terminate LLI */ LinkList[XferRp % N_BUF][2] = 0; } } } - else - { + else { GPDMA_INT_TCCLR = 0x3; } - VICVectAddr = 0; + VICVectAddr = 0; } @@ -159,45 +167,49 @@ void Isr_GPDMA (void) { /** * @param blks Number of blocks to receive (1..127) - * @param bs Block size (64 or 512) + * @param bs Block size (64 or 512) * */ -static void ready_reception (unsigned int blks, unsigned int bs) { - unsigned int n; - unsigned long dma_ctrl; - - /* ------ Setting up GPDMA Ch-0 ------ */ - GPDMA_CH0_CFG &= 0xFFF80420; /* Disable ch-0 */ - GPDMA_INT_TCCLR = 0x01; /* Clear interrupt flag */ - dma_ctrl = 0x88492000 | (bs / 4); /* 1_000_1_0_00_010_010_010_010_************ */ - - /* Create link list */ - for (n = 0; n < N_BUF; n++) { - LinkList[n][0] = (unsigned long)&MCI_FIFO; - LinkList[n][1] = (unsigned long)DmaBuff[n]; - LinkList[n][2] = (unsigned long)LinkList[(n + 1) % N_BUF]; - LinkList[n][3] = dma_ctrl; - } - - /* Load first LLI */ - GPDMA_CH0_SRC = LinkList[0][0]; - GPDMA_CH0_DEST = LinkList[0][1]; - GPDMA_CH0_LLI = LinkList[0][2]; - GPDMA_CH0_CTRL = LinkList[0][3]; - - /* Enable ch-0 */ - GPDMA_CH0_CFG |= 0x19009; /* *************_0_0_1_1_0_010_*_0000_*_0100_1 */ - - /* --------- Setting up MCI ---------- */ - - XferRp = 0; XferWp = 0; /* Block FIFO R/W index */ - XferStat = 1; /* Transfer status: MCI --> Memory */ - - MCI_DATA_LEN = bs * blks; /* Set total data length */ - MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.2); /* Data timer: 0.2sec */ - MCI_CLEAR = 0x72A; /* Clear status flags */ - MCI_MASK0 = 0x72A; /* DataBlockEnd StartBitErr DataEnd RxOverrun DataTimeOut DataCrcFail */ - for (n = 0; bs > 1; bs >>= 1, n += 0x10); - MCI_DATA_CTRL = n | 0xB; /* Start to receive data blocks */ +static void ready_reception(unsigned int blks, unsigned int bs) +{ + unsigned int n; + unsigned long dma_ctrl; + + /* ------ Setting up GPDMA Ch-0 ------ */ + GPDMA_CH0_CFG &= 0xFFF80420; /* Disable ch-0 */ + GPDMA_INT_TCCLR = 0x01; /* Clear interrupt flag */ + dma_ctrl = 0x88492000 | (bs / 4); /* 1_000_1_0_00_010_010_010_010_************ */ + + /* Create link list */ + for(n = 0; n < N_BUF; n++) { + LinkList[n][0] = (unsigned long)&MCI_FIFO; + LinkList[n][1] = (unsigned long)DmaBuff[n]; + LinkList[n][2] = (unsigned long)LinkList[(n + 1) % N_BUF]; + LinkList[n][3] = dma_ctrl; + } + + /* Load first LLI */ + GPDMA_CH0_SRC = LinkList[0][0]; + GPDMA_CH0_DEST = LinkList[0][1]; + GPDMA_CH0_LLI = LinkList[0][2]; + GPDMA_CH0_CTRL = LinkList[0][3]; + + /* Enable ch-0 */ + GPDMA_CH0_CFG |= 0x19009; /* *************_0_0_1_1_0_010_*_0000_*_0100_1 */ + + /* --------- Setting up MCI ---------- */ + + XferRp = 0; + XferWp = 0; /* Block FIFO R/W index */ + XferStat = 1; /* Transfer status: MCI --> Memory */ + + MCI_DATA_LEN = bs * blks; /* Set total data length */ + MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.2); /* Data timer: 0.2sec */ + MCI_CLEAR = 0x72A; /* Clear status flags */ + MCI_MASK0 = 0x72A; /* DataBlockEnd StartBitErr DataEnd RxOverrun DataTimeOut DataCrcFail */ + + for(n = 0; bs > 1; bs >>= 1, n += 0x10); + + MCI_DATA_CTRL = n | 0xB; /* Start to receive data blocks */ } @@ -206,48 +218,49 @@ static void ready_reception (unsigned int blks, unsigned int bs) { /*-----------------------------------------------------------------------*/ #if _READONLY == 0 -/* - * @param blks Number of blocks to be transmitted (1..127) +/* + * @param blks Number of blocks to be transmitted (1..127) * */ -static void start_transmission ( unsigned char blks) { - unsigned int n; - unsigned long dma_ctrl; +static void start_transmission(unsigned char blks) +{ + unsigned int n; + unsigned long dma_ctrl; - /* ------ Setting up GPDMA Ch-0 ------ */ + /* ------ Setting up GPDMA Ch-0 ------ */ - GPDMA_CH0_CFG &= 0xFFF80420; /* Disable ch-0 */ - GPDMA_INT_TCCLR = 0x01; /* Clear interrupt flag */ - dma_ctrl = 0x84492080; /* 1_000_0_1_00_010_010_010_010_000010000000 */ + GPDMA_CH0_CFG &= 0xFFF80420; /* Disable ch-0 */ + GPDMA_INT_TCCLR = 0x01; /* Clear interrupt flag */ + dma_ctrl = 0x84492080; /* 1_000_0_1_00_010_010_010_010_000010000000 */ - /* Create link list */ - for (n = 0; n < N_BUF; n++) { - LinkList[n][0] = (unsigned long)DmaBuff[n]; - LinkList[n][1] = (unsigned long)&MCI_FIFO; - LinkList[n][2] = (n == blks - 1) ? 0 : (unsigned long)LinkList[(n + 1) % N_BUF]; - LinkList[n][3] = dma_ctrl; - } + /* Create link list */ + for(n = 0; n < N_BUF; n++) { + LinkList[n][0] = (unsigned long)DmaBuff[n]; + LinkList[n][1] = (unsigned long)&MCI_FIFO; + LinkList[n][2] = (n == blks - 1) ? 0 : (unsigned long)LinkList[(n + 1) % N_BUF]; + LinkList[n][3] = dma_ctrl; + } - /* Load first LLI */ - GPDMA_CH0_SRC = LinkList[0][0]; - GPDMA_CH0_DEST = LinkList[0][1]; - GPDMA_CH0_LLI = LinkList[0][2]; - GPDMA_CH0_CTRL = LinkList[0][3]; + /* Load first LLI */ + GPDMA_CH0_SRC = LinkList[0][0]; + GPDMA_CH0_DEST = LinkList[0][1]; + GPDMA_CH0_LLI = LinkList[0][2]; + GPDMA_CH0_CTRL = LinkList[0][3]; - /* Enable ch-0 */ - GPDMA_CH0_CFG |= 0x18901; /* *************_0_0_1_1_0_001_*_0100_*_0000_1 */ + /* Enable ch-0 */ + GPDMA_CH0_CFG |= 0x18901; /* *************_0_0_1_1_0_001_*_0100_*_0000_1 */ - /* --------- Setting up MCI ---------- */ + /* --------- Setting up MCI ---------- */ - XferRp = 0; /* Block FIFO read index */ - XferWc = blks; - XferStat = 2; /* Transfer status: Memroy --> MCI */ + XferRp = 0; /* Block FIFO read index */ + XferWc = blks; + XferStat = 2; /* Transfer status: Memroy --> MCI */ - MCI_DATA_LEN = 512 * (blks + 1); /* Set total data length */ - MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.5); /* Data timer: 0.5sec */ - MCI_CLEAR = 0x51A; /* Clear status flags */ - MCI_MASK0 = 0x51A; /* DataBlockEnd DataEnd TxUnderrun DataTimeOut DataCrcFail */ - MCI_DATA_CTRL = (9 << 4) | 0x9; /* Start to transmit data blocks */ + MCI_DATA_LEN = 512 * (blks + 1); /* Set total data length */ + MCI_DATA_TMR = (unsigned long)(MCLK_RW * 0.5); /* Data timer: 0.5sec */ + MCI_CLEAR = 0x51A; /* Clear status flags */ + MCI_MASK0 = 0x51A; /* DataBlockEnd DataEnd TxUnderrun DataTimeOut DataCrcFail */ + MCI_DATA_CTRL = (9 << 4) | 0x9; /* Start to transmit data blocks */ } #endif /* _READONLY */ @@ -258,11 +271,12 @@ static void start_transmission ( unsigned char blks) { /* Stop data transfer */ /*-----------------------------------------------------------------------*/ -static void stop_transfer (void) { - MCI_MASK0 = 0; /* Disable MCI interrupt */ - MCI_DATA_CTRL = 0; /* Stop MCI data transfer */ +static void stop_transfer(void) +{ + MCI_MASK0 = 0; /* Disable MCI interrupt */ + MCI_DATA_CTRL = 0; /* Stop MCI data transfer */ - GPDMA_CH0_CFG &= 0xFFF80420; /* Disable DMA ch-0 */ + GPDMA_CH0_CFG &= 0xFFF80420; /* Disable DMA ch-0 */ } @@ -272,81 +286,84 @@ static void stop_transfer (void) { /* Power Control (Device dependent) */ /*-----------------------------------------------------------------------*/ -static int power_status (void) { - return (MCI_POWER & 3) ? 1 : 0; +static int power_status(void) +{ + return (MCI_POWER & 3) ? 1 : 0; } -static void power_on (void) { - /* Enable MCI and GPDMA clock */ - PCONP |= (3 << 28); - - /* Enable GPDMA controller with little-endian */ - GPDMA_CH0_CFG &= 0xFFF80000; /* Disable DMA ch-0 */ - GPDMA_CONFIG = 0x01; - - /* Select PCLK for MCI, CCLK/2 = 36MHz */ - PCLKSEL1 = (PCLKSEL1 & 0xFCFFFFFF) | 0x02000000; - - //0.19 0.20 0.21 0.22 - PINMODE1 &= ~( (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13) ); - PINMODE1 |= (BIT7) | (BIT9) | (BIT11) | (BIT13); // no resistors - //2.11 2.12 2.13 - PINMODE4 &= ~( (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27) ); - PINMODE4 |= (BIT23) | (BIT25) | (BIT27); // no resistors - /* Attach MCI unit to I/O pad */ - PINSEL1 = (PINSEL1 & 0xFFFFC03F) | 0x00002A80; /* MCICLK, MCICMD, MCIDATA0, MCIPWR */ +static void power_on(void) +{ + /* Enable MCI and GPDMA clock */ + PCONP |= (3 << 28); + + /* Enable GPDMA controller with little-endian */ + GPDMA_CH0_CFG &= 0xFFF80000; /* Disable DMA ch-0 */ + GPDMA_CONFIG = 0x01; + + /* Select PCLK for MCI, CCLK/2 = 36MHz */ + PCLKSEL1 = (PCLKSEL1 & 0xFCFFFFFF) | 0x02000000; + + //0.19 0.20 0.21 0.22 + PINMODE1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13)); + PINMODE1 |= (BIT7) | (BIT9) | (BIT11) | (BIT13); // no resistors + //2.11 2.12 2.13 + PINMODE4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27)); + PINMODE4 |= (BIT23) | (BIT25) | (BIT27); // no resistors + /* Attach MCI unit to I/O pad */ + PINSEL1 = (PINSEL1 & 0xFFFFC03F) | 0x00002A80; /* MCICLK, MCICMD, MCIDATA0, MCIPWR */ #if USE_4BIT - PINSEL4 = (PINSEL4 & 0xF03FFFFF) | 0x0A800000; /* MCIDATA1-3 */ + PINSEL4 = (PINSEL4 & 0xF03FFFFF) | 0x0A800000; /* MCIDATA1-3 */ #endif - MCI_MASK0 = 0; - MCI_COMMAND = 0; - MCI_DATA_CTRL = 0; + MCI_MASK0 = 0; + MCI_COMMAND = 0; + MCI_DATA_CTRL = 0; - // pin 0.21 high active - SCS |= 0x08; + // pin 0.21 high active + SCS |= 0x08; - /* Register interrupt handlers for MCI,DMA event */ - //RegisterIrq(MCI_INT, Isr_MCI, PRI_LOWEST-1); - install_irq( MCI_INT, (void *)Isr_MCI, 5 ); + /* Register interrupt handlers for MCI,DMA event */ + //RegisterIrq(MCI_INT, Isr_MCI, PRI_LOWEST-1); + install_irq(MCI_INT, (void *)Isr_MCI, 5); - //RegisterIrq(GPDMA_INT, Isr_GPDMA, PRI_LOWEST-1); - install_irq( GPDMA_INT, (void *)Isr_GPDMA, 5 ); + //RegisterIrq(GPDMA_INT, Isr_GPDMA, PRI_LOWEST-1); + install_irq(GPDMA_INT, (void *)Isr_GPDMA, 5); - /* Power-on (VCC is always tied to the socket on this board) */ - MCI_POWER = 0x01; /* Power on */ + /* Power-on (VCC is always tied to the socket on this board) */ + MCI_POWER = 0x01; /* Power on */ - //for (Timer[0] = 10; Timer[0]; ) ; /* 10ms */ - hwtimer_wait(1000); + //for (Timer[0] = 10; Timer[0]; ) ; /* 10ms */ + hwtimer_wait(1000); - MCI_POWER = 0x03; /* Enable signals */ + MCI_POWER = 0x03; /* Enable signals */ } -static void power_off (void) { - MCI_MASK0 = 0; - MCI_COMMAND = 0; - MCI_DATA_CTRL = 0; +static void power_off(void) +{ + MCI_MASK0 = 0; + MCI_COMMAND = 0; + MCI_DATA_CTRL = 0; - MCI_POWER = 0; /* Power-off */ - MCI_CLOCK = 0; + MCI_POWER = 0; /* Power-off */ + MCI_CLOCK = 0; - // pin 0.21 low inactive - SCS &= ~0x08; + // pin 0.21 low inactive + SCS &= ~0x08; //0.21 MCI led Pin (turns sd card off, too) - //0.19 0.20 0.21 0.22 with pull-down - PINMODE1 |= (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13); - PINSEL1 &= ~( (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13) ); -// Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them) + //0.19 0.20 0.21 0.22 with pull-down + PINMODE1 |= (BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13); + PINSEL1 &= ~((BIT6 | BIT7) | (BIT8 | BIT9) | (BIT10 | BIT11) | (BIT12 | BIT13)); + // Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them) - //2.11 2.12 2.13 with pull-down - PINMODE4 |= (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27); - PINSEL4 &= ~( (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27) ); -// Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them) + //2.11 2.12 2.13 with pull-down + PINMODE4 |= (BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27); + PINSEL4 &= ~((BIT22 | BIT23) | (BIT24 | BIT25) | (BIT26 | BIT27)); + // Pins should be now configured as standard input (see board_init.c if you accidentally reconfigured them) - Stat |= STA_NOINIT; + Stat |= STA_NOINIT; } @@ -359,70 +376,90 @@ static void power_off (void) { * @param arg Command argument * @param rt Expected response type. None(0), Short(1) or Long(2) * @param *buff Response return buffer - * @return 1 when function succeeded otherwise returns 0 + * @return 1 when function succeeded otherwise returns 0 * */ -static int send_cmd (unsigned int idx, unsigned long arg, unsigned int rt, unsigned long *buff) { - unsigned int s, mc; - - if (idx & 0x80) { /* Send a CMD55 prior to the specified command if it is ACMD class */ - if (!send_cmd(CMD55, (unsigned long)CardRCA << 16, 1, buff) /* When CMD55 is faild, */ - || !(buff[0] & 0x00000020)) return 0; /* exit with error */ - } - idx &= 0x3F; /* Mask out ACMD flag */ - - do { /* Wait while CmdActive bit is set */ - MCI_COMMAND = 0; /* Cancel to transmit command */ - MCI_CLEAR = 0x0C5; /* Clear status flags */ - for (s = 0; s < 10; s++) MCI_STATUS; /* Skip lock out time of command reg. */ - } while (MCI_STATUS & 0x00800); - - MCI_ARGUMENT = arg; /* Set the argument into argument register */ - mc = 0x400 | idx; /* Enable bit + index */ - if (rt == 1) mc |= 0x040; /* Set Response bit to reveice short resp */ - if (rt > 1) mc |= 0x0C0; /* Set Response and LongResp bit to receive long resp */ - MCI_COMMAND = mc; /* Initiate command transaction */ - - //Timer[1] = 100; - uint32_t timerstart = hwtimer_now(); - - for (;;) { /* Wait for end of the cmd/resp transaction */ - - //if (!Timer[1]) return 0; - if(hwtimer_now() - timerstart > 10000) - { - return 0; - } - - s = MCI_STATUS; /* Get the transaction status */ - - if (rt == 0) - { - if (s & 0x080) - return 1; /* CmdSent */ +static int send_cmd(unsigned int idx, unsigned long arg, unsigned int rt, unsigned long *buff) +{ + unsigned int s, mc; + + if(idx & 0x80) { /* Send a CMD55 prior to the specified command if it is ACMD class */ + if(!send_cmd(CMD55, (unsigned long)CardRCA << 16, 1, buff) /* When CMD55 is faild, */ + || !(buff[0] & 0x00000020)) { + return 0; /* exit with error */ + } + } + + idx &= 0x3F; /* Mask out ACMD flag */ + + do { /* Wait while CmdActive bit is set */ + MCI_COMMAND = 0; /* Cancel to transmit command */ + MCI_CLEAR = 0x0C5; /* Clear status flags */ + + for(s = 0; s < 10; s++) { + MCI_STATUS; /* Skip lock out time of command reg. */ + } + } + while(MCI_STATUS & 0x00800); + + MCI_ARGUMENT = arg; /* Set the argument into argument register */ + mc = 0x400 | idx; /* Enable bit + index */ + + if(rt == 1) { + mc |= 0x040; /* Set Response bit to reveice short resp */ + } + + if(rt > 1) { + mc |= 0x0C0; /* Set Response and LongResp bit to receive long resp */ + } + + MCI_COMMAND = mc; /* Initiate command transaction */ + + //Timer[1] = 100; + uint32_t timerstart = hwtimer_now(); + + for(;;) { /* Wait for end of the cmd/resp transaction */ + + //if (!Timer[1]) return 0; + if(hwtimer_now() - timerstart > 10000) { + return 0; } - else - { - if (s & 0x040) - break; /* CmdRespEnd */ - if (s & 0x001) - { /* CmdCrcFail */ - if (idx == 1 || idx == 12 || idx == 41) /* Ignore CRC error on CMD1/12/41 */ + + s = MCI_STATUS; /* Get the transaction status */ + + if(rt == 0) { + if(s & 0x080) { + return 1; /* CmdSent */ + } + } + else { + if(s & 0x040) { + break; /* CmdRespEnd */ + } + + if(s & 0x001) { + /* CmdCrcFail */ + if(idx == 1 || idx == 12 || idx == 41) { /* Ignore CRC error on CMD1/12/41 */ break; + } + return 0; } - if (s & 0x004) - return 0; /* CmdTimeOut */ + + if(s & 0x004) { + return 0; /* CmdTimeOut */ + } } - } + } + + buff[0] = MCI_RESP0; /* Read the response words */ - buff[0] = MCI_RESP0; /* Read the response words */ - if (rt == 2) { - buff[1] = MCI_RESP1; - buff[2] = MCI_RESP2; - buff[3] = MCI_RESP3; - } + if(rt == 2) { + buff[1] = MCI_RESP1; + buff[2] = MCI_RESP2; + buff[3] = MCI_RESP3; + } - return 1; /* Return with success */ + return 1; /* Return with success */ } @@ -436,21 +473,23 @@ static int send_cmd (unsigned int idx, unsigned long arg, unsigned int rt, unsig * @param tmr Timeout in unit of 1ms * @returns 1 when card is tran state, otherwise returns 0 */ -static int wait_ready (unsigned short tmr) { +static int wait_ready(unsigned short tmr) +{ unsigned long rc; - uint32_t stoppoll = hwtimer_now() + tmr * 100; - bool bBreak = false; - while (hwtimer_now() < stoppoll/*Timer[0]*/) - { - if (send_cmd(CMD13, (unsigned long) CardRCA << 16, 1, &rc) && ((rc & 0x01E00) == 0x00800)) - { + uint32_t stoppoll = hwtimer_now() + tmr * 100; + bool bBreak = false; + + while(hwtimer_now() < stoppoll/*Timer[0]*/) { + if(send_cmd(CMD13, (unsigned long) CardRCA << 16, 1, &rc) && ((rc & 0x01E00) == 0x00800)) { bBreak = true; break; } + /* This loop will take a time. Insert rot_rdq() here for multitask envilonment. */ } - return bBreak;//Timer[0] ? 1 : 0; + + return bBreak;//Timer[0] ? 1 : 0; } @@ -459,15 +498,16 @@ static int wait_ready (unsigned short tmr) { /*-----------------------------------------------------------------------*/ /* Swap byte order */ /*-----------------------------------------------------------------------*/ -static void bswap_cp (unsigned char *dst, const unsigned long *src) { - unsigned long d; +static void bswap_cp(unsigned char *dst, const unsigned long *src) +{ + unsigned long d; - d = *src; - *dst++ = (unsigned char)(d >> 24); - *dst++ = (unsigned char)(d >> 16); - *dst++ = (unsigned char)(d >> 8); - *dst++ = (unsigned char)(d >> 0); + d = *src; + *dst++ = (unsigned char)(d >> 24); + *dst++ = (unsigned char)(d >> 16); + *dst++ = (unsigned char)(d >> 8); + *dst++ = (unsigned char)(d >> 0); } @@ -483,136 +523,153 @@ static void bswap_cp (unsigned char *dst, const unsigned long *src) { /*-----------------------------------------------------------------------*/ /* Initialize Disk Drive */ /*-----------------------------------------------------------------------*/ -DSTATUS MCI_initialize (void) { - unsigned int cmd, n; - unsigned long resp[4]; - unsigned char ty; +DSTATUS MCI_initialize(void) +{ + unsigned int cmd, n; + unsigned long resp[4]; + unsigned char ty; - if (Stat & STA_NODISK) return Stat; /* No card in the socket */ + if(Stat & STA_NODISK) { + return Stat; /* No card in the socket */ + } - power_off(); + power_off(); - hwtimer_wait(HWTIMER_TICKS(1000)); + hwtimer_wait(HWTIMER_TICKS(1000)); - power_on(); /* Force socket power on */ - MCI_CLOCK = 0x100 | (PCLK/MCLK_ID/2-1); /* Set MCICLK = MCLK_ID */ - //for (Timer[0] = 2; Timer[0]; ); - hwtimer_wait(250); + power_on(); /* Force socket power on */ + MCI_CLOCK = 0x100 | (PCLK / MCLK_ID / 2 - 1); /* Set MCICLK = MCLK_ID */ + //for (Timer[0] = 2; Timer[0]; ); + hwtimer_wait(250); - send_cmd(CMD0, 0, 0, NULL); /* Enter idle state */ - CardRCA = 0; + send_cmd(CMD0, 0, 0, NULL); /* Enter idle state */ + CardRCA = 0; - /*---- Card is 'idle' state ----*/ + /*---- Card is 'idle' state ----*/ /* Initialization timeout of 1000 msec */ - uint32_t start = hwtimer_now(); + uint32_t start = hwtimer_now(); - /* SDC Ver2 */ - if (send_cmd(CMD8, 0x1AA, 1, resp) && (resp[0] & 0xFFF) == 0x1AA) { + /* SDC Ver2 */ + if(send_cmd(CMD8, 0x1AA, 1, resp) && (resp[0] & 0xFFF) == 0x1AA) { /* The card can work at vdd range of 2.7-3.6V */ DEBUG("SDC Ver. 2\n"); - do { /* Wait while card is busy state (use ACMD41 with HCS bit) */ - /* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */ - if (hwtimer_now() > start + 1000000/*!Timer[0]*/) { + do { /* Wait while card is busy state (use ACMD41 with HCS bit) */ + /* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */ + if(hwtimer_now() > start + 1000000/*!Timer[0]*/) { DEBUG("%s, %d: Timeout #1\n", __FILE__, __LINE__); goto di_fail; } - } while (!send_cmd(ACMD41, 0x40FF8000, 1, resp) || !(resp[0] & 0x80000000)); + } + while(!send_cmd(ACMD41, 0x40FF8000, 1, resp) || !(resp[0] & 0x80000000)); - ty = (resp[0] & 0x40000000) ? CT_SD2|CT_BLOCK : CT_SD2; /* Check CCS bit in the OCR */ - } - else { /* SDC Ver1 or MMC */ - if (send_cmd(ACMD41, 0x00FF8000, 1, resp)) { + ty = (resp[0] & 0x40000000) ? CT_SD2 | CT_BLOCK : CT_SD2; /* Check CCS bit in the OCR */ + } + else { /* SDC Ver1 or MMC */ + if(send_cmd(ACMD41, 0x00FF8000, 1, resp)) { DEBUG("SDC Ver. 1\n"); - ty = CT_SD1; + ty = CT_SD1; cmd = ACMD41; /* ACMD41 is accepted -> SDC Ver1 */ - } + } else { DEBUG("MMC\n"); - ty = CT_MMC; + ty = CT_MMC; cmd = CMD1; /* ACMD41 is rejected -> MMC */ - } - do { /* Wait while card is busy state (use ACMD41 or CMD1) */ + } + + do { /* Wait while card is busy state (use ACMD41 or CMD1) */ DEBUG("%s, %d: %lX\n", __FILE__, __LINE__, resp[0]); - /* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */ - if (hwtimer_now() > start + 1000000/*!Timer[0]*/) { + + /* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */ + if(hwtimer_now() > start + 1000000/*!Timer[0]*/) { DEBUG("now: %lu, started at: %lu\n", hwtimer_now(), start); DEBUG("%s, %d: Timeout #2\n", __FILE__, __LINE__); goto di_fail; } - } while (!send_cmd(cmd, 0x00FF8000, 1, resp) || !(resp[0] & 0x80000000)); - } + } + while(!send_cmd(cmd, 0x00FF8000, 1, resp) || !(resp[0] & 0x80000000)); + } - CardType = ty; /* Save card type */ - bswap_cp(&CardInfo[32], resp); /* Save OCR */ + CardType = ty; /* Save card type */ + bswap_cp(&CardInfo[32], resp); /* Save OCR */ - /*---- Card is 'ready' state ----*/ + /*---- Card is 'ready' state ----*/ - if (!send_cmd(CMD2, 0, 2, resp)) { + if(!send_cmd(CMD2, 0, 2, resp)) { DEBUG("%s, %d: Failed entering ident state", __FILE__, __LINE__); goto di_fail; /* Enter ident state */ } - for (n = 0; n < 4; n++) bswap_cp(&CardInfo[n * 4 + 16], &resp[n]); /* Save CID */ - /*---- Card is 'ident' state ----*/ + for(n = 0; n < 4; n++) { + bswap_cp(&CardInfo[n * 4 + 16], &resp[n]); /* Save CID */ + } + + /*---- Card is 'ident' state ----*/ - if (ty & CT_SDC) { /* SDC: Get generated RCA and save it */ - if (!send_cmd(CMD3, 0, 1, resp)) { + if(ty & CT_SDC) { /* SDC: Get generated RCA and save it */ + if(!send_cmd(CMD3, 0, 1, resp)) { DEBUG("%s, %d: Failed generating RCA\n", __FILE__, __LINE__); goto di_fail; } - CardRCA = (unsigned short)(resp[0] >> 16); - } else { /* MMC: Assign RCA to the card */ - if (!send_cmd(CMD3, 1 << 16, 1, resp)) goto di_fail; - CardRCA = 1; - } - - /*---- Card is 'stby' state ----*/ - - if (!send_cmd(CMD9, (unsigned long)CardRCA << 16, 2, resp)) /* Get CSD and save it */ - { - goto di_fail; - } - for (n = 0; n < 4; n++) bswap_cp(&CardInfo[n * 4], &resp[n]); - - if (!send_cmd(CMD7, (unsigned long)CardRCA << 16, 1, resp)) /* Select card */ - { - //printf("MCI CMD7 fail\n"); - goto di_fail; - } - - /*---- Card is 'tran' state ----*/ - - if (!(ty & CT_BLOCK)) { /* Set data block length to 512 (for byte addressing cards) */ - if (!send_cmd(CMD16, 512, 1, resp) || (resp[0] & 0xFDF90000)) - { - //printf("MCI CMD16 fail\n"); - goto di_fail; - } - } + + CardRCA = (unsigned short)(resp[0] >> 16); + } + else { /* MMC: Assign RCA to the card */ + if(!send_cmd(CMD3, 1 << 16, 1, resp)) { + goto di_fail; + } + + CardRCA = 1; + } + + /*---- Card is 'stby' state ----*/ + + if(!send_cmd(CMD9, (unsigned long)CardRCA << 16, 2, resp)) { /* Get CSD and save it */ + goto di_fail; + } + + for(n = 0; n < 4; n++) { + bswap_cp(&CardInfo[n * 4], &resp[n]); + } + + if(!send_cmd(CMD7, (unsigned long)CardRCA << 16, 1, resp)) { /* Select card */ + //printf("MCI CMD7 fail\n"); + goto di_fail; + } + + /*---- Card is 'tran' state ----*/ + + if(!(ty & CT_BLOCK)) { /* Set data block length to 512 (for byte addressing cards) */ + if(!send_cmd(CMD16, 512, 1, resp) || (resp[0] & 0xFDF90000)) { + //printf("MCI CMD16 fail\n"); + goto di_fail; + } + } #if USE_4BIT - if (ty & CT_SDC) { /* Set wide bus mode (for SDCs) */ - if (!send_cmd(ACMD6, 2, 1, resp) /* Set bus mode of SDC */ - || (resp[0] & 0xFDF90000)) - { - //printf("MCI ACMD6 fail\n"); - goto di_fail; - } - MCI_CLOCK |= 0x800; /* Set bus mode of MCI */ - } + + if(ty & CT_SDC) { /* Set wide bus mode (for SDCs) */ + if(!send_cmd(ACMD6, 2, 1, resp) /* Set bus mode of SDC */ + || (resp[0] & 0xFDF90000)) { + //printf("MCI ACMD6 fail\n"); + goto di_fail; + } + + MCI_CLOCK |= 0x800; /* Set bus mode of MCI */ + } + #endif - MCI_CLOCK = (MCI_CLOCK & 0xF00) | 0x200 | (PCLK/MCLK_RW/2-1); /* Set MCICLK = MCLK_RW, power-save mode */ + MCI_CLOCK = (MCI_CLOCK & 0xF00) | 0x200 | (PCLK / MCLK_RW / 2 - 1); /* Set MCICLK = MCLK_RW, power-save mode */ - Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ - return Stat; + Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */ + return Stat; di_fail: - power_off(); - Stat |= STA_NOINIT; /* Set STA_NOINIT */ - return Stat; + power_off(); + Stat |= STA_NOINIT; /* Set STA_NOINIT */ + return Stat; } @@ -622,8 +679,9 @@ di_fail: /* Get Disk Status */ /*-----------------------------------------------------------------------*/ -DSTATUS MCI_status (void) { - return Stat; +DSTATUS MCI_status(void) +{ + return Stat; } @@ -636,56 +694,69 @@ DSTATUS MCI_status (void) { /** * @param buff Pointer to the data buffer to store read data * @param sector Start sector number (LBA) - * @param count Sector count (1..127) + * @param count Sector count (1..127) */ -DRESULT MCI_read (unsigned char *buff, unsigned long sector, unsigned char count) { +DRESULT MCI_read(unsigned char *buff, unsigned long sector, unsigned char count) +{ unsigned long resp; - unsigned int cmd; - unsigned char rp; + unsigned int cmd; + unsigned char rp; + + + if(count < 1 || count > 127) { + return RES_PARERR; /* Check parameter */ + } + if(Stat & STA_NOINIT) { + return RES_NOTRDY; /* Check drive status */ + } + + if(!(CardType & CT_BLOCK)) { + sector *= 512; /* Convert LBA to byte address if needed */ + } - if (count < 1 || count > 127) return RES_PARERR; /* Check parameter */ - if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check drive status */ + if(!wait_ready(500)) { + return RES_ERROR; /* Make sure that card is tran state */ + } - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert LBA to byte address if needed */ - if (!wait_ready(500)) return RES_ERROR; /* Make sure that card is tran state */ + ready_reception(count, 512); /* Ready to receive data blocks */ - ready_reception(count, 512); /* Ready to receive data blocks */ + cmd = (count > 1) ? CMD18 : CMD17; /* Transfer type: Single block or Multiple block */ - cmd = (count > 1) ? CMD18 : CMD17; /* Transfer type: Single block or Multiple block */ + if(send_cmd(cmd, sector, 1, &resp) /* Start to read */ + && !(resp & 0xC0580000)) { + rp = 0; - if (send_cmd(cmd, sector, 1, &resp) /* Start to read */ - && !(resp & 0xC0580000)) - { - rp = 0; - do - { - while ((rp == XferWp) && !(XferStat & 0xC)) - { /* Wait for block arrival */ + do { + while((rp == XferWp) && !(XferStat & 0xC)) { + /* Wait for block arrival */ /* This loop will take a time. Replace it with sync process for multitask envilonment. */ } - if (XferStat & 0xC) - { + + if(XferStat & 0xC) { break; /* Abort if any error has occured */ } Copy_al2un(buff, DmaBuff[rp], 512); /* Pop an block */ XferRp = rp = (rp + 1) % N_BUF; /* Next DMA buffer */ - if (XferStat & 0xC) - { + + if(XferStat & 0xC) { break; /* Abort if overrun has occured */ } + buff += 512; /* Next user buffer address */ } - while (--count); - if (cmd == CMD18) /* Terminate to read (MB) */ + while(--count); + + if(cmd == CMD18) { /* Terminate to read (MB) */ send_cmd(CMD12, 0, 1, &resp); + } } stop_transfer(); /* Close data path */ - return count ? RES_ERROR : RES_OK; + return count ? RES_ERROR : RES_OK; } @@ -696,70 +767,102 @@ DRESULT MCI_read (unsigned char *buff, unsigned long sector, unsigned char count #if _READONLY == 0 /** - * @param buff Pointer to the data to be written + * @param buff Pointer to the data to be written * @param sector Start sector number (LBA) * @param count Sector count (1..127) * */ -DRESULT MCI_write (const unsigned char *buff, unsigned long sector, unsigned char count) { - unsigned long rc; - unsigned int cmd; - unsigned char wp, xc; +DRESULT MCI_write(const unsigned char *buff, unsigned long sector, unsigned char count) +{ + unsigned long rc; + unsigned int cmd; + unsigned char wp, xc; - if (count < 1 || count > 127) return RES_PARERR; /* Check parameter */ - if (Stat & STA_NOINIT) return RES_NOTRDY; /* Check drive status */ - if (Stat & STA_PROTECT) return RES_WRPRT; /* Check write protection */ + if(count < 1 || count > 127) { + return RES_PARERR; /* Check parameter */ + } - if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert LBA to byte address if needed */ - if (!wait_ready(500)) return RES_ERROR; /* Make sure that card is tran state */ + if(Stat & STA_NOINIT) { + return RES_NOTRDY; /* Check drive status */ + } - if (count == 1) { /* Single block write */ - cmd = CMD24; - } + if(Stat & STA_PROTECT) { + return RES_WRPRT; /* Check write protection */ + } + + if(!(CardType & CT_BLOCK)) { + sector *= 512; /* Convert LBA to byte address if needed */ + } + + if(!wait_ready(500)) { + return RES_ERROR; /* Make sure that card is tran state */ + } + + if(count == 1) { /* Single block write */ + cmd = CMD24; + } else { /* Multiple block write */ - cmd = (CardType & CT_SDC) ? ACMD23 : CMD23; - if (!send_cmd(cmd, count, 1, &rc) /* Preset number of blocks to write */ - || (rc & 0xC0580000)) { - return RES_ERROR; - } - cmd = CMD25; - } - - if (!send_cmd(cmd, sector, 1, &rc) /* Send a write command */ - || (rc & 0xC0580000)) { - return RES_ERROR; - } - - wp = 0; + cmd = (CardType & CT_SDC) ? ACMD23 : CMD23; + + if(!send_cmd(cmd, count, 1, &rc) /* Preset number of blocks to write */ + || (rc & 0xC0580000)) { + return RES_ERROR; + } + + cmd = CMD25; + } + + if(!send_cmd(cmd, sector, 1, &rc) /* Send a write command */ + || (rc & 0xC0580000)) { + return RES_ERROR; + } + + wp = 0; xc = count; - do { /* Fill block FIFO */ - Copy_un2al(DmaBuff[wp], (unsigned char*)(unsigned int)buff, 512); /* Push a block */ - wp++; /* Next DMA buffer */ - count--; + + do { /* Fill block FIFO */ + Copy_un2al(DmaBuff[wp], (unsigned char *)(unsigned int)buff, 512); /* Push a block */ + wp++; /* Next DMA buffer */ + count--; buff += 512; /* Next user buffer address */ - } while (count && wp < N_BUF); - XferWp = wp = wp % N_BUF; - start_transmission(xc); /* Start transmission */ - - while (count) { - while((wp == XferRp) && !(XferStat & 0xC)) { /* Wait for block FIFO not full */ - /* This loop will take a time. Replace it with sync process for multitask envilonment. */ - } - if (XferStat & 0xC) break; /* Abort if block underrun or any MCI error has occured */ - Copy_un2al(DmaBuff[wp], (unsigned char*)(unsigned int)buff, 512); /* Push a block */ - XferWp = wp = (wp + 1) % N_BUF; /* Next DMA buffer */ - if (XferStat & 0xC) break; /* Abort if block underrun has occured */ - count--; + } + while(count && wp < N_BUF); + + XferWp = wp = wp % N_BUF; + start_transmission(xc); /* Start transmission */ + + while(count) { + while((wp == XferRp) && !(XferStat & 0xC)) { /* Wait for block FIFO not full */ + /* This loop will take a time. Replace it with sync process for multitask envilonment. */ + } + + if(XferStat & 0xC) { + break; /* Abort if block underrun or any MCI error has occured */ + } + + Copy_un2al(DmaBuff[wp], (unsigned char *)(unsigned int)buff, 512); /* Push a block */ + XferWp = wp = (wp + 1) % N_BUF; /* Next DMA buffer */ + + if(XferStat & 0xC) { + break; /* Abort if block underrun has occured */ + } + + count--; buff += 512; /* Next user buffer address */ - } + } - while (!(XferStat & 0xC)); /* Wait for all blocks sent (block underrun) */ - if (XferStat & 0x8) count = 1; /* Abort if any MCI error has occured */ + while(!(XferStat & 0xC)); /* Wait for all blocks sent (block underrun) */ - stop_transfer(); /* Close data path */ - if (cmd == CMD25 && (CardType & CT_SDC)) /* Terminate to write (SDC w/MB) */ - send_cmd(CMD12, 0, 1, &rc); + if(XferStat & 0x8) { + count = 1; /* Abort if any MCI error has occured */ + } - return count ? RES_ERROR : RES_OK; + stop_transfer(); /* Close data path */ + + if(cmd == CMD25 && (CardType & CT_SDC)) { /* Terminate to write (SDC w/MB) */ + send_cmd(CMD12, 0, 1, &rc); + } + + return count ? RES_ERROR : RES_OK; } #endif /* _READONLY */ @@ -770,120 +873,147 @@ DRESULT MCI_write (const unsigned char *buff, unsigned long sector, unsigned cha /* Miscellaneous Functions */ /*-----------------------------------------------------------------------*/ -DRESULT MCI_ioctl ( - unsigned char ctrl, /* Control code */ - void *buff /* Buffer to send/receive data block */ +DRESULT MCI_ioctl( + unsigned char ctrl, /* Control code */ + void *buff /* Buffer to send/receive data block */ ) { - DRESULT res; - unsigned char b, *ptr = buff; - unsigned long resp[4], d, *dp, st, ed; - - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - res = RES_ERROR; - - switch (ctrl) { - case CTRL_SYNC : /* Make sure that all data has been written on the media */ - if (wait_ready(500)) /* Wait for card enters tarn state */ - res = RES_OK; - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (unsigned long) */ - if ((CardInfo[0] >> 6) == 1) { /* SDC CSD v2.0 */ - d = ((unsigned short)CardInfo[8] << 8) + CardInfo[9] + 1; - *(unsigned long*)buff = d << 10; - } else { /* MMC or SDC CSD v1.0 */ - b = (CardInfo[5] & 15) + ((CardInfo[10] & 128) >> 7) + ((CardInfo[9] & 3) << 1) + 2; - d = (CardInfo[8] >> 6) + ((unsigned short)CardInfo[7] << 2) + ((unsigned short)(CardInfo[6] & 3) << 10) + 1; - *(unsigned long*)buff = d << (b - 9); - } - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get sectors on the disk (unsigned short) */ - *(unsigned short*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (unsigned long) */ - if (CardType & CT_SD2) { /* SDC ver 2.00 */ - *(unsigned long*)buff = 16UL << (CardInfo[10] >> 4); - } else { /* SDC ver 1.XX or MMC */ - if (CardType & CT_SD1) /* SDC v1 */ - *(unsigned long*)buff = (((CardInfo[10] & 63) << 1) + ((unsigned short)(CardInfo[11] & 128) >> 7) + 1) << ((CardInfo[13] >> 6) - 1); - else /* MMC */ - *(unsigned long*)buff = ((unsigned short)((CardInfo[10] & 124) >> 2) + 1) * (((CardInfo[11] & 3) << 3) + ((CardInfo[11] & 224) >> 5) + 1); - } - res = RES_OK; - break; - - case CTRL_ERASE_SECTOR : /* Erase a block of sectors */ - if (!(CardType & CT_SDC) || (!(CardInfo[0] >> 6) && !(CardInfo[10] & 0x40))) break; /* Check if sector erase can be applied to the card */ - dp = buff; st = dp[0]; ed = dp[1]; - if (!(CardType & CT_BLOCK)) { - st *= 512; ed *= 512; - } - if (send_cmd(CMD32, st, 1, resp) && send_cmd(CMD33, ed, 1, resp) && send_cmd(CMD38, 0, 1, resp) && wait_ready(30000)) - res = RES_OK; - break; - - case CTRL_POWER : - switch (ptr[0]) { - case 0: /* Sub control code == 0 (POWER_OFF) */ - power_off(); /* Power off */ - res = RES_OK; - break; - case 1: /* Sub control code == 1 (POWER_GET) */ - ptr[1] = (unsigned char)power_status(); - res = RES_OK; - break; - default : - res = RES_PARERR; - } - break; - - case MMC_GET_TYPE : /* Get card type flags (1 byte) */ - *ptr = CardType; - res = RES_OK; - break; - - case MMC_GET_CSD : /* Get CSD (16 bytes) */ - memcpy(buff, &CardInfo[0], 16); - res = RES_OK; - break; - - case MMC_GET_CID : /* Get CID (16 bytes) */ - memcpy(buff, &CardInfo[16], 16); - res = RES_OK; - break; - - case MMC_GET_OCR : /* Get OCR (4 bytes) */ - memcpy(buff, &CardInfo[32], 4); - res = RES_OK; - break; - - case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ - if (CardType & CT_SDC) { /* SDC */ - if (wait_ready(500)) { - ready_reception(1, 64); /* Ready to receive data blocks */ - if (send_cmd(ACMD13, 0, 1, resp) /* Start to read */ - && !(resp[0] & 0xC0580000)) { - while ((XferWp == 0) && !(XferStat & 0xC)); - if (!(XferStat & 0xC)) { - Copy_al2un(buff, DmaBuff[0], 64); - res = RES_OK; - } - } - } - stop_transfer(); /* Close data path */ - } - break; - - default: - res = RES_PARERR; - } - - return res; + DRESULT res; + unsigned char b, *ptr = buff; + unsigned long resp[4], d, *dp, st, ed; + + + if(Stat & STA_NOINIT) { + return RES_NOTRDY; + } + + res = RES_ERROR; + + switch(ctrl) { + case CTRL_SYNC : /* Make sure that all data has been written on the media */ + if(wait_ready(500)) { /* Wait for card enters tarn state */ + res = RES_OK; + } + + break; + + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (unsigned long) */ + if((CardInfo[0] >> 6) == 1) { /* SDC CSD v2.0 */ + d = ((unsigned short)CardInfo[8] << 8) + CardInfo[9] + 1; + *(unsigned long *)buff = d << 10; + } + else { /* MMC or SDC CSD v1.0 */ + b = (CardInfo[5] & 15) + ((CardInfo[10] & 128) >> 7) + ((CardInfo[9] & 3) << 1) + 2; + d = (CardInfo[8] >> 6) + ((unsigned short)CardInfo[7] << 2) + ((unsigned short)(CardInfo[6] & 3) << 10) + 1; + *(unsigned long *)buff = d << (b - 9); + } + + res = RES_OK; + break; + + case GET_SECTOR_SIZE : /* Get sectors on the disk (unsigned short) */ + *(unsigned short *)buff = 512; + res = RES_OK; + break; + + case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (unsigned long) */ + if(CardType & CT_SD2) { /* SDC ver 2.00 */ + *(unsigned long *)buff = 16UL << (CardInfo[10] >> 4); + } + else { /* SDC ver 1.XX or MMC */ + if(CardType & CT_SD1) { /* SDC v1 */ + *(unsigned long *)buff = (((CardInfo[10] & 63) << 1) + ((unsigned short)(CardInfo[11] & 128) >> 7) + 1) << ((CardInfo[13] >> 6) - 1); + } + else { /* MMC */ + *(unsigned long *)buff = ((unsigned short)((CardInfo[10] & 124) >> 2) + 1) * (((CardInfo[11] & 3) << 3) + ((CardInfo[11] & 224) >> 5) + 1); + } + } + + res = RES_OK; + break; + + case CTRL_ERASE_SECTOR : /* Erase a block of sectors */ + if(!(CardType & CT_SDC) || (!(CardInfo[0] >> 6) && !(CardInfo[10] & 0x40))) { + break; /* Check if sector erase can be applied to the card */ + } + + dp = buff; + st = dp[0]; + ed = dp[1]; + + if(!(CardType & CT_BLOCK)) { + st *= 512; + ed *= 512; + } + + if(send_cmd(CMD32, st, 1, resp) && send_cmd(CMD33, ed, 1, resp) && send_cmd(CMD38, 0, 1, resp) && wait_ready(30000)) { + res = RES_OK; + } + + break; + + case CTRL_POWER : + switch(ptr[0]) { + case 0: /* Sub control code == 0 (POWER_OFF) */ + power_off(); /* Power off */ + res = RES_OK; + break; + + case 1: /* Sub control code == 1 (POWER_GET) */ + ptr[1] = (unsigned char)power_status(); + res = RES_OK; + break; + + default : + res = RES_PARERR; + } + + break; + + case MMC_GET_TYPE : /* Get card type flags (1 byte) */ + *ptr = CardType; + res = RES_OK; + break; + + case MMC_GET_CSD : /* Get CSD (16 bytes) */ + memcpy(buff, &CardInfo[0], 16); + res = RES_OK; + break; + + case MMC_GET_CID : /* Get CID (16 bytes) */ + memcpy(buff, &CardInfo[16], 16); + res = RES_OK; + break; + + case MMC_GET_OCR : /* Get OCR (4 bytes) */ + memcpy(buff, &CardInfo[32], 4); + res = RES_OK; + break; + + case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ + if(CardType & CT_SDC) { /* SDC */ + if(wait_ready(500)) { + ready_reception(1, 64); /* Ready to receive data blocks */ + + if(send_cmd(ACMD13, 0, 1, resp) /* Start to read */ + && !(resp[0] & 0xC0580000)) { + while((XferWp == 0) && !(XferStat & 0xC)); + + if(!(XferStat & 0xC)) { + Copy_al2un(buff, DmaBuff[0], 64); + res = RES_OK; + } + } + } + + stop_transfer(); /* Close data path */ + } + + break; + + default: + res = RES_PARERR; + } + + return res; } diff --git a/cpu/lpc2387/rtc/lpc2387-rtc.c b/cpu/lpc2387/rtc/lpc2387-rtc.c index c9aec8793..41f9ec45d 100644 --- a/cpu/lpc2387/rtc/lpc2387-rtc.c +++ b/cpu/lpc2387/rtc/lpc2387-rtc.c @@ -26,7 +26,7 @@ License. See the file LICENSE in the top level directory for more details. #include #include -// cpu +/* cpu */ #include "VIC.h" #include "lpc2387.h" #include "lpc2387-rtc.h" @@ -49,183 +49,192 @@ static volatile time_t epoch; * @param[in] localt Pointer to structure with time to set */ void -rtc_set_localtime(struct tm* localt) +rtc_set_localtime(struct tm *localt) { - if( localt == NULL ) - return; - - /* set clock */ - RTC_SEC = localt->tm_sec; - RTC_MIN = localt->tm_min; - RTC_HOUR = localt->tm_hour; - RTC_DOM = localt->tm_mday; - RTC_DOW = localt->tm_wday; - RTC_DOY = localt->tm_yday; - RTC_MONTH = localt->tm_mon + 1; - RTC_YEAR = localt->tm_year; + if(localt == NULL) { + return; + } + + /* set clock */ + RTC_SEC = localt->tm_sec; + RTC_MIN = localt->tm_min; + RTC_HOUR = localt->tm_hour; + RTC_DOM = localt->tm_mday; + RTC_DOW = localt->tm_wday; + RTC_DOY = localt->tm_yday; + RTC_MONTH = localt->tm_mon + 1; + RTC_YEAR = localt->tm_year; } /*---------------------------------------------------------------------------*/ -void rtc_set(time_t time) { - struct tm* localt; - localt = localtime(&time); // convert seconds to broken-down time - rtc_set_localtime(localt); - epoch = time - localt->tm_sec - localt->tm_min * 60; +void rtc_set(time_t time) +{ + struct tm *localt; + localt = localtime(&time); /* convert seconds to broken-down time */ + rtc_set_localtime(localt); + epoch = time - localt->tm_sec - localt->tm_min * 60; } /*---------------------------------------------------------------------------*/ -/// set clock to start of unix epoch +//* set clock to start of unix epoch */ void rtc_reset(void) { rtc_set(0); - epoch = 0; + epoch = 0; } /*---------------------------------------------------------------------------*/ void -rtc_set_alarm(struct tm* localt, enum rtc_alarm_mask mask) +rtc_set_alarm(struct tm *localt, enum rtc_alarm_mask mask) { - if( localt != NULL ) { - RTC_ALSEC = localt->tm_sec; - RTC_ALMIN = localt->tm_min; - RTC_ALHOUR = localt->tm_hour; - RTC_ALDOM = localt->tm_mday; - RTC_ALDOW = localt->tm_wday; - RTC_ALDOY = localt->tm_yday; - RTC_ALMON = localt->tm_mon + 1; - RTC_ALYEAR = localt->tm_year; - RTC_AMR = ~mask; // set wich alarm fields to check - DEBUG("alarm set %2lu.%2lu.%4lu %2lu:%2lu:%2lu\n", - RTC_ALDOM, RTC_ALMON, RTC_ALYEAR, RTC_ALHOUR, RTC_ALMIN, RTC_ALSEC); - } else { - RTC_AMR = 0xff; - } + if(localt != NULL) { + RTC_ALSEC = localt->tm_sec; + RTC_ALMIN = localt->tm_min; + RTC_ALHOUR = localt->tm_hour; + RTC_ALDOM = localt->tm_mday; + RTC_ALDOW = localt->tm_wday; + RTC_ALDOY = localt->tm_yday; + RTC_ALMON = localt->tm_mon + 1; + RTC_ALYEAR = localt->tm_year; + RTC_AMR = ~mask; /* set wich alarm fields to check */ + DEBUG("alarm set %2lu.%2lu.%4lu %2lu:%2lu:%2lu\n", + RTC_ALDOM, RTC_ALMON, RTC_ALYEAR, RTC_ALHOUR, RTC_ALMIN, RTC_ALSEC); + } + else { + RTC_AMR = 0xff; + } } /*---------------------------------------------------------------------------*/ enum rtc_alarm_mask -rtc_get_alarm(struct tm* localt) +rtc_get_alarm(struct tm *localt) { - if( localt != NULL ) { - localt->tm_sec = RTC_ALSEC; - localt->tm_min = RTC_ALMIN; - localt->tm_hour = RTC_ALHOUR; - localt->tm_mday = RTC_ALDOM; - localt->tm_wday = RTC_ALDOW; - localt->tm_yday = RTC_ALDOY; - localt->tm_mon = RTC_ALMON - 1; - localt->tm_year = RTC_ALYEAR; - localt->tm_isdst = -1; // not available - } - return (~RTC_AMR) & 0xff; // return which alarm fields are checked + if(localt != NULL) { + localt->tm_sec = RTC_ALSEC; + localt->tm_min = RTC_ALMIN; + localt->tm_hour = RTC_ALHOUR; + localt->tm_mday = RTC_ALDOM; + localt->tm_wday = RTC_ALDOW; + localt->tm_yday = RTC_ALDOY; + localt->tm_mon = RTC_ALMON - 1; + localt->tm_year = RTC_ALYEAR; + localt->tm_isdst = -1; /* not available */ + } + + return (~RTC_AMR) & 0xff; /* return which alarm fields are checked */ } /*---------------------------------------------------------------------------*/ -void RTC_IRQHandler (void) __attribute__ ((interrupt("IRQ"))); -void RTC_IRQHandler (void) +void RTC_IRQHandler(void) __attribute__((interrupt("IRQ"))); +void RTC_IRQHandler(void) { - lpm_begin_awake(); - if( RTC_ILR & ILR_RTSSF ) { - // sub second interrupt (does not need flag-clearing) - - } else if( RTC_ILR & ILR_RTCCIF ) { - // counter increase interrupt - RTC_ILR |= ILR_RTCCIF; - epoch += 60 * 60; // add 1 hour - - } else if( RTC_ILR & ILR_RTCALF ) { - RTC_ILR |= ILR_RTCALF; - RTC_AMR = 0xff; // disable alarm irq - DEBUG("Ring\n"); - lpm_end_awake(); - } - - VICVectAddr = 0; // Acknowledge Interrupt + lpm_begin_awake(); + + if(RTC_ILR & ILR_RTSSF) { + /* sub second interrupt (does not need flag-clearing) */ + + } + else if(RTC_ILR & ILR_RTCCIF) { + /* counter increase interrupt */ + RTC_ILR |= ILR_RTCCIF; + epoch += 60 * 60; /* add 1 hour */ + + } + else if(RTC_ILR & ILR_RTCALF) { + RTC_ILR |= ILR_RTCALF; + RTC_AMR = 0xff; /* disable alarm irq */ + DEBUG("Ring\n"); + lpm_end_awake(); + } + + VICVectAddr = 0; /* Acknowledge Interrupt */ } /*---------------------------------------------------------------------------*/ void rtc_enable(void) { - RTC_ILR = (ILR_RTSSF | ILR_RTCCIF | ILR_RTCALF); // clear interrupt flags - RTC_CCR |= CCR_CLKEN; // enable clock - install_irq(RTC_INT, &RTC_IRQHandler, IRQP_RTC); // install interrupt handler + RTC_ILR = (ILR_RTSSF | ILR_RTCCIF | ILR_RTCALF); /* clear interrupt flags */ + RTC_CCR |= CCR_CLKEN; /* enable clock */ + install_irq(RTC_INT, &RTC_IRQHandler, IRQP_RTC); /* install interrupt handler */ - time_t now = rtc_time(NULL); - epoch = now - (now % 3600); + time_t now = rtc_time(NULL); + epoch = now - (now % 3600); } /*---------------------------------------------------------------------------*/ void rtc_init(void) { - PCONP |= BIT9; - RTC_AMR = 0xff; // disable alarm irq - RTC_CIIR = IMHOUR; // enable increase irq - RTC_CISS = 0; // disable subsecond irq + PCONP |= BIT9; + RTC_AMR = 0xff; /* disable alarm irq */ + RTC_CIIR = IMHOUR; /* enable increase irq */ + RTC_CISS = 0; /* disable subsecond irq */ - INTWAKE |= BIT15; // rtc irq wakes up mcu from power down + INTWAKE |= BIT15; /* rtc irq wakes up mcu from power down */ - RTC_CCR = CCR_CLKSRC; // Clock from external 32 kHz Osc. + RTC_CCR = CCR_CLKSRC; /* Clock from external 32 kHz Osc. */ - /* initialize clock with valid unix compatible values - * If RTC_YEAR contains an value larger unix time_t we must reset. */ - if( RTC_YEAR > 2037 ) { - rtc_reset(); - } + /* initialize clock with valid unix compatible values + * If RTC_YEAR contains an value larger unix time_t we must reset. */ + if(RTC_YEAR > 2037) { + rtc_reset(); + } - DEBUG("%2lu.%2lu.%4lu %2lu:%2lu:%2lu epoch %lu\n", - RTC_DOM, RTC_MONTH, RTC_YEAR, RTC_HOUR, RTC_MIN, RTC_SEC, - epoch); + DEBUG("%2lu.%2lu.%4lu %2lu:%2lu:%2lu epoch %lu\n", + RTC_DOM, RTC_MONTH, RTC_YEAR, RTC_HOUR, RTC_MIN, RTC_SEC, + epoch); } /*---------------------------------------------------------------------------*/ -time_t rtc_time(struct timeval* time) +time_t rtc_time(struct timeval *time) { - uint32_t sec; - uint32_t usec; - uint32_t min; - - usec = (RTC_CTC >> 1); - sec = RTC_SEC; - min = RTC_MIN; - while (usec != (RTC_CTC>>1) ) { - usec = (RTC_CTC >> 1); - sec = RTC_SEC; - min = RTC_MIN; - } - - sec += min * 60; // add number of minutes - sec += epoch; // add precalculated epoch in hour granularity - - if( time != NULL ) { - usec = usec * 15625; - usec >>= 9; - time->tv_sec = sec; - time->tv_usec = usec; - } - - return sec; + uint32_t sec; + uint32_t usec; + uint32_t min; + + usec = (RTC_CTC >> 1); + sec = RTC_SEC; + min = RTC_MIN; + + while(usec != (RTC_CTC >> 1)) { + usec = (RTC_CTC >> 1); + sec = RTC_SEC; + min = RTC_MIN; + } + + sec += min * 60; /* add number of minutes */ + sec += epoch; /* add precalculated epoch in hour granularity */ + + if(time != NULL) { + usec = usec * 15625; + usec >>= 9; + time->tv_sec = sec; + time->tv_usec = usec; + } + + return sec; } /*---------------------------------------------------------------------------*/ void rtc_disable(void) { - RTC_CCR &= ~CCR_CLKEN; // disable clock - install_irq(RTC_INT, NULL, 0); - RTC_ILR = 0; + RTC_CCR &= ~CCR_CLKEN; /* disable clock */ + install_irq(RTC_INT, NULL, 0); + RTC_ILR = 0; } /*---------------------------------------------------------------------------*/ void -rtc_get_localtime(struct tm* localt) +rtc_get_localtime(struct tm *localt) { - if( localt != NULL ) { - localt->tm_sec = RTC_SEC; - localt->tm_min = RTC_MIN; - localt->tm_hour = RTC_HOUR; - localt->tm_mday = RTC_DOM; - localt->tm_wday = RTC_DOW; - localt->tm_yday = RTC_DOY; - localt->tm_mon = RTC_MONTH - 1; - localt->tm_year = RTC_YEAR; - localt->tm_isdst = -1; // not available - } + if(localt != NULL) { + localt->tm_sec = RTC_SEC; + localt->tm_min = RTC_MIN; + localt->tm_hour = RTC_HOUR; + localt->tm_mday = RTC_DOM; + localt->tm_wday = RTC_DOW; + localt->tm_yday = RTC_DOY; + localt->tm_mon = RTC_MONTH - 1; + localt->tm_year = RTC_YEAR; + localt->tm_isdst = -1; /* not available */ + } } /*---------------------------------------------------------------------------*/ void gettimeofday_r(struct _reent *r, struct timeval *ptimeval, struct timezone *ptimezone) { - r->_errno = 0; - if( ptimeval != NULL ) { - rtc_time(ptimeval); - } + r->_errno = 0; + + if(ptimeval != NULL) { + rtc_time(ptimeval); + } } diff --git a/cpu/msp430-common/atomic.c b/cpu/msp430-common/atomic.c index 59b7ed5d7..61aa1b7db 100644 --- a/cpu/msp430-common/atomic.c +++ b/cpu/msp430-common/atomic.c @@ -1,7 +1,8 @@ #include #include -unsigned int atomic_set_return(unsigned int* val, unsigned int set) { +unsigned int atomic_set_return(unsigned int *val, unsigned int set) +{ dINT(); unsigned int old_val = *val; *val = set; diff --git a/cpu/msp430-common/cpu.c b/cpu/msp430-common/cpu.c index 0256482fb..3f5867b2f 100644 --- a/cpu/msp430-common/cpu.c +++ b/cpu/msp430-common/cpu.c @@ -10,9 +10,9 @@ This file subject to the terms and conditions of the GNU Lesser General Public License. See the file LICENSE in the top level directory for more details. *******************************************************************************/ #ifdef CC430 - #include +#include #else - #include +#include #endif #include "cpu.h" #include "kernel.h" @@ -23,9 +23,10 @@ volatile int __inISR = 0; char __isr_stack[MSP430_ISR_STACK_SIZE]; -void thread_yield() { +void thread_yield() +{ __save_context(); - + dINT(); /* have active_thread point to the next thread */ sched_run(); @@ -34,49 +35,8 @@ void thread_yield() { __restore_context(); } -// static void __resume_context () { -// __asm__("mov.w %0,r1" : : "m" (active_thread->sp)); -// -// __asm__("pop r15"); -// __asm__("pop r14"); -// __asm__("pop r13"); -// __asm__("pop r12"); -// __asm__("pop r11"); -// __asm__("pop r10"); -// __asm__("pop r9"); -// __asm__("pop r8"); -// __asm__("pop r7"); -// __asm__("pop r6"); -// __asm__("pop r5"); -// __asm__("pop r4"); -// } - - -// static void __resume_ -// -// } -// -// void __save_context_isr () { -// __asm__("push r4"); -// __asm__("push r5"); -// __asm__("push r6"); -// __asm__("push r7"); -// __asm__("push r8"); -// __asm__("push r9"); -// __asm__("push r10"); -// __asm__("push r11"); -// __asm__("push r12"); -// __asm__("push r13"); -// __asm__("push r14"); -// __asm__("push r15"); -// -// __asm__("mov.w r1,%0" : "=r" (active_thread->sp)); -// } -// -// -// __return_from_isr - -void cpu_switch_context_exit(void){ +void cpu_switch_context_exit(void) +{ active_thread = sched_threads[0]; sched_run(); @@ -88,30 +48,32 @@ void cpu_switch_context_exit(void){ //---------------------------------------------------------------------------- char *thread_stack_init(void *task_func, void *stack_start, int stack_size) { - unsigned short * stk; - stk = (unsigned short *) (stack_start + stack_size); + unsigned short *stk; + stk = (unsigned short *)(stack_start + stack_size); *stk = (unsigned short) sched_task_exit; --stk; *stk = (unsigned short) task_func; --stk; - + /* initial value for SR */ -// unsigned int sr; -// __asm__("mov.w r2,%0" : "=r" (sr)); *stk = GIE; --stk; /* Space for registers. */ - for (unsigned int i = 15; i > 4; i--) { + for(unsigned int i = 15; i > 4; i--) { *stk = i; --stk; } + //stk -= 11; - return (char*) stk; + return (char *) stk; } -int inISR() { return __inISR; } +int inISR() +{ + return __inISR; +} diff --git a/cpu/msp430-common/flashrom.c b/cpu/msp430-common/flashrom.c index 686e0cc3d..8b4db0b09 100644 --- a/cpu/msp430-common/flashrom.c +++ b/cpu/msp430-common/flashrom.c @@ -10,38 +10,44 @@ static void finish(uint8_t istate); static inline void busy_wait(void); /*---------------------------------------------------------------------------*/ -uint8_t flashrom_erase(uint8_t *addr) { +uint8_t flashrom_erase(uint8_t *addr) +{ uint8_t istate = prepare(); FCTL3 = FWKEY; /* Lock = 0 */ busy_wait(); - FCTL1 = FWKEY | ERASE; - *addr = 0; /* erase Flash segment */ + FCTL1 = FWKEY | ERASE; + *addr = 0; /* erase Flash segment */ busy_wait(); FCTL1 = FWKEY; /* ERASE = 0 */ - FCTL3 = FWKEY | LOCK; + FCTL3 = FWKEY | LOCK; finish(istate); return 1; } -void flashrom_write(uint8_t *dst, uint8_t *src, size_t size) { +void flashrom_write(uint8_t *dst, uint8_t *src, size_t size) +{ unsigned int i; FCTL3 = FWKEY; /* Lock = 0 */ busy_wait(); - for (i = size; i > 0; i--) { + + for(i = size; i > 0; i--) { FCTL1 = FWKEY | WRT; *dst = *src; /* program Flash word */ - while (!(FCTL3 & WAIT)) { + + while(!(FCTL3 & WAIT)) { nop(); } } + busy_wait(); FCTL1 = FWKEY; /* WRT = 0 */ FCTL3 = FWKEY | LOCK; /* Lock = 1 */ } /*---------------------------------------------------------------------------*/ -static uint8_t prepare(void) { +static uint8_t prepare(void) +{ uint8_t istate; /* Disable all interrupts. */ @@ -51,7 +57,7 @@ static uint8_t prepare(void) { /* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz select SMCLK for flash timing, divider 4+1 */ - FCTL2 = FWKEY | FSSEL_3 | FN2 | FN0; + FCTL2 = FWKEY | FSSEL_3 | FN2 | FN0; /* disable all interrupts to protect CPU during programming from system crash */ @@ -60,19 +66,21 @@ static uint8_t prepare(void) { /* disable all NMI-Interrupt sources */ ie1 = IE1; ie2 = IE2; - IE1 = 0x00; + IE1 = 0x00; IE2 = 0x00; return istate; } /*---------------------------------------------------------------------------*/ -void finish(uint8_t istate) { - /* Enable interrupts. */ - IE1 = ie1; - IE2 = ie2; - restoreIRQ(istate); +void finish(uint8_t istate) +{ + /* Enable interrupts. */ + IE1 = ie1; + IE2 = ie2; + restoreIRQ(istate); } -static inline void busy_wait(void) { +static inline void busy_wait(void) +{ /* Wait for BUSY = 0, not needed unless run from RAM */ while(FCTL3 & 0x0001) { nop(); diff --git a/cpu/msp430-common/hwtimer_cpu.c b/cpu/msp430-common/hwtimer_cpu.c index 013dca20f..0a7ae53ff 100644 --- a/cpu/msp430-common/hwtimer_cpu.c +++ b/cpu/msp430-common/hwtimer_cpu.c @@ -23,65 +23,77 @@ License. See the file LICENSE in the top level directory for more details. void (*int_handler)(int); extern void timerA_init(void); -static void TA0_disable_interrupt(short timer) { +static void TA0_disable_interrupt(short timer) +{ volatile unsigned int *ptr = &TA0CCTL0 + (timer); *ptr &= ~(CCIFG); *ptr &= ~(CCIE); } -static void TA0_enable_interrupt(short timer) { +static void TA0_enable_interrupt(short timer) +{ volatile unsigned int *ptr = &TA0CCTL0 + (timer); *ptr |= CCIE; *ptr &= ~(CCIFG); } -static void TA0_set_nostart(unsigned long value, short timer) { +static void TA0_set_nostart(unsigned long value, short timer) +{ volatile unsigned int *ptr = &TA0CCR0 + (timer); *ptr = value; } -static void TA0_set(unsigned long value, short timer) { +static void TA0_set(unsigned long value, short timer) +{ DEBUG("Setting timer %u to %lu\n", timer, value); TA0_set_nostart(value, timer); TA0_enable_interrupt(timer); } -void TA0_unset(short timer) { +void TA0_unset(short timer) +{ volatile unsigned int *ptr = &TA0CCR0 + (timer); TA0_disable_interrupt(timer); *ptr = 0; } -unsigned long hwtimer_arch_now() { - return TA0R; +unsigned long hwtimer_arch_now() +{ + return TA0R; } -void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) { +void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) +{ timerA_init(); int_handler = handler; } -void hwtimer_arch_enable_interrupt(void) { - for (int i = 0; i < ARCH_MAXTIMERS; i++) { +void hwtimer_arch_enable_interrupt(void) +{ + for(int i = 0; i < ARCH_MAXTIMERS; i++) { TA0_enable_interrupt(i); } } -void hwtimer_arch_disable_interrupt(void) { - for (int i = 0; i < ARCH_MAXTIMERS; i++) { +void hwtimer_arch_disable_interrupt(void) +{ + for(int i = 0; i < ARCH_MAXTIMERS; i++) { TA0_disable_interrupt(i); } } -void hwtimer_arch_set(unsigned long offset, short timer) { +void hwtimer_arch_set(unsigned long offset, short timer) +{ unsigned int value = hwtimer_arch_now() + offset; hwtimer_arch_set_absolute(value, timer); } -void hwtimer_arch_set_absolute(unsigned long value, short timer) { - TA0_set(value,timer); +void hwtimer_arch_set_absolute(unsigned long value, short timer) +{ + TA0_set(value, timer); } -void hwtimer_arch_unset(short timer) { +void hwtimer_arch_unset(short timer) +{ TA0_unset(timer); } diff --git a/cpu/msp430-common/include/cpu.h b/cpu/msp430-common/include/cpu.h index b44c902c1..813f6a06f 100644 --- a/cpu/msp430-common/include/cpu.h +++ b/cpu/msp430-common/include/cpu.h @@ -39,7 +39,8 @@ extern char __isr_stack[MSP430_ISR_STACK_SIZE]; //#define eINT() eint() //#define dINT() dint() -inline void __save_context_isr(void) { +inline void __save_context_isr(void) +{ __asm__("push r15"); __asm__("push r14"); __asm__("push r13"); @@ -53,11 +54,12 @@ inline void __save_context_isr(void) { __asm__("push r5"); __asm__("push r4"); - __asm__("mov.w r1,%0" : "=r" (active_thread->sp)); + __asm__("mov.w r1,%0" : "=r"(active_thread->sp)); } -inline void __restore_context_isr(void) { - __asm__("mov.w %0,r1" : : "m" (active_thread->sp)); +inline void __restore_context_isr(void) +{ + __asm__("mov.w %0,r1" : : "m"(active_thread->sp)); __asm__("pop r4"); __asm__("pop r5"); @@ -73,36 +75,46 @@ inline void __restore_context_isr(void) { __asm__("pop r15"); } -inline void __enter_isr(void) { +inline void __enter_isr(void) +{ __save_context_isr(); - __asm__("mov.w %0,r1" : : "i" (__isr_stack+MSP430_ISR_STACK_SIZE)); + __asm__("mov.w %0,r1" : : "i"(__isr_stack+MSP430_ISR_STACK_SIZE)); __inISR = 1; } -inline void __exit_isr(void) { +inline void __exit_isr(void) +{ __inISR = 0; - if (sched_context_switch_request) sched_run(); + + if(sched_context_switch_request) { + sched_run(); + } + __restore_context_isr(); __asm__("reti"); } -inline void __save_context(void) { +inline void __save_context(void) +{ __asm__("push r2"); /* save SR */ __save_context_isr(); } -inline void __restore_context(void) { +inline void __restore_context(void) +{ __restore_context_isr(); __asm__("reti"); } -inline void eINT(void) { -// puts("+"); +inline void eINT(void) +{ + // puts("+"); eint(); } -inline void dINT(void) { -// puts("-"); +inline void dINT(void) +{ + // puts("-"); dint(); } diff --git a/cpu/msp430-common/include/hwtimer_cpu.h b/cpu/msp430-common/include/hwtimer_cpu.h index 92f53abe0..872b58430 100644 --- a/cpu/msp430-common/include/hwtimer_cpu.h +++ b/cpu/msp430-common/include/hwtimer_cpu.h @@ -14,9 +14,9 @@ License. See the file LICENSE in the top level directory for more details. #define __HWTIMER_CPU_H #ifdef CC430 - #include +#include #else - #include +#include #endif #include diff --git a/cpu/msp430-common/include/malloc.h b/cpu/msp430-common/include/malloc.h index 2ab076c6a..b0b811c66 100644 --- a/cpu/msp430-common/include/malloc.h +++ b/cpu/msp430-common/include/malloc.h @@ -1,5 +1,5 @@ #ifndef __MALLOC_H -#define __MALLOC_H +#define __MALLOC_H #include "oneway_malloc.h" diff --git a/cpu/msp430-common/include/time.h b/cpu/msp430-common/include/time.h index 97bf471f4..5969cd029 100644 --- a/cpu/msp430-common/include/time.h +++ b/cpu/msp430-common/include/time.h @@ -1,15 +1,14 @@ #ifndef MSPGCC_TIME_H #define MSPGCC_TIME_H -struct tm -{ - int tm_sec; // Seconds after the minute [0, 59] - int tm_min; // Minutes after the hour [0, 59] - int tm_hour; // Hours since midnight [0, 23] - int tm_mday; // Day of the month [1, 31] - int tm_mon; // Months since January [0, 11] - int tm_year; // Years since 1900 - int tm_wday; // Days since Sunday [0, 6] +struct tm { + int tm_sec; /* Seconds after the minute [0, 59] */ + int tm_min; /* Minutes after the hour [0, 59] */ + int tm_hour; /* Hours since midnight [0, 23] */ + int tm_mday; /* Day of the month [1, 31] */ + int tm_mon; /* Months since January [0, 11] */ + int tm_year; /* Years since 1900 */ + int tm_wday; /* Days since Sunday [0, 6] */ }; #endif diff --git a/cpu/msp430-common/irq.c b/cpu/msp430-common/irq.c index 8a31d913d..ac1de2735 100644 --- a/cpu/msp430-common/irq.c +++ b/cpu/msp430-common/irq.c @@ -1,28 +1,41 @@ #include #ifdef CC430 - #include +#include #else - #include +#include #endif #include -unsigned int disableIRQ() { +unsigned int disableIRQ() +{ unsigned int state; - __asm__("mov.w r2,%0" : "=r" (state)); + __asm__("mov.w r2,%0" : "=r"(state)); state &= GIE; - if (state) dINT(); + + if(state) { + dINT(); + } + return state; } -unsigned int enableIRQ() { +unsigned int enableIRQ() +{ unsigned int state; - __asm__("mov.w r2,%0" : "=r" (state)); + __asm__("mov.w r2,%0" : "=r"(state)); state &= GIE; - if (!state) eINT(); + + if(!state) { + eINT(); + } + return state; } -void restoreIRQ(unsigned int state) { - if (state) eINT(); +void restoreIRQ(unsigned int state) +{ + if(state) { + eINT(); + } } diff --git a/cpu/msp430-common/msp430-main.c b/cpu/msp430-common/msp430-main.c index 969094c9c..49ae3d5a4 100644 --- a/cpu/msp430-common/msp430-main.c +++ b/cpu/msp430-common/msp430-main.c @@ -35,9 +35,9 @@ #include "cpu.h" #ifdef CC430 - #include +#include #else - #include +#include #endif #include "msp430.h" @@ -46,76 +46,76 @@ static void init_ports(void) { - /* Turn everything off, device drivers enable what is needed. */ + /* Turn everything off, device drivers enable what is needed. */ - /* All configured for digital I/O */ + /* All configured for digital I/O */ #ifdef P1SEL - P1SEL = 0; + P1SEL = 0; #endif #ifdef P2SEL - P2SEL = 0; + P2SEL = 0; #endif #ifdef P3SEL - P3SEL = 0; + P3SEL = 0; #endif #ifdef P4SEL - P4SEL = 0; + P4SEL = 0; #endif #ifdef P5SEL - P5SEL = 0; + P5SEL = 0; #endif #ifdef P6SEL - P6SEL = 0; + P6SEL = 0; #endif - /* All available inputs */ + /* All available inputs */ #ifdef P1DIR - P1DIR = 0; - P1OUT = 0; + P1DIR = 0; + P1OUT = 0; #endif #ifdef P2DIR - P2DIR = 0; - P2OUT = 0; + P2DIR = 0; + P2OUT = 0; #endif #ifdef P3DIR - P3DIR = 0; - P3OUT = 0; + P3DIR = 0; + P3OUT = 0; #endif #ifdef P4DIR - P4DIR = 0; - P4OUT = 0; + P4DIR = 0; + P4OUT = 0; #endif #ifdef P5DIR - P5DIR = 0; - P5OUT = 0; + P5DIR = 0; + P5OUT = 0; #endif #ifdef P6DIR - P6DIR = 0; - P6OUT = 0; + P6DIR = 0; + P6OUT = 0; #endif - P1IE = 0; - P2IE = 0; + P1IE = 0; + P2IE = 0; } /*---------------------------------------------------------------------------*/ /* msp430-ld may align _end incorrectly. Workaround in cpu_init. */ extern int _end; /* Not in sys/unistd.h */ -static char *cur_break = (char *)&_end; +static char *cur_break = (char *) &_end; void msp430_cpu_init(void) { - dint(); - init_ports(); -// lpm_init(); - eint(); - - if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */ - cur_break++; - } + dint(); + init_ports(); + // lpm_init(); + eint(); + + if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */ + cur_break++; + } } /*---------------------------------------------------------------------------*/ #define asmv(arg) __asm__ __volatile__(arg) @@ -131,20 +131,22 @@ msp430_cpu_init(void) */ void *sbrk(int incr) { - char *stack_pointer; - - asmv("mov r1, %0" : "=r" (stack_pointer)); - stack_pointer -= STACK_EXTRA; - if(incr > (stack_pointer - cur_break)) - return (void *)-1; /* ENOMEM */ - - void *old_break = cur_break; - cur_break += incr; - /* - * If the stack was never here then [old_break .. cur_break] should - * be filled with zeros. - */ - return old_break; + char *stack_pointer; + + asmv("mov r1, %0" : "=r"(stack_pointer)); + stack_pointer -= STACK_EXTRA; + + if(incr > (stack_pointer - cur_break)) { + return (void *) - 1; /* ENOMEM */ + } + + void *old_break = cur_break; + cur_break += incr; + /* + * If the stack was never here then [old_break .. cur_break] should + * be filled with zeros. + */ + return old_break; } /*---------------------------------------------------------------------------*/ /* @@ -153,11 +155,11 @@ void *sbrk(int incr) int splhigh_(void) { - /* Clear the GIE (General Interrupt Enable) flag. */ - int sr; - asmv("mov r2, %0" : "=r" (sr)); - asmv("bic %0, r2" : : "i" (GIE)); - return sr & GIE; /* Ignore other sr bits. */ + /* Clear the GIE (General Interrupt Enable) flag. */ + int sr; + asmv("mov r2, %0" : "=r"(sr)); + asmv("bic %0, r2" : : "i"(GIE)); + return sr & GIE; /* Ignore other sr bits. */ } /*---------------------------------------------------------------------------*/ /* @@ -166,8 +168,8 @@ splhigh_(void) void splx_(int sr) { - /* If GIE was set, restore it. */ - asmv("bis %0, r2" : : "r" (sr)); + /* If GIE was set, restore it. */ + asmv("bis %0, r2" : : "r"(sr)); } /*---------------------------------------------------------------------------*/ diff --git a/cpu/msp430-common/startup.c b/cpu/msp430-common/startup.c index bad3bb95c..aa95ea72f 100644 --- a/cpu/msp430-common/startup.c +++ b/cpu/msp430-common/startup.c @@ -3,7 +3,8 @@ extern void board_init(void); -__attribute__ ((constructor)) static void startup(void) { +__attribute__((constructor)) static void startup(void) +{ /* use putchar so the linker links it in: */ putchar('\n'); diff --git a/cpu/msp430x16x/flashrom.c b/cpu/msp430x16x/flashrom.c index 686e0cc3d..92661c5cc 100644 --- a/cpu/msp430x16x/flashrom.c +++ b/cpu/msp430x16x/flashrom.c @@ -10,38 +10,44 @@ static void finish(uint8_t istate); static inline void busy_wait(void); /*---------------------------------------------------------------------------*/ -uint8_t flashrom_erase(uint8_t *addr) { +uint8_t flashrom_erase(uint8_t *addr) +{ uint8_t istate = prepare(); FCTL3 = FWKEY; /* Lock = 0 */ busy_wait(); - FCTL1 = FWKEY | ERASE; + FCTL1 = FWKEY | ERASE; *addr = 0; /* erase Flash segment */ busy_wait(); FCTL1 = FWKEY; /* ERASE = 0 */ - FCTL3 = FWKEY | LOCK; + FCTL3 = FWKEY | LOCK; finish(istate); return 1; } -void flashrom_write(uint8_t *dst, uint8_t *src, size_t size) { +void flashrom_write(uint8_t *dst, uint8_t *src, size_t size) +{ unsigned int i; FCTL3 = FWKEY; /* Lock = 0 */ busy_wait(); - for (i = size; i > 0; i--) { + + for(i = size; i > 0; i--) { FCTL1 = FWKEY | WRT; *dst = *src; /* program Flash word */ - while (!(FCTL3 & WAIT)) { + + while(!(FCTL3 & WAIT)) { nop(); } } + busy_wait(); FCTL1 = FWKEY; /* WRT = 0 */ FCTL3 = FWKEY | LOCK; /* Lock = 1 */ } /*---------------------------------------------------------------------------*/ -static uint8_t prepare(void) { +static uint8_t prepare(void) +{ uint8_t istate; /* Disable all interrupts. */ @@ -51,7 +57,7 @@ static uint8_t prepare(void) { /* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz select SMCLK for flash timing, divider 4+1 */ - FCTL2 = FWKEY | FSSEL_3 | FN2 | FN0; + FCTL2 = FWKEY | FSSEL_3 | FN2 | FN0; /* disable all interrupts to protect CPU during programming from system crash */ @@ -60,19 +66,21 @@ static uint8_t prepare(void) { /* disable all NMI-Interrupt sources */ ie1 = IE1; ie2 = IE2; - IE1 = 0x00; + IE1 = 0x00; IE2 = 0x00; return istate; } /*---------------------------------------------------------------------------*/ -void finish(uint8_t istate) { - /* Enable interrupts. */ - IE1 = ie1; - IE2 = ie2; - restoreIRQ(istate); +void finish(uint8_t istate) +{ + /* Enable interrupts. */ + IE1 = ie1; + IE2 = ie2; + restoreIRQ(istate); } -static inline void busy_wait(void) { +static inline void busy_wait(void) +{ /* Wait for BUSY = 0, not needed unless run from RAM */ while(FCTL3 & 0x0001) { nop(); diff --git a/cpu/msp430x16x/hwtimer_msp430.c b/cpu/msp430x16x/hwtimer_msp430.c index 69326bd69..8721cf3b9 100644 --- a/cpu/msp430x16x/hwtimer_msp430.c +++ b/cpu/msp430x16x/hwtimer_msp430.c @@ -10,45 +10,49 @@ extern void TA0_unset(short timer); void timerA_init(void) { - ticks = 0; // Set tick counter value to 0 - TA0CTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK - TA0CTL &= ~TAIFG; // Clear the IFG - TA0CTL &= ~TAIE; // Clear the IFG + ticks = 0; // Set tick counter value to 0 + TA0CTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK + TA0CTL &= ~TAIFG; // Clear the IFG + TA0CTL &= ~TAIE; // Clear the IFG volatile unsigned int *ccr = &TA0CCR0; volatile unsigned int *ctl = &TA0CCTL0; - for (int i = 0; i < ARCH_MAXTIMERS; i++) { + for(int i = 0; i < ARCH_MAXTIMERS; i++) { *ccr = 0; *ctl &= ~(CCIFG); *ctl &= ~(CCIE); } + ITA0CTL |= MC_2; } -interrupt(TIMERA0_VECTOR) __attribute__ ((naked)) timer_isr_ccr0(void) { +interrupt(TIMERA0_VECTOR) __attribute__((naked)) timer_isr_ccr0(void) +{ __enter_isr(); TA0_unset(0); int_handler(0); - + __exit_isr(); } -interrupt(TIMERA1_VECTOR) __attribute__ ((naked)) timer_isr(void) { +interrupt(TIMERA1_VECTOR) __attribute__((naked)) timer_isr(void) +{ __enter_isr(); - + short taiv = TA0IV; - if (taiv & TAIFG) { - // puts("msp430/hwtimer_cpu TAIFG set!"); - // TA0CTL &= ~TAIFG; - // ticks += 0xFFFF; - } else { + if(taiv & TAIFG) { + // puts("msp430/hwtimer_cpu TAIFG set!"); + // TA0CTL &= ~TAIFG; + // ticks += 0xFFFF; + } + else { - short timer = (taiv/2); + short timer = (taiv / 2); TA0_unset(timer); int_handler(timer); } - + __exit_isr(); } diff --git a/cpu/native/atomic_cpu.c b/cpu/native/atomic_cpu.c index bbe793dc2..289e7e71a 100644 --- a/cpu/native/atomic_cpu.c +++ b/cpu/native/atomic_cpu.c @@ -18,7 +18,7 @@ #include #include -unsigned int atomic_set_return(unsigned int* val, unsigned int set) +unsigned int atomic_set_return(unsigned int *val, unsigned int set) { unsigned int old_val; unsigned int old_state; diff --git a/cpu/native/cc110x_ng/cc110x_ng_cpu.c b/cpu/native/cc110x_ng/cc110x_ng_cpu.c index bb04e2a29..2b6415938 100644 --- a/cpu/native/cc110x_ng/cc110x_ng_cpu.c +++ b/cpu/native/cc110x_ng/cc110x_ng_cpu.c @@ -27,7 +27,8 @@ static uint8_t native_cc110x_ssp0dr; uint8_t cc110x_txrx(uint8_t c) { native_cc110x_ssp0dr = c; - switch (c) { + + switch(c) { case CC1100_READ_BURST: case CC1100_WRITE_BURST: case CC1100_READ_SINGLE: @@ -35,6 +36,7 @@ uint8_t cc110x_txrx(uint8_t c) default: warnx("cc110x_txrx (%i): not implemented", c); } + DEBUG("cc110x_txrx\n"); return native_cc110x_ssp0dr; } diff --git a/cpu/native/hwtimer_cpu.c b/cpu/native/hwtimer_cpu.c index a4137075e..e9dbf345d 100644 --- a/cpu/native/hwtimer_cpu.c +++ b/cpu/native/hwtimer_cpu.c @@ -56,8 +56,8 @@ static void (*int_handler)(int); */ void ticks2tv(unsigned long ticks, struct timeval *tp) { - tp->tv_sec = ticks / HWTIMER_SPEED; - tp->tv_usec = (ticks % HWTIMER_SPEED) ; + tp->tv_sec = ticks / HWTIMER_SPEED; + tp->tv_usec = (ticks % HWTIMER_SPEED) ; } /** @@ -75,7 +75,7 @@ unsigned long tv2ticks(struct timeval *tp) unsigned long ts2ticks(struct timespec *tp) { /* TODO: check for overflow */ - return((tp->tv_sec * HWTIMER_SPEED) + (tp->tv_nsec/1000)); + return((tp->tv_sec * HWTIMER_SPEED) + (tp->tv_nsec / 1000)); } /** @@ -84,34 +84,35 @@ unsigned long ts2ticks(struct timespec *tp) void schedule_timer(void) { int l = next_timer; - for ( - int i = ((next_timer +1) % ARCH_MAXTIMERS); - i != next_timer; - i = ((i+1) % ARCH_MAXTIMERS) - ) - { - - if ( native_hwtimer_isset[l] != 1 ) { + + for( + int i = ((next_timer + 1) % ARCH_MAXTIMERS); + i != next_timer; + i = ((i + 1) % ARCH_MAXTIMERS) + ) { + + if(native_hwtimer_isset[l] != 1) { /* make sure we dont compare to garbage in the following * if condition */ l = i; } - if ( - ( native_hwtimer_isset[i] == 1 ) && - ( tv2ticks(&(native_hwtimer[i].it_value)) < tv2ticks(&(native_hwtimer[l].it_value)) ) - ) - { + if( + (native_hwtimer_isset[i] == 1) && + (tv2ticks(&(native_hwtimer[i].it_value)) < tv2ticks(&(native_hwtimer[l].it_value))) + ) { /* set l to the lowest active time */ l = i; } } + next_timer = l; + /* l could still point to some unused (garbage) timer if no timers * are set at all */ - if (native_hwtimer_isset[next_timer] == 1) { - if (setitimer(ITIMER_REAL, &native_hwtimer[next_timer], NULL) == -1) { + if(native_hwtimer_isset[next_timer] == 1) { + if(setitimer(ITIMER_REAL, &native_hwtimer[next_timer], NULL) == -1) { err(1, "schedule_timer"); } else { @@ -126,7 +127,7 @@ void schedule_timer(void) /** * native timer signal handler - * + * * set new system timer, call timer interrupt handler */ void hwtimer_isr_timer() @@ -139,7 +140,7 @@ void hwtimer_isr_timer() native_hwtimer_isset[next_timer] = 0; schedule_timer(); - if (native_hwtimer_irq[i] == 1) { + if(native_hwtimer_irq[i] == 1) { DEBUG("hwtimer_isr_timer(): calling hwtimer.int_handler(%i)\n", i); int_handler(i); } @@ -151,18 +152,22 @@ void hwtimer_isr_timer() void hwtimer_arch_enable_interrupt(void) { DEBUG("hwtimer_arch_enable_interrupt()\n"); - if (register_interrupt(SIGALRM, hwtimer_isr_timer) != 0) { + + if(register_interrupt(SIGALRM, hwtimer_isr_timer) != 0) { DEBUG("darn!\n\n"); } + return; } void hwtimer_arch_disable_interrupt(void) { DEBUG("hwtimer_arch_disable_interrupt()\n"); - if (unregister_interrupt(SIGALRM) != 0) { + + if(unregister_interrupt(SIGALRM) != 0) { DEBUG("darn!\n\n"); } + return; } @@ -180,17 +185,19 @@ void hwtimer_arch_unset(short timer) void hwtimer_arch_set(unsigned long offset, short timer) { DEBUG("hwtimer_arch_set(%li, %i)\n", offset, timer); - if (offset < HWTIMERMINOFFSET) { + + if(offset < HWTIMERMINOFFSET) { offset = HWTIMERMINOFFSET; DEBUG("hwtimer_arch_set: offset < MIN, set to: %i\n", offset); } + native_hwtimer_irq[timer] = 1; native_hwtimer_isset[timer] = 1; ticks2tv(offset, &(native_hwtimer[timer].it_value)); DEBUG("hwtimer_arch_set(): that is %lis %lius from now\n", - native_hwtimer[timer].it_value.tv_sec, - native_hwtimer[timer].it_value.tv_usec); + native_hwtimer[timer].it_value.tv_sec, + native_hwtimer[timer].it_value.tv_usec); schedule_timer(); @@ -210,7 +217,7 @@ unsigned long hwtimer_arch_now(void) DEBUG("hwtimer_arch_now()\n"); -#ifdef __MACH__ +#ifdef __MACH__ clock_serv_t cclock; mach_timespec_t mts; host_get_clock_service(mach_host_self(), SYSTEM_CLOCK, &cclock); @@ -219,9 +226,11 @@ unsigned long hwtimer_arch_now(void) t.tv_sec = mts.tv_sec; t.tv_nsec = mts.tv_nsec; #else - if (clock_gettime(CLOCK_MONOTONIC, &t) == -1) { + + if(clock_gettime(CLOCK_MONOTONIC, &t) == -1) { err(1, "hwtimer_arch_now: clock_gettime"); } + #endif native_hwtimer_now = ts2ticks(&t); @@ -238,7 +247,7 @@ void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) hwtimer_arch_disable_interrupt(); int_handler = handler; - for (int i = 0; iuc_sigmask; - if (sigemptyset(p) == -1) { + + if(sigemptyset(p) == -1) { err(1, "print_thread_sigmask: sigemptyset"); } - for (int i = 1; i<(NSIG); i++) { - if (native_irq_handlers[i].func != NULL) { + for(int i = 1; i < (NSIG); i++) { + if(native_irq_handlers[i].func != NULL) { printf("%s: %s\n", - strsignal(i), - (sigismember(&native_sig_set, i) ? "blocked": "unblocked") + strsignal(i), + (sigismember(&native_sig_set, i) ? "blocked" : "unblocked") ); } - if (sigismember(p, i)) { + + if(sigismember(p, i)) { printf("%s: pending\n", strsignal(i)); } } @@ -74,11 +76,11 @@ void print_sigmasks(void) ucontext_t *p; //tcb_t *cb = NULL; - for (int i=0; iname); //print_thread_sigmask(sched_threads[i]->sp); - p = (ucontext_t*)(sched_threads[i]->stack_start); + p = (ucontext_t *)(sched_threads[i]->stack_start); print_thread_sigmask(p); puts(""); } @@ -89,27 +91,32 @@ void native_print_signals() { sigset_t p, q; puts("native signals:\n"); - if (sigemptyset(&p) == -1) { + + if(sigemptyset(&p) == -1) { err(1, "native_print_signals: sigemptyset"); } - if (sigpending(&p) == -1) { + + if(sigpending(&p) == -1) { err(1, "native_print_signals: sigpending"); } - if (sigprocmask(SIG_SETMASK, NULL, &q) == -1) { + + if(sigprocmask(SIG_SETMASK, NULL, &q) == -1) { err(1, "native_print_signals(): sigprocmask"); } - for (int i = 1; i<(NSIG); i++) { - if (native_irq_handlers[i].func != NULL || i == SIGUSR1) { + for(int i = 1; i < (NSIG); i++) { + if(native_irq_handlers[i].func != NULL || i == SIGUSR1) { printf("%s: %s in active thread\n", - strsignal(i), - (sigismember(&native_sig_set, i) ? "blocked": "unblocked") + strsignal(i), + (sigismember(&native_sig_set, i) ? "blocked" : "unblocked") ); } - if (sigismember(&p, i)) { + + if(sigismember(&p, i)) { printf("%s: pending\n", strsignal(i)); } - if (sigismember(&q, i)) { + + if(sigismember(&q, i)) { printf("%s: blocked in this context\n", strsignal(i)); } } @@ -126,24 +133,29 @@ unsigned disableIRQ(void) _native_in_syscall = 1; DEBUG("disableIRQ()\n"); - if (sigfillset(&mask) == -1) { + if(sigfillset(&mask) == -1) { err(1, "disableIRQ(): sigfillset"); } - if (native_interrupts_enabled == 1) { + + if(native_interrupts_enabled == 1) { DEBUG("sigprocmask(..native_sig_set)\n"); - if (sigprocmask(SIG_SETMASK, &mask, &native_sig_set) == -1) { + + if(sigprocmask(SIG_SETMASK, &mask, &native_sig_set) == -1) { err(1, "disableIRQ(): sigprocmask"); } } else { DEBUG("sigprocmask()\n"); - if (sigprocmask(SIG_SETMASK, &mask, NULL) == -1) { + + if(sigprocmask(SIG_SETMASK, &mask, NULL) == -1) { err(1, "disableIRQ(): sigprocmask()"); } } + prev_state = native_interrupts_enabled; native_interrupts_enabled = 0; - if (_native_sigpend > 0) { + + if(_native_sigpend > 0) { DEBUG("\n\n\t\treturn from syscall, calling native_irq_handler\n\n"); _native_in_syscall = 0; printf("calling swapcontext()\n"); @@ -152,6 +164,7 @@ unsigned disableIRQ(void) else { _native_in_syscall = 0; } + DEBUG("disableIRQ(): return\n"); return prev_state; @@ -167,15 +180,16 @@ unsigned enableIRQ(void) _native_in_syscall = 1; DEBUG("enableIRQ()\n"); - if (sigprocmask(SIG_SETMASK, &native_sig_set, NULL) == -1) { + if(sigprocmask(SIG_SETMASK, &native_sig_set, NULL) == -1) { err(1, "enableIRQ(): sigprocmask()"); } + prev_state = native_interrupts_enabled; native_interrupts_enabled = 1; //print_sigmasks(); //native_print_signals(); - if (_native_sigpend > 0) { + if(_native_sigpend > 0) { DEBUG("\n\n\t\treturn from syscall, calling native_irq_handler\n\n"); _native_in_syscall = 0; printf("calling swapcontext()\n"); @@ -184,6 +198,7 @@ unsigned enableIRQ(void) else { _native_in_syscall = 0; } + DEBUG("enableIRQ(): return\n"); return prev_state; @@ -193,12 +208,13 @@ void restoreIRQ(unsigned state) { DEBUG("restoreIRQ()\n"); - if (state == 1) { + if(state == 1) { enableIRQ(); } else { disableIRQ(); } + return; } @@ -226,11 +242,13 @@ int _native_popsig(void) nleft = sizeof(int); i = 0; - while ((nleft>0) && ((nread = read(pipefd[0], &sig + i, nleft)) != -1)) { + + while((nleft > 0) && ((nread = read(pipefd[0], &sig + i, nleft)) != -1)) { i += nread; nleft -= nread; } - if (nread == -1) { + + if(nread == -1) { err(1, "_native_popsig(): read()"); } @@ -246,16 +264,17 @@ void native_irq_handler() int sig; DEBUG("\n\n\t\tnative_irq_handler\n\n"); - while (_native_sigpend > 0) { + + while(_native_sigpend > 0) { sig = _native_popsig(); _native_sigpend--; - if (native_irq_handlers[sig].func != NULL) { + if(native_irq_handlers[sig].func != NULL) { DEBUG("calling interrupt handler for %i\n", sig); native_irq_handlers[sig].func(); } - else if (sig == SIGUSR1) { + else if(sig == SIGUSR1) { DEBUG("ignoring SIGUSR1\n"); } else { @@ -263,6 +282,7 @@ void native_irq_handler() errx(1, "XXX: this should not have happened!\n"); } } + DEBUG("native_irq_handler(): return"); _native_in_isr = 0; cpu_switch_context_exit(); @@ -275,32 +295,34 @@ void native_irq_handler() void native_isr_entry(int sig, siginfo_t *info, void *context) { DEBUG("\n\n\t\tnative_isr_entry\n\n"); - if (native_interrupts_enabled == 0) { + + if(native_interrupts_enabled == 0) { errx(1, "interrupts are off, but I caught a signal."); } /* save the signal */ - if (write(pipefd[1], &sig, sizeof(int)) == -1) { + if(write(pipefd[1], &sig, sizeof(int)) == -1) { err(1, "native_isr_entry(): write()"); } + _native_sigpend++; /* indicate irs status */ - + makecontext(&native_isr_context, native_irq_handler, 0); - _native_cur_ctx = (ucontext_t*)active_thread->sp; + _native_cur_ctx = (ucontext_t *)active_thread->sp; - if (_native_in_syscall == 0) { + if(_native_in_syscall == 0) { _native_in_isr = 1; DEBUG("\n\n\t\treturn to _native_sig_leave_tramp\n\n"); #ifdef __MACH__ - _native_saved_eip = ((ucontext_t*)context)->uc_mcontext->__ss.__eip; - ((ucontext_t*)context)->uc_mcontext->__ss.__eip = (unsigned int)&_native_sig_leave_tramp; + _native_saved_eip = ((ucontext_t *)context)->uc_mcontext->__ss.__eip; + ((ucontext_t *)context)->uc_mcontext->__ss.__eip = (unsigned int)&_native_sig_leave_tramp; #elif BSD - _native_saved_eip = ((struct sigcontext*)context)->sc_eip; - ((struct sigcontext*)context)->sc_eip = (unsigned int)&_native_sig_leave_tramp; + _native_saved_eip = ((struct sigcontext *)context)->sc_eip; + ((struct sigcontext *)context)->sc_eip = (unsigned int)&_native_sig_leave_tramp; #else - _native_saved_eip = ((ucontext_t*)context)->uc_mcontext.gregs[REG_EIP]; - ((ucontext_t*)context)->uc_mcontext.gregs[REG_EIP] = (unsigned int)&_native_sig_leave_tramp; + _native_saved_eip = ((ucontext_t *)context)->uc_mcontext.gregs[REG_EIP]; + ((ucontext_t *)context)->uc_mcontext.gregs[REG_EIP] = (unsigned int)&_native_sig_leave_tramp; #endif // TODO: change sigmask? } @@ -321,22 +343,22 @@ int register_interrupt(int sig, void *handler) struct sigaction sa; DEBUG("XXX: register_interrupt()\n"); - if (sigdelset(&native_sig_set, sig)) { + if(sigdelset(&native_sig_set, sig)) { err(1, "register_interrupt: sigdelset"); } native_irq_handlers[sig].func = handler; - sa.sa_sigaction = (void*) native_isr_entry; + sa.sa_sigaction = (void *) native_isr_entry; /* sa.sa_handler = (void*) native_isr_entry; */ - if (sigemptyset(&sa.sa_mask) == -1) { + if(sigemptyset(&sa.sa_mask) == -1) { err(1, "register_interrupt: sigemptyset"); } sa.sa_flags = SA_RESTART | SA_SIGINFO | SA_ONSTACK; - if (sigaction(sig, &sa, NULL)) { + if(sigaction(sig, &sa, NULL)) { err(1, "register_interrupt: sigaction"); } @@ -354,21 +376,25 @@ int unregister_interrupt(int sig) struct sigaction sa; DEBUG("XXX: unregister_interrupt()\n"); - if (sigaddset(&native_sig_set, sig) == -1) { + if(sigaddset(&native_sig_set, sig) == -1) { err(1, "unregister_interrupt: sigaddset"); } + native_irq_handlers[sig].func = NULL; /* sa.sa_sigaction = SIG_IGN; */ sa.sa_handler = SIG_IGN; - if (sigemptyset(&sa.sa_mask) == -1) { + + if(sigemptyset(&sa.sa_mask) == -1) { err(1, "unregister_interrupt: sigemptyset"); } + sa.sa_flags = SA_RESTART | SA_SIGINFO | SA_ONSTACK; - if (sigaction(sig, &sa, NULL)) { + if(sigaction(sig, &sa, NULL)) { err(1, "unregister_interrupt: sigaction"); } + return 0; } @@ -387,14 +413,16 @@ void native_interrupt_init(void) native_interrupts_enabled = 1; _native_sigpend = 0; - for (int i = 0; i<255; i++) { + for(int i = 0; i < 255; i++) { native_irq_handlers[i].func = NULL; } - sa.sa_sigaction = (void*) native_isr_entry; - if (sigemptyset(&sa.sa_mask) == -1) { + sa.sa_sigaction = (void *) native_isr_entry; + + if(sigemptyset(&sa.sa_mask) == -1) { err(1, "native_interrupt_init: sigemptyset"); } + sa.sa_flags = SA_RESTART | SA_SIGINFO | SA_ONSTACK; /* @@ -402,25 +430,26 @@ void native_interrupt_init(void) err(1, "native_interrupt_init: sigemptyset"); } */ - if (sigprocmask(SIG_SETMASK, NULL, &native_sig_set) == -1) { + if(sigprocmask(SIG_SETMASK, NULL, &native_sig_set) == -1) { err(1, "native_interrupt_init(): sigprocmask"); } - if (sigdelset(&native_sig_set, SIGUSR1) == -1) { + if(sigdelset(&native_sig_set, SIGUSR1) == -1) { err(1, "native_interrupt_init: sigdelset"); } - if (sigaction(SIGUSR1, &sa, NULL)) { + if(sigaction(SIGUSR1, &sa, NULL)) { err(1, "native_interrupt_init: sigaction"); } - if (getcontext(&native_isr_context) == -1) { + if(getcontext(&native_isr_context) == -1) { err(1, "native_isr_entry(): getcontext()"); } - if (sigfillset(&(native_isr_context.uc_sigmask)) == -1) { + if(sigfillset(&(native_isr_context.uc_sigmask)) == -1) { err(1, "native_isr_entry(): sigfillset()"); } + native_isr_context.uc_stack.ss_sp = __isr_stack; native_isr_context.uc_stack.ss_size = SIGSTKSZ; native_isr_context.uc_stack.ss_flags = 0; @@ -430,14 +459,16 @@ void native_interrupt_init(void) sigstk.ss_sp = sigalt_stk; sigstk.ss_size = SIGSTKSZ; sigstk.ss_flags = 0; - if (sigaltstack(&sigstk, NULL) < 0) { + + if(sigaltstack(&sigstk, NULL) < 0) { err(1, "main: sigaltstack"); } + makecontext(&native_isr_context, native_irq_handler, 0); _native_in_syscall = 0; - if (pipe(pipefd) == -1) { + if(pipe(pipefd) == -1) { err(1, "native_interrupt_init(): pipe()"); } diff --git a/cpu/native/lpm_cpu.c b/cpu/native/lpm_cpu.c index 121ad5429..cb4592169 100644 --- a/cpu/native/lpm_cpu.c +++ b/cpu/native/lpm_cpu.c @@ -47,21 +47,23 @@ void _native_lpm_sleep() int retval; retval = select(1, &_native_uart_rfds, NULL, NULL, NULL); DEBUG("_native_lpm_sleep: retval: %i\n", retval); - if (retval != -1) { + + if(retval != -1) { /* uart ready, handle input */ /* TODO: switch to ISR context */ _native_handle_uart0_input(); } - else if (errno != EINTR) { + else if(errno != EINTR) { /* select failed for reason other than signal */ err(1, "lpm_set(): select()"); } + /* otherwise select was interrupted because of a signal, continue below */ #else pause(); -#endif +#endif - if (_native_sigpend > 0) { + if(_native_sigpend > 0) { DEBUG("\n\n\t\treturn from syscall, calling native_irq_handler\n\n"); _native_in_syscall = 0; _native_in_isr = 1; @@ -83,8 +85,7 @@ enum lpm_mode lpm_set(enum lpm_mode target) last_lpm = native_lpm; native_lpm = target; - switch(native_lpm) /* @contiki :-p */ - { + switch(native_lpm) { /* @contiki :-p */ case LPM_ON: break; diff --git a/cpu/native/native_cpu.c b/cpu/native/native_cpu.c index 4dbe18ecf..d0c71b1ee 100644 --- a/cpu/native/native_cpu.c +++ b/cpu/native/native_cpu.c @@ -55,15 +55,15 @@ char *thread_stack_init(void *task_func, void *stack_start, int stacksize) stk = stack_start; #ifdef NATIVESPONTOP - p = (ucontext_t*)stk; - stk += sizeof(ucontext_t)/sizeof(void*); + p = (ucontext_t *)stk; + stk += sizeof(ucontext_t) / sizeof(void *); stacksize -= sizeof(ucontext_t); #else - p = (ucontext_t*)(stk + ((stacksize-sizeof(ucontext_t))/sizeof(void*))); + p = (ucontext_t *)(stk + ((stacksize - sizeof(ucontext_t)) / sizeof(void *))); stacksize -= sizeof(ucontext_t); #endif - if (getcontext(p) == -1) { + if(getcontext(p) == -1) { err(1, "thread_stack_init(): getcontext()"); } @@ -71,7 +71,8 @@ char *thread_stack_init(void *task_func, void *stack_start, int stacksize) p->uc_stack.ss_size = stacksize; p->uc_stack.ss_flags = 0; p->uc_link = &end_context; - if (sigemptyset(&(p->uc_sigmask)) == -1) { + + if(sigemptyset(&(p->uc_sigmask)) == -1) { err(1, "thread_stack_init(): sigemptyset()"); } @@ -89,9 +90,10 @@ void cpu_switch_context_exit(void) sched_run(); DEBUG("XXX: cpu_switch_context_exit(): calling setcontext(%s)\n\n", active_thread->name); - ctx = (ucontext_t*)(active_thread->sp); + ctx = (ucontext_t *)(active_thread->sp); eINT(); // XXX: workaround for bug (?) in sched_task_exit - if (setcontext(ctx) == -1) { + + if(setcontext(ctx) == -1) { err(1, "cpu_switch_context_exit(): setcontext():"); } } @@ -105,14 +107,16 @@ void thread_yield() DEBUG("thread_yield()\n"); - oc = (ucontext_t*)(active_thread->sp); + oc = (ucontext_t *)(active_thread->sp); sched_run(); - nc = (ucontext_t*)(active_thread->sp); - if (nc != oc) { + nc = (ucontext_t *)(active_thread->sp); + + if(nc != oc) { DEBUG("thread_yield(): calling swapcontext(%s)\n\n", active_thread->name); - if (swapcontext(oc, nc) == -1) { + + if(swapcontext(oc, nc) == -1) { err(1, "thread_yield(): swapcontext()"); } } @@ -123,9 +127,10 @@ void thread_yield() void native_cpu_init() { - if (getcontext(&end_context) == -1) { + if(getcontext(&end_context) == -1) { err(1, "end_context(): getcontext()"); } + end_context.uc_stack.ss_sp = __isr_stack; end_context.uc_stack.ss_size = SIGSTKSZ; end_context.uc_stack.ss_flags = 0; diff --git a/cpu/native/rtc/posix-rtc.c b/cpu/native/rtc/posix-rtc.c index 22444d65f..dca0a8d87 100644 --- a/cpu/native/rtc/posix-rtc.c +++ b/cpu/native/rtc/posix-rtc.c @@ -45,18 +45,20 @@ void rtc_disable(void) native_rtc_enabled = 0; } -void rtc_set_localtime(struct tm* localt) +void rtc_set_localtime(struct tm *localt) { DEBUG("rtc_set_localtime()\n"); printf("setting time not supported."); } -void rtc_get_localtime(struct tm* localt) +void rtc_get_localtime(struct tm *localt) { time_t t; + if(native_rtc_enabled == 1) { t = time(NULL); - if (localtime_r(&t, localt) == NULL) { + + if(localtime_r(&t, localt) == NULL) { err(1, "rtc_get_localtime: localtime_r"); } } diff --git a/cpu/native/startup.c b/cpu/native/startup.c index 7ecb03806..4523c3dff 100644 --- a/cpu/native/startup.c +++ b/cpu/native/startup.c @@ -22,7 +22,7 @@ extern void board_init(void); extern void native_cpu_init(void); extern void native_interrupt_init(void); -__attribute__ ((constructor)) static void startup(void) +__attribute__((constructor)) static void startup(void) { native_cpu_init(); native_interrupt_init();