Browse Source

Merge pull request #5366 from haukepetersen/add_flashrom_samd21

cpu/samd21: added flashpage driver implementation
master
Francisco Acosta 6 years ago committed by GitHub
parent
commit
6df211383e
  1. 1
      boards/samd21-xpro/Makefile.features
  2. 1
      boards/saml21-xpro/Makefile.features
  3. 1
      boards/samr21-xpro/Makefile.features
  4. 10
      cpu/sam0_common/include/cpu_conf.h
  5. 62
      cpu/sam0_common/periph/flashpage.c

1
boards/samd21-xpro/Makefile.features

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += peiph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm

1
boards/saml21-xpro/Makefile.features

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt

1
boards/samr21-xpro/Makefile.features

@ -1,6 +1,7 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm

10
cpu/sam0_common/include/cpu_conf.h

@ -36,6 +36,16 @@ extern "C" {
#define CPU_FLASH_BASE FLASH_ADDR
/** @} */
/**
* @brief Flash page configuration
* @{
*/
/* a flashpage in RIOT is mapped to a flash row on the SAM0s */
#define FLASHPAGE_SIZE (256U)
/* one SAM0 row contains 4 SAM0 pages -> 4x the amount of RIOT flashpages */
#define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / 4)
/** @} */
#ifdef __cplusplus
}
#endif

62
cpu/sam0_common/periph/flashpage.c

@ -0,0 +1,62 @@
/*
* Copyright (C) 2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_sam0_common
* @{
*
* @file
* @brief Low-level flash page driver implementation
*
* The sam0 has its flash memory organized in pages and rows, where each row
* consists of 4 pages. While pages are writable one at a time, it is only
* possible to delete a complete row. This implementation abstracts this
* behavior by only writing complete rows at a time, so the FLASH_PAGE_SIZE we
* use in RIOT is actually the row size as specified in the datasheet.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "assert.h"
#include "periph/flashpage.h"
#define NVMCTRL_PAC_BIT (0x00000002)
void flashpage_write(int page, void *data)
{
assert(page < FLASHPAGE_NUMOF);
uint32_t *page_addr = (uint32_t *)flashpage_addr(page);
/* remove peripheral access lock for the NVMCTRL peripheral */
#ifdef CPU_FAM_SAML21
PAC->WRCTRL.reg = (PAC_WRCTRL_KEY_CLR | ID_NVMCTRL);
#else
if (PAC1->WPSET.reg & NVMCTRL_PAC_BIT) {
PAC1->WPCLR.reg = NVMCTRL_PAC_BIT;
}
#endif
/* erase given page (the ADDR register uses 16-bit addresses) */
NVMCTRL->ADDR.reg = (((uint32_t)page_addr) >> 1);
NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER);
while (!(NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY)) {}
/* write data to page */
if (data != NULL) {
uint32_t *data_addr = (uint32_t *)data;
NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC);
for (unsigned i = 0; i < (FLASHPAGE_SIZE / 4); i++) {
*page_addr++ = data_addr[i];
}
NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP);
}
}
Loading…
Cancel
Save