cpu/kinetis: make UART mode configurable per board

boards/frdm-k64f/include/periph_conf.h

@@ -89,6 +89,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART0_RX_TX_IRQn,
+        .mode   = UART_MODE_8N1
     },
 };
 

boards/mulle/include/periph_conf.h

@@ -106,6 +106,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART0_RX_TX_IRQn,
+        .mode   = UART_MODE_8N1
     },
     {
         .dev    = UART1,
@@ -116,6 +117,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART1_RX_TX_IRQn,
+        .mode   = UART_MODE_8N1
     },
 };
 

boards/pba-d-01-kw2x/include/periph_conf.h

@@ -91,6 +91,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART2_RX_TX_IRQn,
+        .mode   = UART_MODE_8N1
     },
     {
         .dev    = UART0,
@@ -101,6 +102,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART0_RX_TX_IRQn,
+        .mode   = UART_MODE_8N1
     }
 };
 

cpu/kinetis_common/include/periph_cpu.h

@@ -198,6 +198,18 @@ typedef enum {
 /** @} */
 #endif /* ndef DOXYGEN */
 
+/**
+ * @name    CPU specific UART modes values
+ * @{
+ */
+/** @brief 8 data bits, no parity, 1 stop bit */
+#define UART_MODE_8N1       (0)
+/** @brief 8 data bits, even parity, 1 stop bit */
+#define UART_MODE_8E1       (UART_C1_PE_MASK)
+/** @brief 8 data bits, odd parity, 1 stop bit */
+#define UART_MODE_8O1       (UART_C1_PE_MASK | UART_C1_PT_MASK)
+/** @} */
+
 #ifndef DOXYGEN
 /**
  * @brief   Override default ADC resolution values
@@ -302,14 +314,15 @@ enum {
  * @brief UART module configuration options
  */
 typedef struct {
-    UART_Type *dev;            /**< Pointer to module hardware registers */
-    volatile uint32_t *clken;  /**< Clock enable bitband register address */
-    uint32_t freq;             /**< Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK */
-    gpio_t pin_rx;             /**< RX pin, GPIO_UNDEF disables RX */
-    gpio_t pin_tx;             /**< TX pin */
-    uint32_t pcr_rx;           /**< Pin configuration register bits for RX */
-    uint32_t pcr_tx;           /**< Pin configuration register bits for TX */
-    IRQn_Type irqn;            /**< IRQ number for this module */
+    UART_Type *dev;             /**< Pointer to module hardware registers */
+    volatile uint32_t *clken;   /**< Clock enable bitband register address */
+    uint32_t freq;              /**< Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK */
+    gpio_t pin_rx;              /**< RX pin, GPIO_UNDEF disables RX */
+    gpio_t pin_tx;              /**< TX pin */
+    uint32_t pcr_rx;            /**< Pin configuration register bits for RX */
+    uint32_t pcr_tx;            /**< Pin configuration register bits for TX */
+    IRQn_Type irqn;             /**< IRQ number for this module */
+    uint8_t mode;               /**< UART mode: data bits, parity, stop bits */
 } uart_conf_t;
 
 /**

cpu/kinetis_common/periph/uart.c

@@ -98,7 +98,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
     /* disable transmitter and receiver */
     dev->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
     /* set defaults, 8-bit mode, no parity */
-    dev->C1 = 0;
+    dev->C1 = uart_config[uart].mode;
 
     /* calculate baudrate */
     ubd = (uint16_t)(clk / (baudrate * 16));