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Merge pull request #6863 from haukepetersen/add_board_nrf52840dk

boards: add support for nRF52840dk
pr/rotary
Martine Lenders 6 years ago committed by GitHub
parent
commit
8899825630
  1. 3
      boards/nrf52840dk/Makefile
  2. 7
      boards/nrf52840dk/Makefile.dep
  3. 16
      boards/nrf52840dk/Makefile.features
  4. 21
      boards/nrf52840dk/Makefile.include
  5. 32
      boards/nrf52840dk/board.c
  6. 82
      boards/nrf52840dk/include/board.h
  7. 83
      boards/nrf52840dk/include/gpio_params.h
  8. 101
      boards/nrf52840dk/include/periph_conf.h
  9. 2
      boards/nrf52dk/Makefile.include
  10. 1
      cpu/nrf51/include/periph_cpu.h
  11. 4
      cpu/nrf51/periph/i2c.c
  12. 20
      cpu/nrf52/include/cpu_conf.h
  13. 1
      cpu/nrf52/include/periph_cpu.h
  14. 2426
      cpu/nrf52/include/vendor/nrf52840.h
  15. 14656
      cpu/nrf52/include/vendor/nrf52840_bitfields.h
  16. 0
      cpu/nrf52/ldscripts/nrf52832xxaa.ld
  17. 0
      cpu/nrf52/ldscripts/nrf52832xxaa_sd.ld
  18. 27
      cpu/nrf52/ldscripts/nrf52840xxaa.ld
  19. 27
      cpu/nrf52/ldscripts/nrf52840xxaa_sd.ld
  20. 25
      cpu/nrf52/vectors.c
  21. 6
      cpu/nrf5x_common/include/periph_cpu_common.h
  22. 49
      cpu/nrf5x_common/periph/gpio.c
  23. 7
      cpu/nrf5x_common/periph/spi.c
  24. 34
      cpu/nrf5x_common/periph/uart.c

3
boards/nrf52840dk/Makefile

@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

7
boards/nrf52840dk/Makefile.dep

@ -0,0 +1,7 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
ifneq (,$(filter gnrc_netdev_default netdev_default,$(USEMODULE)))
USEMODULE += nrfmin
endif

16
boards/nrf52840dk/Makefile.features

@ -0,0 +1,16 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Various other features (if any)
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += radio_nrfmin
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_3

21
boards/nrf52840dk/Makefile.include

@ -0,0 +1,21 @@
# define the cpu used by the nRF52 DK
export CPU = nrf52
export CPU_MODEL = nrf52840xxaa
# set default port depending on operating system
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup JLink for flashing
export JLINK_DEVICE := nrf52
# special options when using SoftDevice
ifneq (,$(filter nordic_softdevice_ble,$(USEPKG)))
export JLINK_PRE_FLASH := erase\nloadfile $(BINDIR)/softdevice.hex
export JLINK_FLASH_ADDR := 0x1f000
export LINKER_SCRIPT ?= $(RIOTCPU)/$(CPU)/ldscripts/$(CPU_MODEL)_sd.ld
endif
include $(RIOTMAKE)/tools/jlink.inc.mk
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk

32
boards/nrf52840dk/board.c

@ -0,0 +1,32 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nrf52840dk
* @{
*
* @file
* @brief Board initialization for the nRF52840 DK
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "board.h"
void board_init(void)
{
/* initialize the boards LEDs */
LED_PORT->DIRSET = (LED0_MASK | LED1_MASK | LED2_MASK | LED3_MASK);
LED_PORT->OUTSET = (LED0_MASK | LED1_MASK | LED2_MASK | LED3_MASK);
/* initialize the CPU */
cpu_init();
}

82
boards/nrf52840dk/include/board.h

@ -0,0 +1,82 @@
/*
* Copyright (C) 2017 Feie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nrf52840dk nRF52840 DK
* @ingroup boards
* @{
*
* @file
* @brief Board specific configuration for the nRF52840 DK
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED pin configuration
* @{
*/
#define LED0_PIN GPIO_PIN(0, 13)
#define LED1_PIN GPIO_PIN(0, 14)
#define LED2_PIN GPIO_PIN(0, 15)
#define LED3_PIN GPIO_PIN(0, 16)
#define LED_PORT (NRF_P0)
#define LED0_MASK (1 << 13)
#define LED1_MASK (1 << 14)
#define LED2_MASK (1 << 15)
#define LED3_MASK (1 << 16)
#define LED0_ON (LED_PORT->OUTCLR = LED0_MASK)
#define LED0_OFF (LED_PORT->OUTSET = LED0_MASK)
#define LED0_TOGGLE (LED_PORT->OUT ^= LED0_MASK)
#define LED1_ON (LED_PORT->OUTCLR = LED1_MASK)
#define LED1_OFF (LED_PORT->OUTSET = LED1_MASK)
#define LED1_TOGGLE (LED_PORT->OUT ^= LED1_MASK)
#define LED2_ON (LED_PORT->OUTCLR = LED2_MASK)
#define LED2_OFF (LED_PORT->OUTSET = LED2_MASK)
#define LED2_TOGGLE (LED_PORT->OUT ^= LED2_MASK)
#define LED3_ON (LED_PORT->OUTCLR = LED3_MASK)
#define LED3_OFF (LED_PORT->OUTSET = LED3_MASK)
#define LED3_TOGGLE (LED_PORT->OUT ^= LED3_MASK)
/** @} */
/**
* @brief Button pin configuration
* @{
*/
#define BUTTON1_PIN (GPIO_PIN(0, 11))
#define BUTTON2_PIN (GPIO_PIN(0, 12))
#define BUTTON3_PIN (GPIO_PIN(0, 24))
#define BUTTON4_PIN (GPIO_PIN(0, 25))
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /** BOARD_H */
/** @} */

83
boards/nrf52840dk/include/gpio_params.h

@ -0,0 +1,83 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nrf52840dk
* @{
*
* @file
* @brief Configuration of SAUL mapped GPIO pins
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LED 1",
.pin = LED0_PIN,
.mode = GPIO_OUT
},
{
.name = "LED 2",
.pin = LED1_PIN,
.mode = GPIO_OUT
},
{
.name = "LED 3",
.pin = LED2_PIN,
.mode = GPIO_OUT
},
{
.name = "LED 4",
.pin = LED3_PIN,
.mode = GPIO_OUT
},
{
.name = "Button 1",
.pin = BUTTON1_PIN,
.mode = GPIO_IN_PU
},
{
.name = "Button 2",
.pin = BUTTON2_PIN,
.mode = GPIO_IN_PU
},
{
.name = "Button 3",
.pin = BUTTON3_PIN,
.mode = GPIO_IN_PU
},
{
.name = "Button 4",
.pin = BUTTON4_PIN,
.mode = GPIO_IN_PU
}
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

101
boards/nrf52840dk/include/periph_conf.h

@ -0,0 +1,101 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nrf52840dk
* @{
*
* @file
* @brief Peripheral configuration for the nRF52840 DK
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock configuration
*
* @note The radio will not work with the internal RC oscillator!
*
* @{
*/
#define CLOCK_CORECLOCK (64000000U) /* fixed for all NRF52832 */
#define CLOCK_CRYSTAL (32U) /* set to 0: internal RC oscillator
32: 32MHz crystal */
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = NRF_TIMER1,
.channels = 3,
.bitmode = TIMER_BITMODE_BITMODE_32Bit,
.irqn = TIMER1_IRQn
}
};
#define TIMER_0_ISR isr_timer1
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name Real time counter configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV NRF_RTC1
#define RTT_IRQ RTC1_IRQn
#define RTT_ISR isr_rtc1
#define RTT_MAX_VALUE (0xffffff)
#define RTT_FREQUENCY (10) /* in Hz */
#define RTT_PRESCALER (3275U) /* run with 10 Hz */
/** @} */
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_PIN_RX GPIO_PIN(0, 8)
#define UART_PIN_TX GPIO_PIN(0, 6)
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = NRF_SPI0,
.sclk = 15,
.mosi = 13,
.miso = 14
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __PERIPH_CONF_H */

2
boards/nrf52dk/Makefile.include

@ -1,6 +1,6 @@
# define the cpu used by the nRF52 DK
export CPU = nrf52
export CPU_MODEL = nrf52xxaa
export CPU_MODEL = nrf52832xxaa
# set default port depending on operating system
PORT_LINUX ?= /dev/ttyACM0

1
cpu/nrf51/include/periph_cpu.h

@ -29,7 +29,6 @@ extern "C" {
* @brief Redefine some peripheral names to unify them between nRF51 and 52
* @{
*/
#define GPIO_BASE (NRF_GPIO)
#define UART_IRQN (UART0_IRQn)
#define SPI_SCKSEL (dev(bus)->PSELSCK)
#define SPI_MOSISEL (dev(bus)->PSELMOSI)

4
cpu/nrf51/periph/i2c.c

@ -101,8 +101,8 @@ int i2c_init_master(i2c_t bus, i2c_speed_t speed)
dev(bus)->POWER = TWI_POWER_POWER_Enabled;
/* pin configuration */
GPIO_BASE->PIN_CNF[i2c_config[bus].pin_scl] = (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos);
GPIO_BASE->PIN_CNF[i2c_config[bus].pin_scl] = (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos);
NRF_GPIO->PIN_CNF[i2c_config[bus].pin_scl] = (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos);
NRF_GPIO->PIN_CNF[i2c_config[bus].pin_scl] = (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos);
dev(bus)->PSELSCL = i2c_config[bus].pin_scl;
dev(bus)->PSELSDA = i2c_config[bus].pin_sda;

20
cpu/nrf52/include/cpu_conf.h

@ -21,20 +21,32 @@
#define CPU_CONF_H
#include "cpu_conf_common.h"
#ifdef CPU_MODEL_NRF52832XXAA
#include "vendor/nrf52.h"
#include "vendor/nrf52_bitfields.h"
#elif defined(CPU_MODEL_NRF52840XXAA)
#include "vendor/nrf52840.h"
#include "vendor/nrf52840_bitfields.h"
#else
#error "The CPU_MODEL of your board is currently not supported"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @name ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (2U)
#define CPU_IRQ_NUMOF (38U)
#define CPU_FLASH_BASE (0x00000000)
#ifdef CPU_MODEL_NRF52832XXAA
#define CPU_IRQ_NUMOF (38U)
#elif CPU_MODEL_NRF52840XXAA
#define CPU_IRQ_NUMOF (46U)
#endif
/** @} */
/**
@ -43,8 +55,10 @@ extern "C" {
*/
#define FLASHPAGE_SIZE (4096U)
#if defined(CPU_MODEL_NRF52XXAA)
#if defined(CPU_MODEL_NRF52832XXAA)
#define FLASHPAGE_NUMOF (128U)
#elif defined(CPU_MODEL_NRF52840XXAA)
#define FLASHPAGE_NUMOF (256U)
#endif
/** @} */

1
cpu/nrf52/include/periph_cpu.h

@ -29,7 +29,6 @@ extern "C" {
* @brief Redefine some peripheral names to unify them between nRF51 and 52
* @{
*/
#define GPIO_BASE (NRF_P0)
#define UART_IRQN (UARTE0_UART0_IRQn)
#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)

2426
cpu/nrf52/include/vendor/nrf52840.h vendored

File diff suppressed because it is too large Load Diff

14656
cpu/nrf52/include/vendor/nrf52840_bitfields.h vendored

File diff suppressed because it is too large Load Diff

0
cpu/nrf52/ldscripts/nrf52xxaa.ld → cpu/nrf52/ldscripts/nrf52832xxaa.ld

0
cpu/nrf52/ldscripts/nrf52xxaa_sd.ld → cpu/nrf52/ldscripts/nrf52832xxaa_sd.ld

27
cpu/nrf52/ldscripts/nrf52840xxaa.ld

@ -0,0 +1,27 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_nrf52
* @{
*
* @file
* @brief Memory definitions for the NRF52840XXAA
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
INCLUDE cortexm_base.ld

27
cpu/nrf52/ldscripts/nrf52840xxaa_sd.ld

@ -0,0 +1,27 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_nrf52
* @{
*
* @file
* @brief Memory definitions for the NRF52840XXAA
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x1f000, LENGTH = 0xe1000
ram (rwx) : ORIGIN = 0x20002800, LENGTH = 0x3D800
}
INCLUDE cortexm_base.ld

25
cpu/nrf52/vectors.c

@ -89,6 +89,15 @@ WEAK_DEFAULT void isr_spi2(void);
WEAK_DEFAULT void isr_rtc2(void);
WEAK_DEFAULT void isr_i2s(void);
#ifdef CPU_MODEL_NRF52840XXAA
WEAK_DEFAULT void isr_fpu(void);
WEAK_DEFAULT void isr_usbd(void);
WEAK_DEFAULT void isr_uarte1(void);
WEAK_DEFAULT void isr_qspi(void);
WEAK_DEFAULT void isr_cryptocell(void);
WEAK_DEFAULT void isr_spi3(void);
WEAK_DEFAULT void isr_pwm3(void);
#endif
#ifdef SOFTDEVICE_PRESENT
extern void SWI2_EGU2_IRQHandler(void);
@ -144,9 +153,9 @@ ISR_VECTORS const void *interrupt_vector[] = {
#else
(void *) isr_swi2, /* swi2 */
#endif
(void *) (0UL), /* swi3 */
(void *) (0UL), /* swi4 */
(void *) (0UL), /* swi5 */
(void *) isr_swi3, /* swi3 */
(void *) isr_swi4, /* swi4 */
(void *) isr_swi5, /* swi5 */
(void *) isr_timer3, /* timer 3 */
(void *) isr_timer4, /* timer 4 */
(void *) isr_pwm0, /* pwm 0 */
@ -159,4 +168,14 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void *) isr_spi2, /* spi 2 */
(void *) isr_rtc2, /* rtc 2 */
(void *) isr_i2s, /* i2s */
#ifdef CPU_MODEL_NRF52840XXAA
(void *) isr_fpu, /* fpu */
(void *) isr_usbd, /* usbc */
(void *) isr_uarte1, /* uarte1 */
(void *) isr_qspi, /* qspi */
(void *) isr_cryptocell, /* cryptocell */
(void *) isr_spi3, /* spi3 */
(void *) (0UL), /* reserved */
(void *) isr_pwm3, /* pwm3 */
#endif
};

6
cpu/nrf5x_common/include/periph_cpu_common.h

@ -35,11 +35,15 @@ extern "C" {
#define CPUID_LEN (8U)
/**
* @brief Override macro for defining GPIO pins
* @name Override macro for defining GPIO pins
*
* The port definition is used (and zeroed) to suppress compiler warnings
*/
#ifdef CPU_MODEL_NRF52840XXAA
#define GPIO_PIN(x,y) ((x << 5) | y)
#else
#define GPIO_PIN(x,y) ((x & 0) | y)
#endif
/**
* @brief Generate GPIO mode bitfields

49
cpu/nrf5x_common/periph/gpio.c

@ -30,11 +30,39 @@
#include "periph_cpu.h"
#include "periph_conf.h"
#define PORT_BIT (1 << 5)
#define PIN_MASK (0x1f)
/**
* @brief Place to store the interrupt context
*/
static gpio_isr_ctx_t exti_chan;
/**
* @brief Get the port's base address
*/
static inline NRF_GPIO_Type* port(gpio_t pin)
{
#if (CPU_FAM_NRF51)
return NRF_GPIO;
#elif defined(CPU_MODEL_NRF52832XXAA)
return NRF_P0;
#else
return (pin & PORT_BIT) ? NRF_P1 : NRF_P0;
#endif
}
/**
* @brief Get a pin's offset
*/
static inline int pin_num(gpio_t pin)
{
#ifdef CPU_MODEL_NRF52840XXAA
return (pin & PIN_MASK);
#else
return (int)pin;
#endif
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
@ -44,7 +72,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
case GPIO_IN_PU:
case GPIO_OUT:
/* configure pin direction, input buffer and pull resistor state */
GPIO_BASE->PIN_CNF[pin] = mode;
port(pin)->PIN_CNF[pin] = mode;
break;
default:
return -1;
@ -68,6 +96,9 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* configure the GPIOTE channel: set even mode, pin and active flank */
NRF_GPIOTE->CONFIG[0] = (GPIOTE_CONFIG_MODE_Event |
(pin << GPIOTE_CONFIG_PSEL_Pos) |
#ifdef CPU_MODEL_NRF52840XXAA
((pin & PORT_BIT) << 8) |
#endif
(flank << GPIOTE_CONFIG_POLARITY_Pos));
/* enable external interrupt */
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
@ -88,35 +119,35 @@ void gpio_irq_disable(gpio_t pin)
int gpio_read(gpio_t pin)
{
if (GPIO_BASE->DIR & (1 << pin)) {
return (GPIO_BASE->OUT & (1 << pin)) ? 1 : 0;
if (port(pin)->DIR & (1 << pin)) {
return (port(pin)->OUT & (1 << pin)) ? 1 : 0;
}
else {
return (GPIO_BASE->IN & (1 << pin)) ? 1 : 0;
return (port(pin)->IN & (1 << pin)) ? 1 : 0;
}
}
void gpio_set(gpio_t pin)
{
GPIO_BASE->OUTSET = (1 << pin);
port(pin)->OUTSET = (1 << pin);
}
void gpio_clear(gpio_t pin)
{
GPIO_BASE->OUTCLR = (1 << pin);
port(pin)->OUTCLR = (1 << pin);
}
void gpio_toggle(gpio_t pin)
{
GPIO_BASE->OUT ^= (1 << pin);
port(pin)->OUT ^= (1 << pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
GPIO_BASE->OUTSET = (1 << pin);
port(pin)->OUTSET = (1 << pin);
} else {
GPIO_BASE->OUTCLR = (1 << pin);
port(pin)->OUTCLR = (1 << pin);
}
}

7
cpu/nrf5x_common/periph/spi.c

@ -24,6 +24,7 @@
#include "mutex.h"
#include "assert.h"
#include "periph/spi.h"
#include "periph/gpio.h"
#ifdef SPI_NUMOF
@ -50,9 +51,9 @@ void spi_init(spi_t bus)
void spi_init_pins(spi_t bus)
{
/* set pin direction */
GPIO_BASE->DIRSET = ((1 << spi_config[bus].sclk) |
(1 << spi_config[bus].mosi));
GPIO_BASE->DIRCLR = (1 << spi_config[bus].miso);
gpio_init(spi_config[bus].sclk, GPIO_OUT);
gpio_init(spi_config[bus].mosi, GPIO_OUT);
gpio_init(spi_config[bus].miso, GPIO_IN);
/* select pins for the SPI device */
SPI_SCKSEL = spi_config[bus].sclk;
SPI_MOSISEL = spi_config[bus].mosi;

34
cpu/nrf5x_common/periph/uart.c

@ -27,9 +27,19 @@
#include "cpu.h"
#include "periph/uart.h"
#include "periph_cpu.h"
#include "periph_conf.h"
#include "periph/gpio.h"
#ifdef CPU_MODEL_NRF52840XXAA
#define PSEL_RXD NRF_UART0->PSEL.RXD
#define PSEL_TXD NRF_UART0->PSEL.TXD
#define PSEL_RTS NRF_UART0->PSEL.RTS
#define PSEL_CTS NRF_UART0->PSEL.CTS
#else
#define PSEL_RXD NRF_UART0->PSELRXD
#define PSEL_TXD NRF_UART0->PSELTXD
#define PSEL_RTS NRF_UART0->PSELRTS
#define PSEL_CTS NRF_UART0->PSELCTS
#endif
/**
* @brief Allocate memory for the interrupt context
@ -56,26 +66,26 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
/* configure RX pin */
if (rx_cb) {
GPIO_BASE->DIRCLR = (1 << UART_PIN_RX);
NRF_UART0->PSELRXD = UART_PIN_RX;
gpio_init(UART_PIN_RX, GPIO_IN);
PSEL_RXD = UART_PIN_RX;
}
/* configure TX pin */
GPIO_BASE->DIRSET = (1 << UART_PIN_TX);
NRF_UART0->PSELTXD = UART_PIN_TX;
gpio_init(UART_PIN_TX, GPIO_OUT);
PSEL_TXD = UART_PIN_TX;
/* enable HW-flow control if defined */
#if UART_HWFLOWCTRL
/* set pin mode for RTS and CTS pins */
GPIO_BASE->DIRSET = (1 << UART_PIN_RTS);
GPIO_BASE->DIRCLR = (1 << UART_PIN_CTS);
gpio_init(UART_PIN_RTS, GPIO_OUT);
gpio_init(UART_PIN_CTS, GPIO_IN);
/* configure RTS and CTS pins to use */
NRF_UART0->PSELRTS = UART_PIN_RTS;
NRF_UART0->PSELCTS = UART_PIN_CTS;
PSEL_RTS = UART_PIN_RTS;
PSEL_CTS = UART_PIN_CTS;
NRF_UART0->CONFIG |= UART_CONFIG_HWFC_Msk; /* enable HW flow control */
#else
NRF_UART0->PSELRTS = 0xffffffff; /* pin disconnected */
NRF_UART0->PSELCTS = 0xffffffff; /* pin disconnected */
PSEL_RTS = 0xffffffff; /* pin disconnected */
PSEL_CTS = 0xffffffff; /* pin disconnected */
#endif
/* select baudrate */

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