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dev/timer
Rakendra Thapa 8 years ago
parent dc2bbffcc7
commit 8e24860266
13 changed files with 125 additions and 416 deletions
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6
boards/ek-lm4f120xl/board.c
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@ -35,11 +35,9 @@ void board_init(void)
*/
static void leds_init(void)
{
// enable clock for PORTF
/* enable clock for PORTF */
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
//configure the pins as general output
/*configure the pins as general output */
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
// Turn Red led on
ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 2);
}

24
boards/ek-lm4f120xl/include/board.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -12,14 +12,14 @@
* @brief Board specific files for the Stellaris Launchpad LM4F120 board
* @{
*
* @file
* @file board.h
* @brief Board specific definitions for the Stellaris Launchpad LM4F120 board
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __BOARD_H
#define __BOARD_H
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph/uart.h"
@ -63,10 +63,16 @@ extern "C" {
#define LED_RED_OFF GPIO_PORTF_DATA_R &= ~(LED_RED_PIN)
#define LED_RED_TOGGLE /* not available */
/* @} */
#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
#define VAL_I(x) printf(#x ": %d\n",x);
#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
#define VAL_S(x) printf(#x ":%s\n", x);
/**
* @name Macros defined for quick debugging purposes.
* @{
*/
#define TRACE printf("TRACE %s:%d: %s\n", __FILE__, __LINE__, __FUNCTION__)
#define VAL_I(x) printf(#x ": %d\n",x);
#define VAL_X(x) printf(#x ":0x%X\n", (unsigned int)x);
#define VAL_S(x) printf(#x ":%s\n", x);
/* @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
@ -77,5 +83,5 @@ extern void board_init(void);
}
#endif
#endif /** __BOARD_H */
#endif /** BOARD_H */
/** @} */

308
boards/ek-lm4f120xl/include/periph_conf.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -10,14 +10,14 @@
* @ingroup boards_ek-lm4f120xl
* @{
*
* @file
* @file periph_conf.h
* @name Peripheral MCU configuration for the ek-lm4f120xl board
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __PERIPH_CONF_H
#define __PERIPH_CONF_H
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#ifdef __cplusplus
extern "C" {
@ -33,23 +33,20 @@ extern "C" {
#define TIMER_IRQ_PRIO 1
/* Timer 0 configuration */
//#define TIMER_0_DEV TIM2
#define TIMER_0_CHANNELS 2
#define TIMER_0_CHANNELS 1
#define TIMER_0_PRESCALER (39U)
#define TIMER_0_MAX_VALUE (0xffffffff)
#define TIMER_0_ISR isr_wtimer0
#define TIMER_0_IRQ_CHAN Timer0A_IRQn
/* Timer 1 configuration */
#define TIMER_1_CHANNELS 2
#define TIMER_1_CHANNELS 1
#define TIMER_1_PRESCALER (39U)
#define TIMER_1_MAX_VALUE (0xffffffff)
#define TIMER_1_ISR isr_wtimer1
#define TIMER_1_IRQ_CHAN Timer1A_IRQn
/** @} */
/** @} */
/**
* @name UART configuration
* @{
@ -58,30 +55,22 @@ extern "C" {
#define UART_0_EN 1
#define UART_1_EN 0
#define UART_IRQ_PRIO 1
#define UART_CLK ROM_SysCtlClockGet() /*RT clock runs with 40MHz */
#define UART_CLK ROM_SysCtlClockGet() /* UART clock runs with 40MHz */
/* UART 0 device configuration */
#define UART_0_DEV UART0_BASE
#define UART_0_CLK (40000000) /* UART clock runs with 42MHz (F_CPU / 4) */
#define UART_0_CLK (40000000)
#define UART_0_IRQ_CHAN UART0_IRQn
#define UART_0_ISR isr_usart0
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_TX_PIN UART_PA1_U0TX
#define UART_0_RX_PIN UART_PA0_U0RX
#define UART_0_AF 7
/* UART 1 device configuration */
#define UART_1_DEV UART1_BASE
#define UART_1_CLK (40000000) /* UART clock runs with 40MHz (F_CPU / 4) */
#define UART_1_CLK (40000000)
#define UART_1_IRQ_CHAN UART1_IRQn
#define UART_1_ISR isr_usart1
/* UART 1 pin configuration */
#define UART_1_PORT GPIOD
#define UART_1_TX_PIN 8
#define UART_1_RX_PIN 9
#define UART_1_AF 7
/** @} */
/**
@ -91,295 +80,18 @@ extern "C" {
#define ADC_NUMOF (2U)
#define ADC_0_EN 1
#define ADC_1_EN 1
#define ADC_MAX_CHANNELS 2
/** @} */
/* ADC 0 configuration */
#define ADC_0_DEV ADC0_BASE
#define ADC_0_CHANNELS 2
#define ADC_0_PORT GPIO_PORTE_BASE
/* ADC 0 channel 0 pin config */
#define ADC_0_CH0 1
#define ADC_0_CH0_PIN GPIO_PIN_3
/* ADC 0 channel 1 pin config */
#define ADC_0_CH1 4
#define ADC_0_CH1_PIN 4
/* ADC 1 configuration */
#define ADC_1_DEV ADC1_BASE
#define ADC_1_CHANNELS 2
#define ADC_1_PORT GPIO_PORTE_BASE
#define ADC_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
/* ADC 1 channel 0 pin config */
#define ADC_1_CH0 11
#define ADC_1_CH0_PIN GPIO_PIN_2
/* ADC 1 channel 1 pin config */
#define ADC_1_CH1 12
#define ADC_1_CH1_PIN 2
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (1U)
#define DAC_0_EN 1
#define DAC_MAX_CHANNELS 2
/* DAC 0 configuration */
#define DAC_0_DEV DAC
#define DAC_0_CHANNELS 2
#define DAC_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
#define DAC_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#define DAC_0_PORT GPIOA
#define DAC_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
/* DAC 0 channel config */
#define DAC_0_CH0_PIN 4
#define DAC_0_CH1_PIN 5
/**
* @name PWM configuration
* @{
*/
#define PWM_NUMOF (2U)
#define PWM_0_EN 1
#define PWM_1_EN 1
#define PWM_MAX_CHANNELS 4
/* PWM 0 device configuration */
#define PWM_0_DEV TIM1
#define PWM_0_CHANNELS 4
#define PWM_0_CLK (168000000U)
#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM1EN)
#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN)
/* PWM 0 pin configuration */
#define PWM_0_PORT GPIOE
#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN)
#define PWM_0_PIN_CH0 9
#define PWM_0_PIN_CH1 11
#define PWM_0_PIN_CH2 13
#define PWM_0_PIN_CH3 14
#define PWM_0_PIN_AF 1
/* PWM 1 device configuration */
#define PWM_1_DEV TIM3
#define PWM_1_CHANNELS 3
#define PWM_1_CLK (84000000U)
#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN)
/* PWM 1 pin configuration */
#define PWM_1_PORT GPIOB
#define PWM_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define PWM_1_PIN_CH0 4
#define PWM_1_PIN_CH1 5
#define PWM_1_PIN_CH2 0
#define PWM_1_PIN_CH3 1
#define PWM_1_PIN_AF 2
/** @} */
/**
* @name Random Number Generator configuration
* @{
*/
#define RANDOM_NUMOF (1U)
/** @} */
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF (2U)
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_IRQ_PRIO 1
/* SPI 0 device config */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_0_IRQ SPI1_IRQn
#define SPI_0_IRQ_HANDLER isr_spi1
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT GPIOA
#define SPI_0_SCK_PIN 5
#define SPI_0_SCK_AF 5
#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_AF 5
#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_AF 5
#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
/* SPI 1 device config */
#define SPI_1_DEV SPI2
#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
#define SPI_1_BUS_DIV 0 /* 1 -> SPI runs with half CPU clock, 0 -> quarter CPU clock */
#define SPI_1_IRQ SPI2_IRQn
#define SPI_1_IRQ_HANDLER isr_spi2
/* SPI 1 pin configuration */
#define SPI_1_SCK_PORT GPIOB
#define SPI_1_SCK_PIN 13
#define SPI_1_SCK_AF 5
#define SPI_1_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define SPI_1_MISO_PORT GPIOB
#define SPI_1_MISO_PIN 14
#define SPI_1_MISO_AF 5
#define SPI_1_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define SPI_1_MOSI_PORT GPIOB
#define SPI_1_MOSI_PIN 15
#define SPI_1_MOSI_AF 5
#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_0_EN 1
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (42000000U)
/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 6
#define I2C_0_SCL_AF 4
#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 7
#define I2C_0_SDA_AF 4
#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
/** @} */
/**
* @name GPIO configuration
* @{
*/
#define GPIO_NUMOF 12
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_IRQ_PRIO 1
/* IRQ config */
#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_1 could be used here */
#define GPIO_IRQ_1 GPIO_2
#define GPIO_IRQ_2 GPIO_3
#define GPIO_IRQ_3 GPIO_4
#define GPIO_IRQ_4 GPIO_5
#define GPIO_IRQ_5 GPIO_6
#define GPIO_IRQ_6 GPIO_7
#define GPIO_IRQ_7 GPIO_8
#define GPIO_IRQ_8 GPIO_9
#define GPIO_IRQ_9 GPIO_10
#define GPIO_IRQ_10 GPIO_11
#define GPIO_IRQ_11 -1/* not configured */
#define GPIO_IRQ_12 -1/* not configured */
#define GPIO_IRQ_13 -1/* not configured */
#define GPIO_IRQ_14 -1/* not configured */
#define GPIO_IRQ_15 -1/* not configured */
/* GPIO channel 0 config */
#define GPIO_0_PORT GPIOA /* Used for user button 1 */
#define GPIO_0_PIN 0
#define GPIO_0_CLK 0 /* 0: PORT A, 1: B ... */
#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
#define GPIO_0_IRQ EXTI0_IRQn
/* GPIO channel 1 config */
#define GPIO_1_PORT GPIOE /* LIS302DL INT1 */
#define GPIO_1_PIN 0
#define GPIO_1_CLK 4
#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE)
#define GPIO_1_IRQ EXTI0_IRQn
/* GPIO channel 2 config */
#define GPIO_2_PORT GPIOE /* LIS302DL INT2 */
#define GPIO_2_PIN 1
#define GPIO_2_CLK 4
#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE)
#define GPIO_2_IRQ EXTI1_IRQn
/* GPIO channel 3 config */
#define GPIO_3_PORT GPIOE
#define GPIO_3_PIN 2
#define GPIO_3_CLK 4
#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE)
#define GPIO_3_IRQ EXTI2_IRQn
/* GPIO channel 4 config */
#define GPIO_4_PORT GPIOE /* LIS302DL CS */
#define GPIO_4_PIN 3
#define GPIO_4_CLK 4
#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE)
#define GPIO_4_IRQ EXTI3_IRQn
/* GPIO channel 5 config */
#define GPIO_5_PORT GPIOD /* CS43L22 RESET */
#define GPIO_5_PIN 4
#define GPIO_5_CLK 3
#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PD)
#define GPIO_5_IRQ EXTI4_IRQn
/* GPIO channel 6 config */
#define GPIO_6_PORT GPIOD /* LD8 */
#define GPIO_6_PIN 5
#define GPIO_6_CLK 3
#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PD)
#define GPIO_6_IRQ EXTI9_5_IRQn
/* GPIO channel 7 config */
#define GPIO_7_PORT GPIOD
#define GPIO_7_PIN 6
#define GPIO_7_CLK 3
#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PD)
#define GPIO_7_IRQ EXTI9_5_IRQn
/* GPIO channel 8 config */
#define GPIO_8_PORT GPIOD
#define GPIO_8_PIN 7
#define GPIO_8_CLK 3
#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PD)
#define GPIO_8_IRQ EXTI9_5_IRQn
/* GPIO channel 9 config */
#define GPIO_9_PORT GPIOA
#define GPIO_9_PIN 8
#define GPIO_9_CLK 0
#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA)
#define GPIO_9_IRQ EXTI9_5_IRQn
/* GPIO channel 10 config */
#define GPIO_10_PORT GPIOA /* LD7 */
#define GPIO_10_PIN 9
#define GPIO_10_CLK 0
#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA)
#define GPIO_10_IRQ EXTI9_5_IRQn
/* GPIO channel 11 config */
#define GPIO_11_PORT GPIOD
#define GPIO_11_PIN 10
#define GPIO_11_CLK 3
#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PD)
#define GPIO_11_IRQ EXTI15_10_IRQn
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __PERIPH_CONF_H */
#endif /* PERIPH_CONF_H */
/** @} */

6
cpu/lm4f120/cpu.c
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@ -10,11 +10,10 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file cpu.c
* @brief Implementation of the CPU initialization
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include "cpu.h"
@ -31,7 +30,7 @@
*/
void cpu_init(void)
{
// initializes the Cortex-M core
/* initializes the Cortex-M core */
cortexm_init();
/* initialize the clock system */
@ -68,3 +67,4 @@ void cpu_clock_init(int clk)
break;
}
}
/** @} */

31
cpu/lm4f120/include/cpu_conf.h
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@ -8,19 +8,20 @@
/**
* @defgroup cpu_lm4f120
* @ingroup cpu
* @brief CPU specific implementations for the Stellaris Launchpad LM4F120 board
* @ingroup cpu cpu_lm4f120
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*12
* @file cpu_conf.h
* @brief CPU specific implementations for LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __CPU_CONF_H
#define __CPU_CONF_H
#ifndef CPU_CONF_H
#define CPU_CONF_H
#include <stdio.h>
#include <stdlib.h>
#include "hw_ints.h"
#include "hw_memmap.h"
#include "hw_nvic.h"
@ -41,8 +42,6 @@
#include "stellaris_periph/rom.h"
#include "hwtimer_cpu.h"
#include "periph/uart.h"
#include "stdio.h"
#include "stdlib.h"
#ifdef __cplusplus
extern "C" {
@ -59,9 +58,11 @@ extern "C" {
/**
* @brief Length for reading CPU_ID
* @{
*/
#define CPUID_ID_LEN (12)
#define CPUID_ADDR NVIC_CPUID
/** @} */
/**
* @name CC110X buffer size definitions for the stm32f4
@ -71,9 +72,11 @@ extern "C" {
#define TRANSCEIVER_BUFFER_SIZE (10)
#define RX_BUF_SIZE (10)
#endif
/** @} */
/**
* @name Define the nominal CPU core clock in this board
* @{
*/
#define F_CPU 1000000
#define CLK80 1
@ -81,13 +84,19 @@ extern "C" {
#define CLK40 3
#define CLK16 4
#define CLK1 5
/** @} */
/**
* @name cpu functions
* @{
*/
extern void setup_fpu(void);
extern void cpu_clock_init(int);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __CPU_CONF_H */
#endif /* CPU_CONF_H */
/** @} */

20
cpu/lm4f120/include/hwtimer_cpu.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.coa>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -10,33 +10,33 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file hwtimer_cpu.h
* @brief CPU specific hwtimer configuration options
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifndef HWTIMER_CPU_H
#define HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
extern "C"{
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
/** @} */
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
#endif /* HWTIMER_CPU_H */
/** @} */

36
cpu/lm4f120/include/lm4f120h5qr.h
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@ -1,10 +1,5 @@
/**************************************************************************//**
* @file lm4f120h5qr.h
* @brief LM4F120H5QR Core Peripheral Access Layer Header File
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
/*
* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -30,20 +25,27 @@
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/**************************************************************************
* @ingroup cpu_lm4f120
* @{
* @file lm4f120h5qr.h
* @brief LM4F120H5QR Core Peripheral Access Layer Header File
* @note
*
**************************************************************************/
#ifndef __LM4F120H5QR_H__
#define __LM4F120H5QR_H__
#ifndef LM4F120H5QR_H
#define LM4F120H5QR_H
#ifdef __cplusplus
extern "C" {
#endif
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< LM4F120H5QR provides an MPU */
#define __NVIC_PRIO_BITS 3 /*!< LM4F120H5QR uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
@ -61,7 +63,7 @@ typedef enum
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** LM4F specific Interrupt Numbers **********************************************************************/
/****** LM4F specific Interrupt Numbers ***********************************************************************/
GPIOPortA_IRQn = 0,
GPIOPortB_IRQn = 1,
GPIOPortC_IRQn = 2,
@ -113,11 +115,11 @@ typedef enum
} IRQn_Type;
#include <stdint.h> /* standard types definitions */
#include <stdint.h> /* standard types definitions */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#ifdef __cplusplus
}
#endif
#endif /* __LM4F120H5QR_H__*/
#endif /* LM4F120H5QR_H*/
/** @} */

5
cpu/lm4f120/lpm_arch.c
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@ -10,12 +10,10 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file lpm_arch.c
* @brief Implementation of the kernels power management interface
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include "cpu.h"
@ -52,3 +50,4 @@ void lpm_arch_end_awake(void)
{
/* TODO */
}
/** @} */

5
cpu/lm4f120/periph/adc.c
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@ -10,12 +10,10 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file adc.c
* @brief Low-level ADC driver implementation
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
#include "cpu.h"
@ -219,3 +217,4 @@ float adc_mapf(adc_t dev, int value, float min, float max)
}
#endif /* ADC_NUMOF */
/** @} */

13
cpu/lm4f120/periph/cpuid.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -7,23 +7,22 @@
*/
/**
* @addtogroup driver_periph
* @addtogroup driver_periph
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief Low-level CPUID driver implementation
* @file cpuid.c
* @brief Low-level CPUID driver implementation
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#include <string.h>
#include "cpu_conf.h"
#include "periph/cpuid.h"
void cpuid_get(void *id)
{
memcpy(id, (void *)(CPUID_ADDR), CPUID_ID_LEN);
}
/** @} */

18
cpu/lm4f120/periph/timer.c
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@ -10,11 +10,10 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file timer.c
* @brief Implementation of the low-level timer driver for the LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include <stdint.h>
@ -33,12 +32,14 @@
/**
* @brief Struct holding the configuration data
* @{
*/
typedef struct {
void (*cb)(int); /**< timeout callback */
} timer_conf_t;
static timer_conf_t config[TIMER_NUMOF];
/**@}*/
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
@ -48,7 +49,7 @@ int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // Configure for periodic mode
WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
ROM_IntPrioritySet(INT_WTIMER0A, 32);
@ -84,7 +85,7 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
int timer_clear(tim_t dev, int channel)
{
if (dev == TIMER_0){
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // clear timer0A timeout flag
WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
return 1;
}
return -1;
@ -135,7 +136,7 @@ void timer_irq_disable(tim_t dev)
void timer_reset(tim_t dev)
{
if (dev == TIMER_0) {
// Performs a software reset of a peripheral
/* Performs a software reset of a peripheral */
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_WTIMER0);
}
}
@ -143,7 +144,7 @@ void timer_reset(tim_t dev)
#if TIMER_0_EN
void isr_timer0(void)
{
TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
TIMER0_ICR_R = TIMER_ICR_TATOCINT;
config[TIMER_0].cb(0);
if (sched_context_switch_request){
@ -152,13 +153,14 @@ void isr_timer0(void)
}
void isr_wtimer0(void)
{
WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
WTIMER0_ICR_R = TIMER_ICR_TATOCINT;
config[TIMER_0].cb(0);
if (sched_context_switch_request){
thread_yield();
}
}
#endif
#endif /* TIMER_0_EN */
#endif /* TIMER_0_EN */
/** @} */

56
cpu/lm4f120/periph/uart.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -10,11 +10,10 @@
* @ingroup cpu_lm4f120
* @{
*
* @file
* @file uart.c
* @brief Implementation of the low-level UART driver for the LM4F120
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
* @}
*/
#include <stdint.h>
@ -26,24 +25,18 @@
#include "periph_conf.h"
/* guard the file in case no UART is defined */
#if (UART_0_EN)
#if UART_0_EN
/**
* @brief Struct holding the configuration data for a UART device
* @{
*/
typedef struct {
uart_rx_cb_t rx_cb; /**< receive callback */
uart_tx_cb_t tx_cb; /**< transmit callback */
void *arg; /**< callback argument */
} uart_conf_t;
/**
* @brief Unified interrupt handler for all UART devices
*
* @param uartnum the number of the UART that triggered the ISR
* @param uart the UART device that triggered the ISR
*/
//static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart);
/**@}*/
/**
* @brief UART device configurations
@ -70,9 +63,9 @@ static const unsigned long g_ulUARTBase[3] =
UART2_BASE
};
// The list of possible interrupts for the console UART.
//
//*****************************************************************************
/**
* The list of possible interrupts for the console UART.
*/
static const unsigned long g_ulUARTInt[3] =
{
INT_UART0,
@ -80,8 +73,8 @@ static const unsigned long g_ulUARTInt[3] =
INT_UART2
};
/**********************************************************************************/
/* Configuring the UART console
/**
* Configuring the UART console
*/
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
@ -103,28 +96,25 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
config[uart].arg = arg;
// ulBase = g_ulUARTBase[uart];
// Configure the relevant UART pins for operations as a UART rather than GPIOs.
/* enable recieve interrupt */
switch (uart){
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // Set FIFO to 8 Characters
ROM_UARTFIFOEnable(UART0_BASE); // Enable FIFOs
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
ROM_UARTFIFOEnable(UART0_BASE);
// Enable the UART interrupt
/* Enable the UART interrupt */
NVIC_EnableIRQ(UART_0_IRQ_CHAN);
// Enable RX interrupt
/* Enable RX interrupt */
UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
// Enable the UART interrupt
/* Enable the UART interrupt */
NVIC_EnableIRQ(UART_1_IRQ_CHAN);
break;
#endif
@ -190,21 +180,16 @@ void uart_poweroff(uart_t uart)
ROM_UARTDisable(UART0_BASE);
}
//*****************************************************************************
//
// The UART interrupt handler.
//
//*****************************************************************************
/**
* The UART interrupt handler.
*/
void isr_usart0(void)
{
unsigned long ulStatus;
char cChar;
long lChar;
// Get the interrupt status
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
// Clear the asserted interrupts
ROM_UARTIntClear(UART0_BASE, ulStatus);
// Are we interrupted due to TX done
@ -218,10 +203,8 @@ void isr_usart0(void)
// Are we interrupted due to a recieved character
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
// Get all the available characters from the UART
while(ROM_UARTCharsAvail(UART0_BASE))
{
// Read a character
lChar = ROM_UARTCharGetNonBlocking(UART0_BASE);
cChar = (unsigned char)(lChar & 0xFF);
config[UART_0].rx_cb(config[UART_0].arg, cChar);
@ -231,4 +214,5 @@ void isr_usart0(void)
thread_yield();
}
}
#endif /* (UART_0_EN || UART_1_EN) */
#endif /*UART_0_EN*/
/** @} */

13
cpu/lm4f120/vectors.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2(void *) (0UL)14-2(void *) (0UL)15 Freie Universität Berlin
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa#gmail.com>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -10,12 +10,10 @@
* @ingroup cpu_stm32f4
* @{
*
* @file
* @file vectors.c
* @brief Interrupt vector definitions
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#include <stdint.h>
@ -138,7 +136,7 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
* context switching is happening here */
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
// Peripherial interrupts start here.
/* Peripherial interrupts start here.*/
(void *) dummy_handler, // GPIO Port A 16
(void *) dummy_handler, // GPIO Port B 17
(void *) dummy_handler, // GPIO Port C 18
@ -233,7 +231,7 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void *) (0UL), // Reserved 107
(void *) dummy_handler, // 16/32 bit timer 5 A 108
(void *) dummy_handler, // 16/32 bit timer 5 B 109
(void *) isr_wtimer0, // 32/64 bit timer 0 A 110
(void *) isr_wtimer0, // 32/64 bit timer 0 A 110
(void *) dummy_handler, // 32/64 bit timer 0 B 111
(void *) dummy_handler, // 32/64 bit timer 1 A 112
(void *) dummy_handler, // 32/64 bit timer 1 B 113
@ -279,3 +277,4 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void *) (0UL), // Reserved 153
(void *) (0UL) // Reserved 154
};
/** @} */

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