Browse Source

boards/avsextrem: remove deprectated smb380 driver

pr/rotary
Hauke Petersen 6 years ago
parent
commit
90bc8e0505
  1. 2
      boards/avsextrem/Makefile
  2. 1
      boards/avsextrem/Makefile.include
  3. 3
      boards/avsextrem/drivers/Makefile
  4. 1309
      boards/avsextrem/drivers/avsextrem-smb380.c
  5. 425
      boards/avsextrem/drivers/avsextrem-ssp0.c
  6. 258
      boards/avsextrem/include/smb380-board.h
  7. 125
      boards/avsextrem/include/ssp0-board.h

2
boards/avsextrem/Makefile

@ -1,5 +1,5 @@
MODULE = board
DIRS = drivers $(RIOTBOARD)/msba2-common
DIRS = $(RIOTBOARD)/msba2-common
include $(RIOTBASE)/Makefile.base

1
boards/avsextrem/Makefile.include

@ -1,4 +1,3 @@
USEMODULE += msba2-common
USEMODULE += avsextrem-drivers
include $(RIOTBOARD)/msba2-common/Makefile.include

3
boards/avsextrem/drivers/Makefile

@ -1,3 +0,0 @@
MODULE = avsextrem-drivers
include $(RIOTBASE)/Makefile.base

1309
boards/avsextrem/drivers/avsextrem-smb380.c

File diff suppressed because it is too large Load Diff

425
boards/avsextrem/drivers/avsextrem-ssp0.c

@ -1,425 +0,0 @@
/*
* avsextrem-ssp0.c - implementation of the SPI0 interface for the LPC2387,
* and the AVSESTREM board.
* Copyright (C) 2013 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @file
* @internal
* @brief Implements the SPI0 interface for the LPC2387
*
* @author Marco Ziegert <ziegert@inf.fu-berlin.de>
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
* @version $Revision: 3854 $
*
* @note $Id: avsextrem-ssp0.c 3854 2013-08-14 15:27:01Z zkasmi $
*/
#include "lpc23xx.h" /* LPC23XX/24xx Peripheral Registers */
#include "cpu.h"
#include "VIC.h"
#include "periph_conf.h"
#include "ssp0-board.h"
#include "smb380-board.h"
//#include "mma7455l-board.h"
#include "gpioint.h"
#include <stdio.h>
//uint16_t sampleRateMMA7455L;
//uint16_t interruptTicksMMA7455L;
//
//static void MMA7455L_extIntHandler(void);
uint32_t SSP0Init(void)
{
/*
* enable clock to SSP0 for security reason.
* By default, it's enabled already
*/
PCONP |= PCSSP0;
//TODO: configure CLK, MISO, MOSI by default as GPIOs.
#if USE_CS
// P1.20 1.21 1.23 1.24
// PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 | BIT17;
#else
// No SSEL0
// PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17; //1.20 1.23 1.24
#endif
#if SSP1_INTERRUPT_MODE
if (install_irq(SSP1_INT, (void *)SSP0Handler, HIGHEST_PRIORITY) == FALSE) {
return (FALSE);
}
/*
* Set SSPINMS registers to enable interrupts,
* enable all error related interrupts
*/
SSP1IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM;
#endif
return (1);
}
/*
* datasize (wordsize) in decimal (4-16), cpol&cpha =(0/1) and frequency divided
* by 1000 (e.g. 8 MHz = 8000)
*/
uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
uint16_t freq)
{
switch (chip) {
case BMA180_INTERN:
case SMB380_ACC: {
#if USE_CS
PINSEL3 |= BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 |
BIT17; //P1.20 1.21 1.23 1.24
#else
// 1.20 1.23 1.24 are not configured as SSEL0
PINSEL3 |= BIT8 | BIT9 | BIT14 | BIT15 | BIT16 | BIT17;
#endif
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN:
case ACAMDMS: {
#if USE_CS
PINSEL0 |= BIT31;
PINSEL1 |= BIT1 | BIT3 | BIT5; // P0.15 0.16 0.17 0.18
#else
// Turn on NanoPAN
PINSEL0 |= BIT31;
// 0.15 0.17 0.18 are not configured as SSEL0
PINSEL1 |= BIT3 | BIT5;
#endif
break;
}
case NORDIC: {
PINSEL0 |= BIT31;
PINSEL1 |= BIT3 | BIT5; // 0.15 0.17 0.18 SSEL0 (No)
break;
}
default: {
printf("wrong CHIP selected\n");
return 0;
}
}
uint32_t SSP0CR0tmp = 0;
switch (datasize) {
case 4:
SSP0CR0tmp = BIT0 | BIT1;
break;
case 5:
SSP0CR0tmp = BIT2;
break;
case 6:
SSP0CR0tmp = BIT0 | BIT2;
break;
case 7:
SSP0CR0tmp = BIT1 | BIT2;
break;
case 8:
SSP0CR0tmp = BIT0 | BIT1 | BIT2;
break;
case 9:
SSP0CR0tmp = BIT3;
break;
case 10:
SSP0CR0tmp = BIT0 | BIT3;
break;
case 11:
SSP0CR0tmp = BIT1 | BIT3;
break;
case 12:
SSP0CR0tmp = BIT0 | BIT1 | BIT3;
break;
case 13:
SSP0CR0tmp = BIT2 | BIT3;
break;
case 14:
SSP0CR0tmp = BIT0 | BIT2 | BIT3;
break;
case 15:
SSP0CR0tmp = BIT1 | BIT2 | BIT3;
break;
case 16:
SSP0CR0tmp = BIT0 | BIT1 | BIT2 | BIT3;
break;
default:
return 0;
}
if (cpol) {
SSP0CR0tmp |= BIT6;
}
if (cpha) {
SSP0CR0tmp |= BIT7;
}
SSP0CR1 = 0x00; // SSP0 disabled
// Setting xx-Bit Datasize, CPOL and CPHA
SSP0CR0 = SSP0CR0tmp;
// Clock Setup
uint32_t pclksel;
uint32_t cpsr;
lpc2387_pclk_scale(CLOCK_CORECLOCK / 1000, freq, &pclksel, &cpsr);
PCLKSEL1 &= ~(BIT10 | BIT11); // CCLK to PCLK divider ???
PCLKSEL1 |= pclksel << 10;
SSP0CPSR = cpsr;
// Enable
SSP0CR1 |= BIT1; // SSP0 enabled
uint32_t dummy;
for (uint32_t i = 0; i < FIFOSIZE; i++) {
dummy = SSP0DR; // clear the RxFIFO
}
/* to suppress unused-but-set-variable */
(void) dummy;
return 1;
}
uint8_t SSP0Unprepare(uint8_t chip)
{
switch (chip) {
case BMA180_INTERN:
case SMB380_ACC: {
// Turn off Acceleration Sensor
PINSEL3 &= ~(BIT8 | BIT9 | BIT10 | BIT11 | BIT14 | BIT15 | BIT16 |
BIT17);
FIO1DIR |= BIT20 | BIT21 | BIT24;
FIO1DIR &= ~BIT23; // MISO as Input
FIO1SET = BIT20 | BIT24; /*
* CLK + SSEL + MOSI GPIO as Output
* TODO: depends on CPOL+CPHA Settings
*/
FIO1CLR = BIT21;
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NORDIC:
case NANOPAN:
case ACAMDMS: {
// Turn off Nanopan (Pins to GPIO)
PINSEL0 &= ~(BIT30 | BIT31); //CLK to GPIO
PINSEL1 &= ~(BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5);
FIO0DIR |= BIT15 | BIT16 | BIT18; //CLK + SSEL + MOSI GPIO as Output
FIO0DIR &= ~BIT17; // MISO as Input
FIO0SET = BIT15 | BIT16; /*
* CLK + SSEL + MOSI GPIO as Output
* TODO: depends on CPOL+CPHA Settings
*/
FIO0CLR = BIT18;
break;
}
default: {
printf("wrong CHIP selected\n");
return 0;
}
}
return 1;
}
unsigned char SMB380_ssp_write(const unsigned char regAddr,
const unsigned char data, unsigned char flag)
{
uint16_t temp = 0;
if (flag) {
temp = (unsigned int)(((regAddr & 0xFF7F) << 8) | data);
}
else {
temp = (((unsigned int)(regAddr | 0x80) << 8) | 0xFF);
}
return SSP0_write(temp, SMB380_ACC);
}
unsigned char SSP0_write(const uint16_t data, uint8_t device)
{
unsigned char ret = 1;
while ((SSP0SR & (SSPSR_TNF | SSPSR_BSY)) != SSPSR_TNF)
;
if (!USE_CS) {
switch (device) {
case BMA180_INTERN:
case SMB380_ACC: {
FIO1CLR = SSP0_SEL;
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN: {
FIO0CLR = SSP0_SELN;
break;
}
case ACAMDMS:
case NORDIC:
// Chip Select is done in Nordic driver
break;
default:
ret = 0;
goto ret;
}
}
SSP0DR = data;
if (!USE_CS) {
while (SSP0SR & SSPSR_BSY)
;
switch (device) {
case BMA180_INTERN:
case SMB380_ACC: {
FIO1SET = SSP0_SEL;
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN: {
FIO0SET = SSP0_SELN;
break;
}
case ACAMDMS:
case NORDIC:
// Chip Select is done in Nordic driver
break;
default:
ret = 0;
goto ret;
}
}
ret:
return ret;
}
unsigned short SSP0_read(uint8_t device)
{
uint16_t data;
while (!(SSP0SR & SSPSR_RNE))
;
if (!USE_CS) {
switch (device) {
case BMA180_INTERN:
case SMB380_ACC: {
FIO1CLR = SSP0_SEL;
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN: {
FIO0CLR = SSP0_SELN;
break;
}
case NORDIC:
case ACAMDMS:
// Chip Select is done in Nordic driver
break;
default:
data = 0xFFFF;
goto ret;
}
}
data = SSP0DR;
if (!USE_CS) {
switch (device) {
case BMA180_INTERN:
case SMB380_ACC: {
FIO1SET = SSP0_SEL;
break;
}
case BMA180_EXTERN:
case L3G_EXTERN:
case NANOPAN: {
FIO0SET = SSP0_SELN;
break;
}
case ACAMDMS:
case NORDIC:
// Chip Select is done in Nordic driver
break;
default:
data = 0xFFFF;
goto ret;
}
}
ret:
return data;
}
unsigned short SMB380_ssp_read(void)
{
return SSP0_read(SMB380_ACC);
}
unsigned short nrf24l01_ssp_read_write(const uint8_t data)
{
SSP0_write(data, NORDIC);
return SSP0_read(NORDIC);
}
unsigned short acam_trx(const uint8_t data)
{
SSP0_write(data, ACAMDMS);
return SSP0_read(ACAMDMS);
}

258
boards/avsextrem/include/smb380-board.h

@ -1,258 +0,0 @@
/*
* msba2acc-smb380.h - Definitions of the Driver for the SMB380 acceleration
* sensor.
* Copyright (C) 2013 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
**/
/**
* @file
* @internal
* @brief SMB380 acceleration sensor definitions for the LPC2387
*
* @author Marco Ziegert <ziegert@inf.fu-berlin.de>
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
*
*/
#ifndef SMB380_H
#define SMB380_H
#include <stdint.h>
#include "bitarithm.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SMB380_DEBUG_MESSAGE "SMB380 Driver Error: "
#define MSG_TYPE_SMB380_WAKEUP 814
#define SMB380_X_AXIS 0 /* X Axis-Name */
#define SMB380_Y_AXIS 1 /* Y Axis-Name */
#define SMB380_Z_AXIS 2 /* Z Axis-Name */
#define LPM_PREVENT_SLEEP_ACCSENSOR BIT2
enum SMB380_MODE {
SMB380_POLL,
SMB380_POLL_AFTER_CONTINOUS,
SMB380_CONTINOUS,
SMB380_THRESHOLD,
SMB380_FALSEALERT
};
volatile enum SMB380_MODE smb380_mode;
/* Writeable values to EEPROM: from 0x0A (control1) to 0x1D (offset_T).
For writing enable ... flag and add eeprom_offset_address.
Generally it is a good idea to read out shared register addresses before writing,
registers 0x14 and 34h are especially critical.
*/
#define SMB380_EEPROM_OFFSET 0x20
/* Chip-ID Bit0-2, default: 010b */
#define SMB380_CHIP_ID 0x00
/* Chip-ID mask */
#define SMB380_CHIP_ID_MASK 0x07
/* ml_version Bit0-3 ; al_version Bit4-7 */
#define SMB380_AL_ML_VERSION 0x01
#define SMB380_AL_MASK 0xF0
#define SMB380_ML_MASK 0x0F
/* LSB_acc_x Bit6-7; new_data_x Bit0 */
#define SMB380_ACC_X_LSB_NEWDATA 0x02
/* MSB_acc_x Bit0-7 */
#define SMB380_ACC_X_MSB 0x03
/* LSB_acc_y Bit6-7; new_data_y Bit0 */
#define SMB380_ACC_Y_LSB_NEWDATA 0x04
/* MSB_acc_y Bit0-7 */
#define SMB380_ACC_Y_MSB 0x05
/* LSB_acc_z Bit6-7; new_data_z Bit0 */
#define SMB380_ACC_Z_LSB_NEWDATA 0x06
/* MSB_acc_z Bit0-7 */
#define SMB380_ACC_Z_MSB 0x07
#define SMB380_ACC_LSB_MASK 0xC0
#define SMB380_ACC_MSB_MASK 0xFF
#define SMB380_ACC_NEWDATA_MASK 0x01
/* Temperature Bit0-7 */
#define SMB380_TEMP 0x08
/* Status register, contains six flags */
#define SMB380_STATUS 0x09
#define SMB380_STATUS_ST_RESULT_MASK 0x80
#define SMB380_STATUS_ALERT_PHASE_MASK 0x10
#define SMB380_STATUS_LG_LATCHED_MASK 0x08
#define SMB380_STATUS_HG_LATCHED_MASK 0x04
#define SMB380_STATUS_STATUS_LG_MASK 0x02
#define SMB380_STATUS_STATUS_HG_MASK 0x01
/* Control register - contains seven values, default: x000 0000b */
#define SMB380_CONTROL1 0x0A
#define SMB380_CONTROL1_RESET_INT_MASK 0x40
#define SMB380_CONTROL1_UPDATE_MASK 0x20
#define SMB380_CONTROL1_EE_W_MASK 0x10
#define SMB380_CONTROL1_SELF_TEST_1_MASK 0x08
#define SMB380_CONTROL1_SELF_TEST_0_MASK 0x04
#define SMB380_CONTROL1_SOFT_RESET_MASK 0x02
#define SMB380_CONTROL1_SLEEP_MASK 0x01
/* Control register - contains six values, default: x000 0011b */
#define SMB380_CONTROL2 0x0B
#define SMB380_CONTROL2_ALERT_MASK 0x80
#define SMB380_CONTROL2_ANY_MOTION_MASK 0x40
#define SMB380_CONTROL2_COUNTER_HG_MASK 0x30
#define SMB380_CONTROL2_COUNTER_LG_MASK 0x0C
#define SMB380_CONTROL2_ENABLE_HG_MASK 0x02
#define SMB380_CONTROL2_ENABLE_LG_MASK 0x01
/* default: 20 */
#define SMB380_LG_THRES 0x0C
/* default: 150 */
#define SMB380_LG_DUR 0x0D
/* default: 160 */
#define SMB380_HG_THRES 0x0E
/* default: 150 */
#define SMB380_HG_DUR 0x0F
/* default: 0 */
#define SMB380_ANY_MOTION_THRES 0x10
/* default: 0000 0000b */
#define SMB380_ANY_MOTION_DUR_HYST 0x1
#define SMB380_ANY_MOTION_DUR_MASK 0xC0
#define SMB380_ANY_MOTION_DUR_HG_HYST_MASK 0x38
#define SMB380_ANY_MOTION_DUR_LG_HYST_MASK 0x07
/* default: 162 */
#define SMB380_CUST1 0x12
/* default: 13 */
#define SMB380_CUST2 0x13
/* default: xxx0 1110b */
#define SMB380_CONTROL3 0x14
#define SMB380_CONTROL3_RANGE_MASK 0x18
#define SMB380_CONTROL3_BANDWITH_MASK 0x07
/* default: 1000 0000b */
#define SMB380_CONTROL4 0x15
#define SMB380_CONTROL4_SPI4_MASK 0x80
#define SMB380_CONTROL4_ENABLE_ADV_INT_MASK 0x40
#define SMB380_CONTROL4_NEW_DATA_INT_MASK 0x20
#define SMB380_CONTROL4_LATCH_INT_MASK 0x10
#define SMB380_CONTROL4_SHADOW_DIS_MASK 0x08
#define SMB380_CONTROL4_WAKEUP_PAUSE_MASK 0x06
#define SMB380_CONTROL4_WAKEUP_MASK 0x01
#define SMB380_OFFSET_LSB_GAIN_X 0x16
#define SMB380_OFFSET_LSB_GAIN_Y 0x17
#define SMB380_OFFSET_LSB_GAIN_Z 0x18
#define SMB380_OFFSET_LSB_GAIN_T 0x19
#define SMB380_OFFSET_LSB_MASK 0xC0
#define SMB380_OFFSET_GAIN_MASK 0x3F
#define SMB380_OFFSET_MSB_X 0x1A
#define SMB380_OFFSET_MSB_Y 0x1B
#define SMB380_OFFSET_MSB_Z 0x1C
#define SMB380_OFFSET_MSB_T 0x1D
#define SMB380_TEMP_OFFSET -30
#define SMB380_DEFAULT_MAXG 4.0f
#define SMB380_READ_REGISTER 0x00
#define SMB380_WRITE_REGISTER 0x01
#define SMB380_WAKE_UP_PAUSE_20MS 0x00
#define SMB380_WAKE_UP_PAUSE_80MS 0x01
#define SMB380_WAKE_UP_PAUSE_320MS 0x02
#define SMB380_WAKE_UP_PAUSE_2560MS 0x03
#define SMB380_RANGE_2G 0x00
#define SMB380_RANGE_4G 0x01
#define SMB380_RANGE_8G 0x02
#define SMB380_BAND_WIDTH_25HZ 0x00
#define SMB380_BAND_WIDTH_50HZ 0x01
#define SMB380_BAND_WIDTH_100HZ 0x02
#define SMB380_BAND_WIDTH_190HZ 0x03
#define SMB380_BAND_WIDTH_375HZ 0x04
#define SMB380_BAND_WIDTH_750HZ 0x05
#define SMB380_BAND_WIDTH_1500HZ 0x06
/* SMB380_RING_BUFF_SIZE * int16_t (2Byte) * 4 (x,y,z,Temp) = 512 Byte (for 64) */
#define SMB380_RING_BUFF_SIZE 256
/* TODO chsnge size to 2048 */
#define SMB380_RING_BUFF_MAX_THREADS 10
#define SMB380_SAMPLE_RATE_MAX 3000
/*
* change from Header (public) to internal use (private)
* (use it after every write to EEPROM).
* set update_image Bit in control1 to
* copie content from EEPROM (0x2B to 0x3D) to Image (0x0B to 0x1D)
**/
void SMB380_update_image(void);
/*
* change from Header (public) to internal use (private)
* set ee_w Bit in control1 to
* enable read to 0x16 to 0x22 and
* enable write to 0x16 to 0x3D
**/
void SMB380_enable_eeprom_default(void);
/* Example Hysterese function */
uint8_t SMB380_HystereseFunctionSample(int16_t *value);
/* Simple api for single-sample, single thread interrupt mode */
uint8_t SMB380_init_simple(uint16_t samplerate, uint8_t bandwidth,
uint8_t range);
/* Enables Interrupts (normally only once called) */
uint8_t SMB380_init(uint8_t (*func)(int16_t *));
void SMB380_setSampleRate(uint16_t rate);
uint16_t SMB380_getSampleRate(void);
void freeRingReadPointer(void);
void actualizeRingReadPointer(void);
uint8_t readRingBuff(int16_t *value);
uint8_t writeRingBuff(int16_t *value);
void SMB380_activateDynRangeSet(uint8_t activate);
uint8_t checkRange(int16_t *value);
void SMB380_enableEEPROM(void);
void SMB380_disableEEPROM(void);
/* getter */
float SMB380_getSampleRatio(void);
void SMB380_getAcceleration(unsigned char axis, int16_t *pAbs, int16_t *pMg);
int16_t SMB380_getTemperature(void);
unsigned char SMB380_getChipID(void);
unsigned char SMB380_getWakeUpPause(void);
unsigned char SMB380_getBandWidth(void);
int16_t SMB380_getBandWidthAbs(void);
unsigned char SMB380_getRange(void);
unsigned char SMB380_getCustomerReg(void);
unsigned char SMB380_readOffset(uint16_t *offset);
unsigned char SMB380_readOffsetTemp(uint16_t *offset);
unsigned char SMB380_readGain(uint16_t *gain);
unsigned char SMB380_readGainTemp(uint16_t *gain);
/* setter */
void SMB380_setTempOffset(uint16_t offset, uint8_t EEPROM);
void SMB380_setWakeUpPause(unsigned char duration);
void SMB380_setBandWidth(unsigned char bandWidth);
void SMB380_setRange(unsigned char range);
void SMB380_softReset(void);
void SMB380_setCustomerReg(unsigned char data);
void SMB380_setUpperLimit(void);
void SMB380_enableUpperLimit(void);
void SMB380_disableUpperLimit(void);
void SMB380_enableLowerLimit(void);
void SMB380_disableLowerLimit(void);
uint8_t SMB380_setAnyMotionLimit(uint16_t mg, uint16_t gvalueint);
void SMB380_enableAnyMotionLimit(void);
void SMB380_disableAnyMotionLimit(void);
void SMB380_enableNewDataInt(void);
void SMB380_disableNewDataInt(void);
void SMB380_resetInterruptFlags(void);
void SMB380_writeOffset(uint16_t *offset, uint8_t EEPROM);
void SMB380_writeOffsetTemp(uint16_t *offset, uint8_t EEPROM);
/* stats */
void SMB380_ShowMemory(void);
void SMB380_Selftest_1(void);
#ifdef __cplusplus
}
#endif
#endif /* SMB380_H */

125
boards/avsextrem/include/ssp0-board.h

@ -1,125 +0,0 @@
/*
* ssp0-borad.h - header file of the SPI interface for the LPC2387.
* Copyright (C) 2013 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @file
* @internal
* @brief SPI interface definitions for the LPC2387
*
* @author Marco Ziegert <ziegert@inf.fu-berlin.de>
* @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
* @version $Revision: 3854 $
*
* @note $Id: avsextrem-ssp0.c 3854 2010-01-18 15:27:01Z zkasmi $
*/
#ifndef SSP_H
#define SSP_H
#include "stdint.h"
#ifdef __cplusplus
extern "C" {
#endif
#define DMA_ENABLED 0
/*
* if USE_CS is zero, set SSEL as GPIO that you have total control of the
* sequence
**/
#define USE_CS 0
/*
* if 1, use driver for onboard BMA180, otherwise for external BMA180 utilizing
* Nanopan Connector
**/
#define BMA180_ONBOARD 1
#define SMB380_ACC 0
#define NANOPAN 1
#define NORDIC 2
#define BMA180_EXTERN 3
#define BMA180_INTERN 4
#define L3G_EXTERN 5
#define L3G_INTERN 6
#define ACAMDMS 7
/* SPI read and write buffer size */
#define BUFSIZE 256
#define FIFOSIZE 8
/* SSP select pin */
#define SSP0_SEL 1 << 21 /* P1.21 SMB380 */
#define SSP0_SELN 1 << 16 /* P0.16 Nanotron */
/* SSP1 external interrupt Pin (SMB380 specific) */
#define SMB380_INT1 1 << 1 /* P0.1 */
#define BMA180_INT1 1 << 8 /* P2.8 */
/* SSP1 CR0 register */
#define SSPCR0_DSS 1 << 0
#define SSPCR0_FRF 1 << 4
#define SSPCR0_SPO 1 << 6
#define SSPCR0_SPH 1 << 7
#define SSPCR0_SCR 1 << 8
/* SSP1 CR1 register */
#define SSPCR1_LBM 1 << 0
#define SSPCR1_SSE 1 << 1
#define SSPCR1_MS 1 << 2
#define SSPCR1_SOD 1 << 3
/* SSP1 Interrupt Mask Set/Clear register */
#define SSPIMSC_RORIM 1 << 0
#define SSPIMSC_RTIM 1 << 1
#define SSPIMSC_RXIM 1 << 2
#define SSPIMSC_TXIM 1 << 3
/* SSP1 Interrupt Status register */
#define SSPRIS_RORRIS 1 << 0
#define SSPRIS_RTRIS 1 << 1
#define SSPRIS_RXRIS 1 << 2
#define SSPRIS_TXRIS 1 << 3
/* SSP1 Masked Interrupt register */
#define SSPMIS_RORMIS 1 << 0
#define SSPMIS_RTMIS 1 << 1
#define SSPMIS_RXMIS 1 << 2
#define SSPMIS_TXMIS 1 << 3
/* SSP1 Interrupt clear register */
#define SSPICR_RORIC 1 << 0
#define SSPICR_RTIC 1 << 1
#define SSP1_INTERRUPT_MODE 0
#define SMB380_EXTINT_MODE 1
#define BMA180_EXTINT_MODE 1
uint32_t SSP0Init(void);
uint8_t SSP0Prepare(uint8_t chip, uint8_t datasize, uint8_t cpol, uint8_t cpha,
uint16_t freq);
uint8_t SSP0Unprepare(uint8_t chip);
unsigned char SSP0_write(const uint16_t data, uint8_t device);
unsigned short SSP0_read(uint8_t device);
unsigned char SMB380_ssp_write(const unsigned char regAddr,
const unsigned char data, unsigned char flag);
unsigned short SMB380_ssp_read(void);
unsigned short nrf24l01_ssp_read_write(const uint8_t data);
unsigned short acam_trx(const uint8_t data);
void SSP0Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* SSP_H */
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