Browse Source

cpu: added support for stm32l4

pr/rotary
Hauke Petersen 6 years ago
parent
commit
964deefc39
  1. 14
      cpu/stm32_common/cpu_common.c
  2. 5
      cpu/stm32_common/include/periph_cpu_common.h
  3. 4
      cpu/stm32_common/periph/gpio.c
  4. 9
      cpu/stm32_common/periph/uart.c
  5. 10
      cpu/stm32l4/Makefile
  6. 5
      cpu/stm32l4/Makefile.include
  7. 180
      cpu/stm32l4/cpu.c
  8. 47
      cpu/stm32l4/include/cpu_conf.h
  9. 81
      cpu/stm32l4/include/periph_cpu.h
  10. 18523
      cpu/stm32l4/include/vendor/stm32l476xx.h
  11. 30
      cpu/stm32l4/ldscripts/stm32l476rg.ld
  12. 5
      cpu/stm32l4/periph/Makefile
  13. 220
      cpu/stm32l4/vectors.c

14
cpu/stm32_common/cpu_common.c

@ -38,7 +38,11 @@ void periph_clk_en(bus_t bus, uint32_t mask)
{
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4)
RCC->APB1ENR1 |= mask;
#else
RCC->APB1ENR |= mask;
#endif
break;
case APB2:
RCC->APB2ENR |= mask;
@ -55,7 +59,8 @@ void periph_clk_en(bus_t bus, uint32_t mask)
case AHB:
RCC->AHBENR |= mask;
break;
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
|| defined(CPU_FAM_STM32L4)
case AHB1:
RCC->AHB1ENR |= mask;
break;
@ -81,7 +86,11 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
{
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4)
RCC->APB1ENR1 &= ~(mask);
#else
RCC->APB1ENR &= ~(mask);
#endif
break;
case APB2:
RCC->APB2ENR &= ~(mask);
@ -98,7 +107,8 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
case AHB:
RCC->AHBENR &= ~(mask);
break;
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
|| defined(CPU_FAM_STM32L4)
case AHB1:
RCC->AHB1ENR &= ~(mask);
break;

5
cpu/stm32_common/include/periph_cpu_common.h

@ -62,10 +62,11 @@ typedef enum {
#if defined(CPU_FAM_STM32L0)
AHB, /**< AHB bus */
IOP, /**< IOP bus */
#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1)\
#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
|| defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
AHB, /**< AHB bus */
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
|| defined(CPU_FAM_STM32L4)
AHB1, /**< AHB1 bus */
AHB2, /**< AHB2 bus */
AHB3 /**< AHB3 bus */

4
cpu/stm32_common/periph/gpio.c

@ -78,6 +78,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
#endif
@ -178,6 +180,8 @@ void gpio_init_analog(gpio_t pin)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
#endif

9
cpu/stm32_common/periph/uart.c

@ -123,7 +123,8 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
assert(uart < UART_NUMOF);
for (size_t i = 0; i < len; i++) {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32F3)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
while (!(dev(uart)->ISR & USART_ISR_TXE)) {}
dev(uart)->TDR = data[i];
#else
@ -134,7 +135,8 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* make sure the function is synchronous by waiting for the transfer to
* finish */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32F3)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
while (!(dev(uart)->ISR & USART_ISR_TC)) {}
#else
while (!(dev(uart)->SR & USART_SR_TC)) {}
@ -155,7 +157,8 @@ void uart_poweroff(uart_t uart)
static inline void irq_handler(uart_t uart)
{
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32F3)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
uint32_t status = dev(uart)->ISR;

10
cpu/stm32l4/Makefile

@ -0,0 +1,10 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS += periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/stm32_common
# (file triggers compiler bug. see #5775)
SRC_NOLTO += vectors.c
include $(RIOTBASE)/Makefile.base

5
cpu/stm32l4/Makefile.include

@ -0,0 +1,5 @@
export CPU_ARCH = cortex-m4f
export CPU_FAM = stm32l4
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTCPU)/Makefile.include.cortexm_common

180
cpu/stm32l4/cpu.c

@ -0,0 +1,180 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32l4
* @{
*
* @file
* @brief Implementation of the CPU initialization
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
* @}
*/
#include <stdint.h>
#include "cpu.h"
#include "irq.h"
#include "periph_conf.h"
#include "periph/init.h"
/* make sure we have all needed information about the clock configuration */
#ifndef CLOCK_HSE
#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
#endif
#ifndef CLOCK_LSE
#error "Please provide CLOCK_LSE in your board's periph_conf.h"
#endif
#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
#error "Please provide the PLL configuration in your board's periph_conf.h"
#endif
/**
* @name PLL configuration
* @{
*/
/* figure out which input to use */
#if (CLOCK_HSE)
#define PLL_IN CLOCK_HSE
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
#define PLL_IN (48000000) /* MSI @ 48MHz */
#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
#endif
/**check configuration and get the corresponding bitfields */
#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
#error "PLL configuration: PLL M value is out of range"
#endif
#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
#error "PLL configuration: PLL N value is out of range"
#endif
#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#if (CLOCK_PLL_R == 2)
#define PLL_R (0)
#elif (CLOCK_PLL_R == 4)
#define PLL_R (RCC_PLLCFGR_PLLR_0)
#elif (CLOCK_PLL_R == 6)
#define PLL_R (RCC_PLLCFGR_PLLR_1)
#elif (CLOCK_PLL_R == 8)
#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
#else
#error "PLL configuration: PLL R value is invalid"
#endif
/** @} */
/**
* @name Deduct the needed flash wait states from the core clock frequency
* @{
*/
#if (CLOCK_CORECLOCK <= 16000000)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
#elif (CLOCK_CORECLOCK <= 32000000)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
#elif (CLOCK_CORECLOCK <= 48000000)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
#elif (CLOCK_CORECLOCK <= 64000000)
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
#else
#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
#endif
/** @} */
/**
* @brief Configure the STM32L4's clock system
*
* We use the following configuration:
* - we always enable the 32kHz low speed clock (LSI or LSE)
* - we configure the MSI clock to 48MHz (for USB and RNG) and enable it
* - if LSE present, we use it to stabilize the 48MHz MSI clock (MSIPLLEN)
* - use either MSI @ 48MHz or HSE (4 to 48MHZ) as base clock
* - we use the PLL as main clock provider
* - we don't enable any ASI clock
*
* For the computation of the PLL configuration, see defines above.
*/
static void cpu_clock_init(void)
{
/* disable any interrupts. Global interrupts could be enabled if this is
* called from some kind of bootloader... */
unsigned is = irq_disable();
RCC->CIER = 0;
/* for the duration of the configuration, we fall-back to the maximum number
* of flash wait states */
FLASH->ACR = (FLASH_ACR_LATENCY_4WS);
/* reset clock to MSI with 48MHz, disables all other clocks */
RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
/* use MSI as system clock while we do any further configuration and
* configure the AHB and APB clock dividers as configure by the board */
RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV |
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_MSI) {}
/* configure the low speed clock domain (LSE vs LSI) */
#if CLOCK_LSE
/* allow write access to backup domain */
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
PWR->CR1 |= PWR_CR1_DBP;
/* enable LSE */
RCC->BDCR = RCC_BDCR_LSEON;
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
/* disable write access to back domain when done */
PWR->CR1 &= ~(PWR_CR1_DBP);
periph_clk_dis(APB1, RCC_APB1ENR1_PWREN);
/* now we can enable the MSI PLL mode */
RCC->CR |= RCC_CR_MSIPLLEN;
while (!(RCC->CR & RCC_CR_MSIRDY)) {}
#else
RCC->CSR = RCC_CSR_LSION;
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
#endif
/* if configured: enable the HSE clock */
#if CLOCK_HSE
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#endif
/* next we configure and enable the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
/* now tell the system to use the PLL as main clock */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
/* finally we enable I+D cashes, pre-fetch, and we set the actual number of
* needed flash wait states */
FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN |
FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
irq_restore(is);
}
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* initialize the Cortex-M core */
cortexm_init();
/* initialize the clock system */
cpu_clock_init();
/* trigger static peripheral initialization */
periph_init();
}

47
cpu/stm32l4/include/cpu_conf.h

@ -0,0 +1,47 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_stm32l4 STM32L4
* @brief STM32L4 specific code
* @ingroup cpu
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Hauke Petersen <hauke.pertersen@fu-berlin.de>
*/
#ifndef STM32L4_CPU_CONF_H
#define STM32L4_CPU_CONF_H
#include "cpu_conf_common.h"
#ifdef CPU_MODEL_STM32L476RG
#include "vendor/stm32l476xx.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (82U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* STM32L4_CPU_CONF_H */
/** @} */

81
cpu/stm32l4/include/periph_cpu.h

@ -0,0 +1,81 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32l4
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Available ports
*/
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
PORT_H = 7, /**< port H */
};
#ifndef DOXYGEN
/**
* @brief Override ADC resolution values
* @{
*/
#define HAVE_ADC_RES_T
typedef enum {
ADC_RES_6BIT = (0x3 << 3), /**< ADC resolution: 6 bit */
ADC_RES_8BIT = (0x2 << 3), /**< ADC resolution: 8 bit */
ADC_RES_10BIT = (0x1 << 3), /**< ADC resolution: 10 bit */
ADC_RES_12BIT = (0x0 << 3), /**< ADC resolution: 12 bit */
ADC_RES_14BIT = (0xfe), /**< not applicable */
ADC_RES_16BIT = (0xff) /**< not applicable */
} adc_res_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief ADC line configuration values
*/
typedef struct {
gpio_t pin; /**< pin to use */
uint8_t chan; /**< internal channel the pin is connected to */
} adc_conf_t;
/**
* @brief DAC line configuration data
*/
typedef struct {
gpio_t pin; /**< pin connected to the line */
uint8_t chan; /**< DAC device used for this line */
} dac_conf_t;
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */
/** @} */

18523
cpu/stm32l4/include/vendor/stm32l476xx.h vendored

File diff suppressed because it is too large Load Diff

30
cpu/stm32l4/ldscripts/stm32l476rg.ld

@ -0,0 +1,30 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32l4
* @{
*
* @file
* @brief Memory definitions for the STM32L476RG
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32l4/periph/Makefile

@ -0,0 +1,5 @@
# define the module name
MODULE = periph
# include RIOTs generic Makefile
include $(RIOTBASE)/Makefile.base

220
cpu/stm32l4/vectors.c

@ -0,0 +1,220 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32l4
* @{
*
* @file
* @brief Interrupt vector definitions
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdint.h>
#include "vectors_cortexm.h"
/* get the start of the ISR stack as defined in the linkerscript */
extern uint32_t _estack;
/* define a local dummy handler as it needs to be in the same compilation unit
* as the alias definition */
void dummy_handler(void) {
dummy_handler_default();
}
/* Cortex-M common interrupt vectors */
WEAK_DEFAULT void isr_svc(void);
WEAK_DEFAULT void isr_pendsv(void);
WEAK_DEFAULT void isr_systick(void);
/* STM32L4 specific interrupt vectors */
WEAK_DEFAULT void isr_wwdg(void);
WEAK_DEFAULT void isr_pvd_pvm(void);
WEAK_DEFAULT void isr_tamp_stamp(void);
WEAK_DEFAULT void isr_rtc_wkup(void);
WEAK_DEFAULT void isr_flash(void);
WEAK_DEFAULT void isr_rcc(void);
WEAK_DEFAULT void isr_exti(void);
WEAK_DEFAULT void isr_dma1_channel1(void);
WEAK_DEFAULT void isr_dma1_channel2(void);
WEAK_DEFAULT void isr_dma1_channel3(void);
WEAK_DEFAULT void isr_dma1_channel4(void);
WEAK_DEFAULT void isr_dma1_channel5(void);
WEAK_DEFAULT void isr_dma1_channel6(void);
WEAK_DEFAULT void isr_dma1_channel7(void);
WEAK_DEFAULT void isr_adc1_2(void);
WEAK_DEFAULT void isr_can1_tx(void);
WEAK_DEFAULT void isr_can1_rx0(void);
WEAK_DEFAULT void isr_can1_rx1(void);
WEAK_DEFAULT void isr_can1_sce(void);
WEAK_DEFAULT void isr_tim1_brk_tim15(void);
WEAK_DEFAULT void isr_tim1_up_tim16(void);
WEAK_DEFAULT void isr_tim1_trg_com_tim17(void);
WEAK_DEFAULT void isr_tim1_cc(void);
WEAK_DEFAULT void isr_tim2(void);
WEAK_DEFAULT void isr_tim3(void);
WEAK_DEFAULT void isr_tim4(void);
WEAK_DEFAULT void isr_i2c1_ev(void);
WEAK_DEFAULT void isr_i2c1_er(void);
WEAK_DEFAULT void isr_i2c2_ev(void);
WEAK_DEFAULT void isr_i2c2_er(void);
WEAK_DEFAULT void isr_spi1(void);
WEAK_DEFAULT void isr_spi2(void);
WEAK_DEFAULT void isr_usart1(void);
WEAK_DEFAULT void isr_usart2(void);
WEAK_DEFAULT void isr_usart3(void);
WEAK_DEFAULT void isr_rtc_alarm(void);
WEAK_DEFAULT void isr_dfsdm1_flt3(void);
WEAK_DEFAULT void isr_tim8_brk(void);
WEAK_DEFAULT void isr_tim8_up(void);
WEAK_DEFAULT void isr_tim8_trg_com(void);
WEAK_DEFAULT void isr_tim8_cc(void);
WEAK_DEFAULT void isr_adc3(void);
WEAK_DEFAULT void isr_fmc(void);
WEAK_DEFAULT void isr_sdmmc1(void);
WEAK_DEFAULT void isr_tim5(void);
WEAK_DEFAULT void isr_spi3(void);
WEAK_DEFAULT void isr_uart4(void);
WEAK_DEFAULT void isr_uart5(void);
WEAK_DEFAULT void isr_tim6_dac(void);
WEAK_DEFAULT void isr_tim7(void);
WEAK_DEFAULT void isr_dma2_channel1(void);
WEAK_DEFAULT void isr_dma2_channel2(void);
WEAK_DEFAULT void isr_dma2_channel3(void);
WEAK_DEFAULT void isr_dma2_channel4(void);
WEAK_DEFAULT void isr_dma2_channel5(void);
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
WEAK_DEFAULT void isr_comp(void);
WEAK_DEFAULT void isr_lptim1(void);
WEAK_DEFAULT void isr_lptim2(void);
WEAK_DEFAULT void isr_otg_fs(void);
WEAK_DEFAULT void isr_dma2_channel6(void);
WEAK_DEFAULT void isr_dma2_channel7(void);
WEAK_DEFAULT void isr_lpuart1(void);
WEAK_DEFAULT void isr_quadspi(void);
WEAK_DEFAULT void isr_i2c3_ev(void);
WEAK_DEFAULT void isr_i2c3_er(void);
WEAK_DEFAULT void isr_sai1(void);
WEAK_DEFAULT void isr_sai2(void);
WEAK_DEFAULT void isr_swpmi1(void);
WEAK_DEFAULT void isr_tsc(void);
WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_0(void);
WEAK_DEFAULT void isr_rng(void);
WEAK_DEFAULT void isr_fpu(void);
/* interrupt vector table */
ISR_VECTORS const void *interrupt_vector[] = {
/* Exception stack pointer */
(void*) (&_estack), /* pointer to the top of the stack */
/* Cortex-M4 handlers */
(void*) reset_handler_default, /* entry point of the program */
(void*) nmi_default, /* non maskable interrupt handler */
(void*) hard_fault_default, /* hard fault exception */
(void*) mem_manage_default, /* memory manage exception */
(void*) bus_fault_default, /* bus fault exception */
(void*) usage_fault_default, /* usage fault exception */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) isr_svc, /* system call interrupt, in RIOT used for
* switching into thread context on boot */
(void*) debug_mon_default, /* debug monitor exception */
(void*) (0UL), /* Reserved */
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
* context switching is happening here */
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
/* STM specific peripheral handlers */
(void*) isr_wwdg,
(void*) isr_pvd_pvm,
(void*) isr_tamp_stamp,
(void*) isr_rtc_wkup,
(void*) isr_flash,
(void*) isr_rcc,
(void*) isr_exti,
(void*) isr_exti,
(void*) isr_exti,
(void*) isr_exti,
(void*) isr_exti,
(void*) isr_dma1_channel1,
(void*) isr_dma1_channel2,
(void*) isr_dma1_channel3,
(void*) isr_dma1_channel4,
(void*) isr_dma1_channel5,
(void*) isr_dma1_channel6,
(void*) isr_dma1_channel7,
(void*) isr_adc1_2,
(void*) isr_can1_tx,
(void*) isr_can1_rx0,
(void*) isr_can1_rx1,
(void*) isr_can1_sce,
(void*) isr_exti,
(void*) isr_tim1_brk_tim15,
(void*) isr_tim1_up_tim16,
(void*) isr_tim1_trg_com_tim17,
(void*) isr_tim1_cc,
(void*) isr_tim2,
(void*) isr_tim3,
(void*) isr_tim4,
(void*) isr_i2c1_ev,
(void*) isr_i2c1_er,
(void*) isr_i2c2_ev,
(void*) isr_i2c2_er,
(void*) isr_spi1,
(void*) isr_spi2,
(void*) isr_usart1,
(void*) isr_usart2,
(void*) isr_usart3,
(void*) isr_exti,
(void*) isr_rtc_alarm,
(void*) isr_dfsdm1_flt3,
(void*) isr_tim8_brk,
(void*) isr_tim8_up,
(void*) isr_tim8_trg_com,
(void*) isr_tim8_cc,
(void*) isr_adc3,
(void*) isr_fmc,
(void*) isr_sdmmc1,
(void*) isr_tim5,
(void*) isr_spi3,
(void*) isr_uart4,
(void*) isr_uart5,
(void*) isr_tim6_dac,
(void*) isr_tim7,
(void*) isr_dma2_channel1,
(void*) isr_dma2_channel2,
(void*) isr_dma2_channel3,
(void*) isr_dma2_channel4,
(void*) isr_dma2_channel5,
(void*) isr_dfsdm1_flt0,
(void*) isr_dfsdm1_flt1,
(void*) isr_dfsdm1_flt2,
(void*) isr_comp,
(void*) isr_lptim1,
(void*) isr_lptim2,
(void*) isr_otg_fs,
(void*) isr_dma2_channel6,
(void*) isr_dma2_channel7,
(void*) isr_lpuart1,
(void*) isr_quadspi,
(void*) isr_i2c3_ev,
(void*) isr_i2c3_er,
(void*) isr_sai1,
(void*) isr_sai2,
(void*) isr_swpmi1,
(void*) isr_tsc,
(void*) isr_lcd,
(void*) (0UL),
(void*) isr_rng,
(void*) isr_fpu
};
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