Hauke Petersen
6 years ago
13 changed files with 19126 additions and 7 deletions
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# define the module that is build
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MODULE = cpu
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# add a list of subdirectories, that should also be build
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DIRS += periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/stm32_common
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# (file triggers compiler bug. see #5775)
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SRC_NOLTO += vectors.c
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include $(RIOTBASE)/Makefile.base |
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export CPU_ARCH = cortex-m4f
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export CPU_FAM = stm32l4
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include $(RIOTCPU)/stm32_common/Makefile.include |
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include $(RIOTCPU)/Makefile.include.cortexm_common |
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/*
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* Copyright (C) 2017 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup cpu_stm32l4 |
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* @{ |
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* |
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* @file |
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* @brief Implementation of the CPU initialization |
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* |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl> |
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* @} |
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*/ |
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#include <stdint.h> |
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#include "cpu.h" |
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#include "irq.h" |
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#include "periph_conf.h" |
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#include "periph/init.h" |
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/* make sure we have all needed information about the clock configuration */ |
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#ifndef CLOCK_HSE |
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h" |
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#endif |
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#ifndef CLOCK_LSE |
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#error "Please provide CLOCK_LSE in your board's periph_conf.h" |
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#endif |
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R) |
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#error "Please provide the PLL configuration in your board's periph_conf.h" |
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#endif |
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/**
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* @name PLL configuration |
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* @{ |
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*/ |
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/* figure out which input to use */ |
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#if (CLOCK_HSE) |
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#define PLL_IN CLOCK_HSE |
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE |
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#else |
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#define PLL_IN (48000000) /* MSI @ 48MHz */ |
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI |
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#endif |
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/**check configuration and get the corresponding bitfields */ |
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8) |
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#error "PLL configuration: PLL M value is out of range" |
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#endif |
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos) |
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86) |
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#error "PLL configuration: PLL N value is out of range" |
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#endif |
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos) |
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#if (CLOCK_PLL_R == 2) |
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#define PLL_R (0) |
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#elif (CLOCK_PLL_R == 4) |
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#define PLL_R (RCC_PLLCFGR_PLLR_0) |
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#elif (CLOCK_PLL_R == 6) |
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#define PLL_R (RCC_PLLCFGR_PLLR_1) |
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#elif (CLOCK_PLL_R == 8) |
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1) |
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#else |
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#error "PLL configuration: PLL R value is invalid" |
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#endif |
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/** @} */ |
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/**
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* @name Deduct the needed flash wait states from the core clock frequency |
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* @{ |
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*/ |
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#if (CLOCK_CORECLOCK <= 16000000) |
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS |
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#elif (CLOCK_CORECLOCK <= 32000000) |
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS |
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#elif (CLOCK_CORECLOCK <= 48000000) |
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS |
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#elif (CLOCK_CORECLOCK <= 64000000) |
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS |
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#else |
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS |
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#endif |
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/** @} */ |
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/**
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* @brief Configure the STM32L4's clock system |
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* |
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* We use the following configuration: |
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* - we always enable the 32kHz low speed clock (LSI or LSE) |
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* - we configure the MSI clock to 48MHz (for USB and RNG) and enable it |
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* - if LSE present, we use it to stabilize the 48MHz MSI clock (MSIPLLEN) |
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* - use either MSI @ 48MHz or HSE (4 to 48MHZ) as base clock |
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* - we use the PLL as main clock provider |
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* - we don't enable any ASI clock |
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* |
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* For the computation of the PLL configuration, see defines above. |
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*/ |
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static void cpu_clock_init(void) |
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{ |
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */ |
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unsigned is = irq_disable(); |
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RCC->CIER = 0; |
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/* for the duration of the configuration, we fall-back to the maximum number
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* of flash wait states */ |
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FLASH->ACR = (FLASH_ACR_LATENCY_4WS); |
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/* reset clock to MSI with 48MHz, disables all other clocks */ |
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RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL); |
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while (!(RCC->CR & RCC_CR_MSIRDY)) {} |
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/* use MSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */ |
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RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV | |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV); |
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_MSI) {} |
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/* configure the low speed clock domain (LSE vs LSI) */ |
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#if CLOCK_LSE |
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/* allow write access to backup domain */ |
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periph_clk_en(APB1, RCC_APB1ENR1_PWREN); |
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PWR->CR1 |= PWR_CR1_DBP; |
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/* enable LSE */ |
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RCC->BDCR = RCC_BDCR_LSEON; |
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while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {} |
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/* disable write access to back domain when done */ |
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PWR->CR1 &= ~(PWR_CR1_DBP); |
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periph_clk_dis(APB1, RCC_APB1ENR1_PWREN); |
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/* now we can enable the MSI PLL mode */ |
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RCC->CR |= RCC_CR_MSIPLLEN; |
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while (!(RCC->CR & RCC_CR_MSIRDY)) {} |
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#else |
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RCC->CSR = RCC_CSR_LSION; |
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {} |
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#endif |
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/* if configured: enable the HSE clock */ |
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#if CLOCK_HSE |
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RCC->CR |= RCC_CR_HSEON; |
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while (!(RCC->CR & RCC_CR_HSERDY)) {} |
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#endif |
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/* next we configure and enable the PLL */ |
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN); |
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RCC->CR |= RCC_CR_PLLON; |
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while (!(RCC->CR & RCC_CR_PLLRDY)) {} |
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/* now tell the system to use the PLL as main clock */ |
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RCC->CFGR |= RCC_CFGR_SW_PLL; |
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {} |
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/* finally we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */ |
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN | |
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FLASH_ACR_PRFTEN | FLASH_WAITSTATES); |
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irq_restore(is); |
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} |
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/**
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* @brief Initialize the CPU, set IRQ priorities |
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*/ |
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void cpu_init(void) |
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{ |
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/* initialize the Cortex-M core */ |
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cortexm_init(); |
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/* initialize the clock system */ |
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cpu_clock_init(); |
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/* trigger static peripheral initialization */ |
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periph_init(); |
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} |
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@ -0,0 +1,47 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser General |
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* Public License v2.1. See the file LICENSE in the top level directory for more |
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* details. |
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*/ |
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/**
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* @defgroup cpu_stm32l4 STM32L4 |
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* @brief STM32L4 specific code |
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* @ingroup cpu |
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* @{ |
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* |
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* @file |
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* @brief Implementation specific CPU configuration options |
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* |
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* @author Hauke Petersen <hauke.pertersen@fu-berlin.de> |
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*/ |
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#ifndef STM32L4_CPU_CONF_H |
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#define STM32L4_CPU_CONF_H |
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#include "cpu_conf_common.h" |
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#ifdef CPU_MODEL_STM32L476RG |
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#include "vendor/stm32l476xx.h" |
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#endif |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/**
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* @brief ARM Cortex-M specific CPU configuration |
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* @{ |
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*/ |
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#define CPU_DEFAULT_IRQ_PRIO (1U) |
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#define CPU_IRQ_NUMOF (82U) |
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/** @} */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* STM32L4_CPU_CONF_H */ |
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/** @} */ |
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@ -0,0 +1,81 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup cpu_stm32l4 |
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* @{ |
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* |
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* @file |
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* @brief CPU specific definitions for internal peripheral handling |
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* |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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* |
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*/ |
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#ifndef PERIPH_CPU_H |
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#define PERIPH_CPU_H |
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#include "periph_cpu_common.h" |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/**
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* @brief Available ports |
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*/ |
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enum { |
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PORT_A = 0, /**< port A */ |
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PORT_B = 1, /**< port B */ |
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PORT_C = 2, /**< port C */ |
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PORT_D = 3, /**< port D */ |
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PORT_E = 4, /**< port E */ |
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PORT_F = 5, /**< port F */ |
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PORT_G = 6, /**< port G */ |
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PORT_H = 7, /**< port H */ |
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}; |
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#ifndef DOXYGEN |
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/**
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* @brief Override ADC resolution values |
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* @{ |
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*/ |
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#define HAVE_ADC_RES_T |
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typedef enum { |
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ADC_RES_6BIT = (0x3 << 3), /**< ADC resolution: 6 bit */ |
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ADC_RES_8BIT = (0x2 << 3), /**< ADC resolution: 8 bit */ |
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ADC_RES_10BIT = (0x1 << 3), /**< ADC resolution: 10 bit */ |
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ADC_RES_12BIT = (0x0 << 3), /**< ADC resolution: 12 bit */ |
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ADC_RES_14BIT = (0xfe), /**< not applicable */ |
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ADC_RES_16BIT = (0xff) /**< not applicable */ |
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} adc_res_t; |
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/** @} */ |
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#endif /* ndef DOXYGEN */ |
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/**
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* @brief ADC line configuration values |
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*/ |
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typedef struct { |
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gpio_t pin; /**< pin to use */ |
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uint8_t chan; /**< internal channel the pin is connected to */ |
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} adc_conf_t; |
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/**
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* @brief DAC line configuration data |
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*/ |
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typedef struct { |
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gpio_t pin; /**< pin connected to the line */ |
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uint8_t chan; /**< DAC device used for this line */ |
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} dac_conf_t; |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* PERIPH_CPU_H */ |
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/** @} */ |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,30 @@
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/* |
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* Copyright (C) 2017 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/** |
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* @addtogroup cpu_stm32l4 |
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* @{ |
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* |
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* @file |
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* @brief Memory definitions for the STM32L476RG |
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* |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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* |
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* @} |
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*/ |
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MEMORY |
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{ |
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K |
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K |
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cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12 |
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} |
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_cpuid_address = ORIGIN(cpuid); |
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INCLUDE cortexm_base.ld |
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@ -0,0 +1,5 @@
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# define the module name
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MODULE = periph
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# include RIOTs generic Makefile
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include $(RIOTBASE)/Makefile.base |
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@ -0,0 +1,220 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup cpu_stm32l4 |
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* @{ |
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* |
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* @file |
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* @brief Interrupt vector definitions |
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* |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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* |
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* @} |
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*/ |
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#include <stdint.h> |
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#include "vectors_cortexm.h" |
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/* get the start of the ISR stack as defined in the linkerscript */ |
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extern uint32_t _estack; |
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */ |
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void dummy_handler(void) { |
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dummy_handler_default(); |
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} |
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/* Cortex-M common interrupt vectors */ |
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WEAK_DEFAULT void isr_svc(void); |
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WEAK_DEFAULT void isr_pendsv(void); |
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WEAK_DEFAULT void isr_systick(void); |
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/* STM32L4 specific interrupt vectors */ |
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WEAK_DEFAULT void isr_wwdg(void); |
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WEAK_DEFAULT void isr_pvd_pvm(void); |
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WEAK_DEFAULT void isr_tamp_stamp(void); |
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WEAK_DEFAULT void isr_rtc_wkup(void); |
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WEAK_DEFAULT void isr_flash(void); |
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WEAK_DEFAULT void isr_rcc(void); |
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WEAK_DEFAULT void isr_exti(void); |
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WEAK_DEFAULT void isr_dma1_channel1(void); |
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WEAK_DEFAULT void isr_dma1_channel2(void); |
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WEAK_DEFAULT void isr_dma1_channel3(void); |
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WEAK_DEFAULT void isr_dma1_channel4(void); |
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WEAK_DEFAULT void isr_dma1_channel5(void); |
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WEAK_DEFAULT void isr_dma1_channel6(void); |
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WEAK_DEFAULT void isr_dma1_channel7(void); |
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WEAK_DEFAULT void isr_adc1_2(void); |
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WEAK_DEFAULT void isr_can1_tx(void); |
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WEAK_DEFAULT void isr_can1_rx0(void); |
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WEAK_DEFAULT void isr_can1_rx1(void); |
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WEAK_DEFAULT void isr_can1_sce(void); |
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WEAK_DEFAULT void isr_tim1_brk_tim15(void); |
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WEAK_DEFAULT void isr_tim1_up_tim16(void); |
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WEAK_DEFAULT void isr_tim1_trg_com_tim17(void); |
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WEAK_DEFAULT void isr_tim1_cc(void); |
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WEAK_DEFAULT void isr_tim2(void); |
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WEAK_DEFAULT void isr_tim3(void); |
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WEAK_DEFAULT void isr_tim4(void); |
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WEAK_DEFAULT void isr_i2c1_ev(void); |
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WEAK_DEFAULT void isr_i2c1_er(void); |
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WEAK_DEFAULT void isr_i2c2_ev(void); |
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WEAK_DEFAULT void isr_i2c2_er(void); |
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WEAK_DEFAULT void isr_spi1(void); |
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WEAK_DEFAULT void isr_spi2(void); |
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WEAK_DEFAULT void isr_usart1(void); |
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WEAK_DEFAULT void isr_usart2(void); |
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WEAK_DEFAULT void isr_usart3(void); |
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WEAK_DEFAULT void isr_rtc_alarm(void); |
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WEAK_DEFAULT void isr_dfsdm1_flt3(void); |
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WEAK_DEFAULT void isr_tim8_brk(void); |
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WEAK_DEFAULT void isr_tim8_up(void); |
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WEAK_DEFAULT void isr_tim8_trg_com(void); |
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WEAK_DEFAULT void isr_tim8_cc(void); |
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WEAK_DEFAULT void isr_adc3(void); |
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WEAK_DEFAULT void isr_fmc(void); |
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WEAK_DEFAULT void isr_sdmmc1(void); |
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WEAK_DEFAULT void isr_tim5(void); |
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WEAK_DEFAULT void isr_spi3(void); |
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WEAK_DEFAULT void isr_uart4(void); |
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WEAK_DEFAULT void isr_uart5(void); |
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WEAK_DEFAULT void isr_tim6_dac(void); |
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WEAK_DEFAULT void isr_tim7(void); |
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WEAK_DEFAULT void isr_dma2_channel1(void); |
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WEAK_DEFAULT void isr_dma2_channel2(void); |
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WEAK_DEFAULT void isr_dma2_channel3(void); |
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WEAK_DEFAULT void isr_dma2_channel4(void); |
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WEAK_DEFAULT void isr_dma2_channel5(void); |
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WEAK_DEFAULT void isr_dfsdm1_flt0(void); |
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WEAK_DEFAULT void isr_dfsdm1_flt1(void); |
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WEAK_DEFAULT void isr_dfsdm1_flt2(void); |
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WEAK_DEFAULT void isr_comp(void); |
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WEAK_DEFAULT void isr_lptim1(void); |
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WEAK_DEFAULT void isr_lptim2(void); |
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WEAK_DEFAULT void isr_otg_fs(void); |
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WEAK_DEFAULT void isr_dma2_channel6(void); |
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WEAK_DEFAULT void isr_dma2_channel7(void); |
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WEAK_DEFAULT void isr_lpuart1(void); |
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WEAK_DEFAULT void isr_quadspi(void); |
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WEAK_DEFAULT void isr_i2c3_ev(void); |
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WEAK_DEFAULT void isr_i2c3_er(void); |
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WEAK_DEFAULT void isr_sai1(void); |
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WEAK_DEFAULT void isr_sai2(void); |
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WEAK_DEFAULT void isr_swpmi1(void); |
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WEAK_DEFAULT void isr_tsc(void); |
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WEAK_DEFAULT void isr_lcd(void); |
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WEAK_DEFAULT void isr_0(void); |
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WEAK_DEFAULT void isr_rng(void); |
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WEAK_DEFAULT void isr_fpu(void); |
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|
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/* interrupt vector table */ |
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ISR_VECTORS const void *interrupt_vector[] = { |
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/* Exception stack pointer */ |
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(void*) (&_estack), /* pointer to the top of the stack */ |
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/* Cortex-M4 handlers */ |
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(void*) reset_handler_default, /* entry point of the program */ |
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(void*) nmi_default, /* non maskable interrupt handler */ |
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(void*) hard_fault_default, /* hard fault exception */ |
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(void*) mem_manage_default, /* memory manage exception */ |
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(void*) bus_fault_default, /* bus fault exception */ |
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(void*) usage_fault_default, /* usage fault exception */ |
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(void*) (0UL), /* Reserved */ |
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(void*) (0UL), /* Reserved */ |
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(void*) (0UL), /* Reserved */ |
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(void*) (0UL), /* Reserved */ |
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(void*) isr_svc, /* system call interrupt, in RIOT used for
|
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* switching into thread context on boot */ |
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(void*) debug_mon_default, /* debug monitor exception */ |
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(void*) (0UL), /* Reserved */ |
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(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
|
||||
* context switching is happening here */ |
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(void*) isr_systick, /* SysTick interrupt, not used in RIOT */ |
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/* STM specific peripheral handlers */ |
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(void*) isr_wwdg, |
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(void*) isr_pvd_pvm, |
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(void*) isr_tamp_stamp, |
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(void*) isr_rtc_wkup, |
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(void*) isr_flash, |
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(void*) isr_rcc, |
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(void*) isr_exti, |
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(void*) isr_exti, |
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(void*) isr_exti, |
||||
(void*) isr_exti, |
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(void*) isr_exti, |
||||
(void*) isr_dma1_channel1, |
||||
(void*) isr_dma1_channel2, |
||||
(void*) isr_dma1_channel3, |
||||
(void*) isr_dma1_channel4, |
||||
(void*) isr_dma1_channel5, |
||||
(void*) isr_dma1_channel6, |
||||
(void*) isr_dma1_channel7, |
||||
(void*) isr_adc1_2, |
||||
(void*) isr_can1_tx, |
||||
(void*) isr_can1_rx0, |
||||
(void*) isr_can1_rx1, |
||||
(void*) isr_can1_sce, |
||||
(void*) isr_exti, |
||||
(void*) isr_tim1_brk_tim15, |
||||
(void*) isr_tim1_up_tim16, |
||||
(void*) isr_tim1_trg_com_tim17, |
||||
(void*) isr_tim1_cc, |
||||
(void*) isr_tim2, |
||||
(void*) isr_tim3, |
||||
(void*) isr_tim4, |
||||
(void*) isr_i2c1_ev, |
||||
(void*) isr_i2c1_er, |
||||
(void*) isr_i2c2_ev, |
||||
(void*) isr_i2c2_er, |
||||
(void*) isr_spi1, |
||||
(void*) isr_spi2, |
||||
(void*) isr_usart1, |
||||
(void*) isr_usart2, |
||||
(void*) isr_usart3, |
||||
(void*) isr_exti, |
||||
(void*) isr_rtc_alarm, |
||||
(void*) isr_dfsdm1_flt3, |
||||
(void*) isr_tim8_brk, |
||||
(void*) isr_tim8_up, |
||||
(void*) isr_tim8_trg_com, |
||||
(void*) isr_tim8_cc, |
||||
(void*) isr_adc3, |
||||
(void*) isr_fmc, |
||||
(void*) isr_sdmmc1, |
||||
(void*) isr_tim5, |
||||
(void*) isr_spi3, |
||||
(void*) isr_uart4, |
||||
(void*) isr_uart5, |
||||
(void*) isr_tim6_dac, |
||||
(void*) isr_tim7, |
||||
(void*) isr_dma2_channel1, |
||||
(void*) isr_dma2_channel2, |
||||
(void*) isr_dma2_channel3, |
||||
(void*) isr_dma2_channel4, |
||||
(void*) isr_dma2_channel5, |
||||
(void*) isr_dfsdm1_flt0, |
||||
(void*) isr_dfsdm1_flt1, |
||||
(void*) isr_dfsdm1_flt2, |
||||
(void*) isr_comp, |
||||
(void*) isr_lptim1, |
||||
(void*) isr_lptim2, |
||||
(void*) isr_otg_fs, |
||||
(void*) isr_dma2_channel6, |
||||
(void*) isr_dma2_channel7, |
||||
(void*) isr_lpuart1, |
||||
(void*) isr_quadspi, |
||||
(void*) isr_i2c3_ev, |
||||
(void*) isr_i2c3_er, |
||||
(void*) isr_sai1, |
||||
(void*) isr_sai2, |
||||
(void*) isr_swpmi1, |
||||
(void*) isr_tsc, |
||||
(void*) isr_lcd, |
||||
(void*) (0UL), |
||||
(void*) isr_rng, |
||||
(void*) isr_fpu |
||||
}; |
||||
Loading…
Reference in new issue