Merge pull request #7158 from OTAkeys/pr/stmclk_f4
cpu/stm32f4: implement stmclk interface for stm32f4master
Alexandre Abadie
6 years ago
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9dadb9cbaf
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because it is too large
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (16000000U) /* HSI fixed @ 16MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#ifndef P
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/* we fix P to 2 (so the PLL output equals 2 * CLOCK_CORECLOCK) */
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#define P (2U)
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#if ((P != 2) && (P != 4) && (P != 6) && (P != 8))
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#error "PLL configuration: PLL P value is invalid"
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#endif
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#endif /* P */
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/* the recommended input clock for the PLL should be 2MHz */
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#define M (PLL_IN / 2000000U)
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#if ((M < 2) || (M > 63))
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#error "PLL configuration: PLL M value is out of range"
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#endif
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/* next we multiply the input freq to 2 * CORECLOCK */
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#define N (P * CLOCK_CORECLOCK / 2000000U)
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#if ((N < 50) || (N > 432))
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#error "PLL configuration: PLL N value is out of range"
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#endif
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/* finally we need to set Q, so that the USB clock is 48MHz */
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#define Q ((P * CLOCK_CORECLOCK) / 48000000U)
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#if ((Q * 48000000U) != (P * CLOCK_CORECLOCK))
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#error "PLL configuration: USB frequency is not 48MHz"
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#endif
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/* now we get the actual bitfields */
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#define PLL_P (((P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_M (M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_Q (Q << RCC_PLLCFGR_PLLQ_Pos)
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_HSI) {}
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
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/* if configured, we need to enable the HSE clock now */
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#if (CLOCK_HSE)
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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/* now we can safely configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now that the PLL is running, we use it as system clock */
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RCC->CFGR |= (RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
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stmclk_disable_hsi();
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irq_restore(is);
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}
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void stmclk_enable_hsi(void)
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{
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RCC->CR |= (RCC_CR_HSION);
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while (!(RCC->CR & RCC_CR_HSIRDY)) {}
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}
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void stmclk_disable_hsi(void)
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{
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if ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_HSI) {
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RCC->CR &= ~(RCC_CR_HSION);
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}
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}
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void stmclk_enable_lfclk(void)
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{
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/* configure the low speed clock domain (LSE vs LSI) */
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#if CLOCK_LSE
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/* allow write access to backup domain */
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stmclk_bdp_unlock();
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/* enable LSE */
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RCC->BDCR |= RCC_BDCR_LSEON;
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while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
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/* disable write access to back domain when done */
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stmclk_bdp_lock();
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#else
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RCC->CSR |= RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
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#endif
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}
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void stmclk_disable_lfclk(void)
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{
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#if CLOCK_LSE
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stmclk_bdp_unlock();
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RCC->BDCR &= ~(RCC_BDCR_LSEON);
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stmclk_bdp_lock();
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#else
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RCC->CSR &= ~(RCC_CSR_LSION);
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#endif
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}
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void stmclk_bdp_unlock(void)
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{
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periph_clk_en(APB1, RCC_APB1ENR_PWREN);
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PWR->CR |= PWR_CR_DBP;
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}
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void stmclk_bdp_lock(void)
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{
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PWR->CR &= ~(PWR_CR_DBP);
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periph_clk_dis(APB1, RCC_APB1ENR_PWREN);
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}
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