cpu/cc2538: add periph/spi driver
Ian Martin
8 years ago
parent
34d2940afb
commit
a2ac92b2bd
@ -1,3 +1,6 @@
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export CPU_ARCH := cortex-m3
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# include common SPI functions
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USEMODULE += periph_common
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include $(RIOTCPU)/Makefile.include.cortexm_common
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@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cc2538
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* @{
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*
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* @file
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* @brief CC2538 SSI interface
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*
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* @author Ian Martin <ian@locicontrols.com>
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*/
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#ifndef CC2538_SSI_H
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#define CC2538_SSI_H
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#include "cc2538.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief SSI component registers
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*/
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typedef struct {
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union {
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cc2538_reg_t CR0; /**< SSI Control Register 0 */
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struct {
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cc2538_reg_t DSS : 4; /**< SSI data size select */
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cc2538_reg_t FRF : 2; /**< SSI frame format select */
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cc2538_reg_t SPO : 1; /**< SSI serial clock polarity */
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cc2538_reg_t SPH : 1; /**< SSI serial clock phase */
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cc2538_reg_t SCR : 8; /**< SSI serial clock rate */
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cc2538_reg_t RESERVED : 16; /**< Reserved bits */
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} CR0bits;
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};
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union {
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cc2538_reg_t CR1; /**< SSI Control Register 1 */
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struct {
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cc2538_reg_t LBM : 1; /**< SSI loop-back mode */
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cc2538_reg_t SSE : 1; /**< SSI synchronous serial port enable */
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cc2538_reg_t MS : 1; /**< SSI master and slave select */
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cc2538_reg_t SOD : 1; /**< SSI slave mode output disable */
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cc2538_reg_t RESERVED : 28; /**< Reserved bits */
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} CR1bits;
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};
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cc2538_reg_t DR; /**< SSI Data register */
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union {
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cc2538_reg_t SR; /**< SSI FIFO/busy Status Register */
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struct {
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cc2538_reg_t TFE : 1; /**< SSI transmit FIFO empty */
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cc2538_reg_t TNF : 1; /**< SSI transmit FIFO not full */
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cc2538_reg_t RNE : 1; /**< SSI receive FIFO not empty */
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cc2538_reg_t RFF : 1; /**< SSI receive FIFO full */
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cc2538_reg_t BSY : 1; /**< SSI busy bit */
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cc2538_reg_t RESERVED : 27; /**< Reserved bits */
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} SRbits;
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};
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cc2538_reg_t CPSR; /**< SSI Clock Register */
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cc2538_reg_t IM; /**< SSI Interrupt Mask register */
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cc2538_reg_t RIS; /**< SSI Raw Interrupt Status register */
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cc2538_reg_t MIS; /**< SSI Masked Interrupt Status register */
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cc2538_reg_t ICR; /**< SSI Interrupt Clear Register */
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cc2538_reg_t DMACTL; /**< SSI uDMA Control Register. */
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cc2538_reg_t CC; /**< SSI clock configuration */
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} cc2538_ssi_t;
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#define SSI0 ( (cc2538_ssi_t*)0x40008000 ) /**< SSI0 Instance */
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#define SSI1 ( (cc2538_ssi_t*)0x40009000 ) /**< SSI1 Instance */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC2538_SSI_H */
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/** @} */
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@ -0,0 +1,329 @@
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/*
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* Copyright (C) 2015 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @addtogroup driver_periph
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* @author Ian Martin <ian@locicontrols.com>
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*
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* @}
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*/
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#include <assert.h>
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#include <stdio.h>
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#include "cc2538_ssi.h"
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/spi.h"
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#include "periph_conf.h"
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#include "thread.h"
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#include "sched.h"
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/* guard file in case no SPI device is defined */
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#if SPI_NUMOF
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/* clock sources for the SSI_CC register */
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#define CS_SYS_DIV 0
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#define CS_IO_DIV 1
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#define SSI0_MASK (1 << 0)
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#define SSI1_MASK (1 << 1)
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#ifndef SPI_DATA_BITS_NUMOF
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#define SPI_DATA_BITS_NUMOF 8
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#endif
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#define spin_until(condition) while (!(condition)) thread_yield()
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/**
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* @brief Array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t locks[SPI_NUMOF] = {MUTEX_INIT};
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int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
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{
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cc2538_ssi_t* ssi = spi_config[dev].dev;
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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/* power on the SPI device */
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spi_poweron(dev);
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/* configure SCK, MISO and MOSI pin */
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spi_conf_pins(dev);
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/* Disable the SSI and configure it for SPI master mode */
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ssi->CR1 = 0;
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/* 3. Configure the SSI clock source */
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ssi->CC = CS_SYS_DIV;
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/* 4. Configure the clock prescale divisor by writing the SSI_CPSR register.
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* frequency of the SSIClk is defined by: SSIClk = SysClk / (CPSDVSR x (1 + SCR))
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*/
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const int32_t speed_lut[] = {
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[SPI_SPEED_100KHZ] = 100000 /* Hz */,
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[SPI_SPEED_400KHZ] = 400000 /* Hz */,
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[SPI_SPEED_1MHZ ] = 1000000 /* Hz */,
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[SPI_SPEED_5MHZ ] = 5000000 /* Hz */,
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[SPI_SPEED_10MHZ ] = 10000000 /* Hz */,
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};
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int32_t SysClk = sys_clock_freq();
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int32_t f_desired = speed_lut[speed];
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int32_t f_actual;
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int32_t err;
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int32_t best_err = INT32_MAX;
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int32_t div1;
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int32_t div2;
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int32_t best_div1 = 2;
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int32_t best_div2 = 1;
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/* System clock is first divided by CPSDVSR, then by SCR */
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for (div1 = 2; div1 <= 254; div1++) {
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div2 = SysClk;
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int32_t denom = div1 * f_desired;
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div2 += denom / 2;
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div2 /= denom;
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if (div2 < 1) {
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div2 = 1;
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}
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else if (div2 > 256) {
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div2 = 256;
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}
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f_actual = SysClk / (div1 * div2);
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err = f_actual - f_desired;
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if (err < 0) {
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err = -err;
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}
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if (err <= best_err) {
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best_div1 = div1;
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best_div2 = div2;
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best_err = err;
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}
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}
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ssi->CPSR = best_div1; /* CPSDVSR */
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ssi->CR0bits.SCR = best_div2 - 1; /* Serial clock rate (SCR) */
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switch (conf) {
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case SPI_CONF_FIRST_RISING:
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ssi->CR0bits.SPO = 0;
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ssi->CR0bits.SPH = 0;
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break;
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case SPI_CONF_SECOND_RISING:
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ssi->CR0bits.SPO = 0;
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ssi->CR0bits.SPH = 1;
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break;
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case SPI_CONF_FIRST_FALLING:
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ssi->CR0bits.SPO = 1;
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ssi->CR0bits.SPH = 0;
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break;
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case SPI_CONF_SECOND_FALLING:
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ssi->CR0bits.SPO = 1;
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ssi->CR0bits.SPH = 1;
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break;
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}
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ssi->CR0bits.FRF = 0; /* SPI protocol mode */
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ssi->CR0bits.DSS = SPI_DATA_BITS_NUMOF - 1; /* The data size */
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ssi->CR1bits.SSE = 1;
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return 0;
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}
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int spi_init_slave(spi_t dev, spi_conf_t conf, char(*cb)(char data))
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{
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/* slave mode is not (yet) supported */
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return -1;
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}
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int spi_conf_pins(spi_t dev)
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{
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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switch ((uintptr_t)spi_config[dev].dev) {
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case (uintptr_t)SSI0:
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IOC_PXX_SEL[spi_config[dev].mosi_pin] = SSI0_TXD;
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IOC_PXX_SEL[spi_config[dev].sck_pin ] = SSI0_CLKOUT;
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IOC_PXX_SEL[spi_config[dev].cs_pin ] = SSI0_FSSOUT;
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IOC_SSIRXD_SSI0 = spi_config[dev].miso_pin;
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break;
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case (uintptr_t)SSI1:
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IOC_PXX_SEL[spi_config[dev].mosi_pin] = SSI1_TXD;
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IOC_PXX_SEL[spi_config[dev].sck_pin ] = SSI1_CLKOUT;
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IOC_PXX_SEL[spi_config[dev].cs_pin ] = SSI1_FSSOUT;
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IOC_SSIRXD_SSI1 = spi_config[dev].miso_pin;
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break;
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}
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IOC_PXX_OVER[spi_config[dev].mosi_pin] = IOC_OVERRIDE_OE;
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IOC_PXX_OVER[spi_config[dev].sck_pin ] = IOC_OVERRIDE_OE;
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IOC_PXX_OVER[spi_config[dev].cs_pin ] = IOC_OVERRIDE_OE;
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IOC_PXX_OVER[spi_config[dev].miso_pin] = IOC_OVERRIDE_DIS;
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gpio_hardware_control(spi_config[dev].mosi_pin);
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gpio_hardware_control(spi_config[dev].miso_pin);
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gpio_hardware_control(spi_config[dev].sck_pin);
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gpio_hardware_control(spi_config[dev].cs_pin);
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return 0;
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}
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int spi_acquire(spi_t dev)
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{
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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mutex_lock(&locks[dev]);
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return 0;
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}
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int spi_release(spi_t dev)
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{
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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mutex_unlock(&locks[dev]);
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return 0;
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}
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static char ssi_flush_input(cc2538_ssi_t *ssi)
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{
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char tmp;
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while (ssi->SRbits.RNE) {
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tmp = ssi->DR;
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}
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return tmp;
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}
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int spi_transfer_byte(spi_t dev, char out, char *in)
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{
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cc2538_ssi_t* ssi = spi_config[dev].dev;
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char tmp;
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ssi_flush_input(ssi);
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/* transmit byte */
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spin_until(ssi->SRbits.TNF);
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ssi->DR = out;
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/* receive byte */
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spin_until(ssi->SRbits.RNE);
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tmp = ssi->DR;
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if (in) {
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*in = tmp;
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}
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return 1;
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}
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int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
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{
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cc2538_ssi_t* ssi = spi_config[dev].dev;
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typeof(length) tx_n = 0, rx_n = 0;
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if (dev >= SPI_NUMOF) {
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return -1;
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}
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ssi_flush_input(ssi);
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/* transmit and receive bytes */
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while (tx_n < length) {
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spin_until(ssi->SRbits.TNF || ssi->SRbits.RNE);
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if (ssi->SRbits.TNF) {
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ssi->DR = out[tx_n];
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tx_n++;
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}
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else if (ssi->SRbits.RNE) {
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assert(rx_n < length);
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in[rx_n] = ssi->DR;
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rx_n++;
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}
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}
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/* receive remaining bytes */
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while (rx_n < length) {
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spin_until(ssi->SRbits.RNE);
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assert(rx_n < length);
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in[rx_n] = ssi->DR;
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rx_n++;
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}
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return rx_n;
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}
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void spi_transmission_begin(spi_t dev, char reset_val)
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{
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/* slave mode is not (yet) supported */
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}
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void spi_poweron(spi_t dev)
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{
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switch ((uintptr_t)spi_config[dev].dev) {
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case (uintptr_t)SSI0:
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/* enable SSI0 in all three power modes */
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SYS_CTRL_RCGCSSI |= SSI0_MASK;
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SYS_CTRL_SCGCSSI |= SSI0_MASK;
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SYS_CTRL_DCGCSSI |= SSI0_MASK;
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break;
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case (uintptr_t)SSI1:
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/* enable SSI1 in all three power modes */
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SYS_CTRL_RCGCSSI |= SSI1_MASK;
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SYS_CTRL_SCGCSSI |= SSI1_MASK;
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SYS_CTRL_DCGCSSI |= SSI1_MASK;
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break;
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}
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}
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void spi_poweroff(spi_t dev)
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{
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switch ((uintptr_t)spi_config[dev].dev) {
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case (uintptr_t)SSI0:
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/* disable SSI0 in all three power modes */
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SYS_CTRL_RCGCSSI &= ~SSI0_MASK;
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SYS_CTRL_SCGCSSI &= ~SSI0_MASK;
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SYS_CTRL_DCGCSSI &= ~SSI0_MASK;
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break;
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case (uintptr_t)SSI1:
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/* disable SSI1 in all three power modes */
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SYS_CTRL_RCGCSSI &= ~SSI1_MASK;
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SYS_CTRL_SCGCSSI &= ~SSI1_MASK;
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SYS_CTRL_DCGCSSI &= ~SSI1_MASK;
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break;
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}
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}
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#endif /* SPI_NUMOF */
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