Browse Source

boards: initial import of iot-lab_M3

dev/timer
Thomas Eichinger 8 years ago
parent
commit
aaa2c2e8ba
  1. 5
      boards/iot-lab_M3/Makefile.dep
  2. 21
      boards/iot-lab_M3/Makefile.include
  3. 8
      boards/iot-lab_M3/board.c
  4. 1067
      boards/iot-lab_M3/board_init.c
  5. 4
      boards/iot-lab_M3/dist/debug.sh
  6. 2
      boards/iot-lab_M3/dist/flash.sh
  7. 2
      boards/iot-lab_M3/dist/reset.sh
  8. 35
      boards/iot-lab_M3/drivers/Makefile
  9. 160
      boards/iot-lab_M3/drivers/at86rf231_driver.c
  10. 87
      boards/iot-lab_M3/drivers/at86rf231_spi1.c
  11. 22
      boards/iot-lab_M3/drivers/iot-lab_M3-uart.c
  12. 6
      boards/iot-lab_M3/include/at86rf231_spi1.h
  13. 34
      boards/iot-lab_M3/include/board.h
  14. 179
      boards/iot-lab_M3/include/periph_conf.h
  15. 128
      boards/iot-lab_M3/system_stm32f1.c
  16. 2
      cpu/cortex-m3_common/include/cmsis_system.h
  17. 38
      cpu/cortex-m3_common/thread_arch.c
  18. 67
      cpu/cortexm_common/crash.c
  19. 2
      cpu/stm32f1/cpu.c
  20. 5
      cpu/stm32f1/hwtimer_arch.c
  21. 8
      cpu/stm32f1/include/cpu-conf.h
  22. 4
      cpu/stm32f1/include/hwtimer_cpu.h
  23. 4
      cpu/stm32f1/io_arch.c
  24. 4
      cpu/stm32f1/lpm_arch.c
  25. 535
      cpu/stm32f1/periph/gpio.c
  26. 119
      cpu/stm32f1/periph/spi.c
  27. 21
      cpu/stm32f1/periph/timer.c
  28. 15
      cpu/stm32f1/periph/uart.c
  29. 4
      cpu/stm32f1/reboot_arch.c
  30. 5
      cpu/stm32f1/startup.c
  31. 2
      cpu/stm32f1/stm32f103re_linkerscript.ld
  32. 4
      cpu/stm32f1/syscalls.c
  33. 16
      drivers/at86rf231/at86rf231.c
  34. 1
      drivers/include/at86rf231.h
  35. 7
      drivers/include/periph/timer.h
  36. 4
      examples/ccn-lite-client/Makefile
  37. 4
      examples/ccn-lite-relay/Makefile
  38. 3
      examples/hello-world/Makefile
  39. 3
      examples/ipc_pingpong/Makefile
  40. 4
      examples/riot_and_cpp/Makefile
  41. 3
      tests/thread_basic/Makefile
  42. 3
      tests/thread_exit/Makefile

5
boards/iot-lab_M3/Makefile.dep

@ -1,3 +1,4 @@
ifneq (,$(findstring at86rf231,$(USEMODULE)))
USEMODULE += at86rf231
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
USEMODULE += transceiver
endif

21
boards/iot-lab_M3/Makefile.include

@ -3,7 +3,7 @@ export CPU = stm32f1
export CPU_MODEL = stm32f103re
# set the default port
export PORT ?= /dev/ttyUSB2
export PORT ?= /dev/ttyUSB0
# define tools used for building the project
export PREFIX = arm-none-eabi-
@ -21,14 +21,14 @@ export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
export CPU_USAGE = -mcpu=cortex-m3
export FPU_USAGE =
export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
export CFLAGS += -flto -ffunction-sections -fdata-sections -fno-builtin
export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
export LINKFLAGS += -ggdb -g3 -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
# $(LINKERSCRIPT) is specified in cpu/Makefile.include
export LINKFLAGS += -T$(LINKERSCRIPT)
export OFLAGS = -O ihex
export FFLAGS = $(BINDIR)/$(APPLICATION).hex
export DEBUGGER_FLAGS = $(BINDIR)/$(APPLICATION).elf
export FFLAGS = $(HEXFILE)
export DEBUGGER_FLAGS = $(ELFFILE)
# use the nano-specs of the NewLib when available
ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
@ -36,15 +36,6 @@ export LINKFLAGS += -specs=nano.specs -lc -lnosys
endif
# export board specific includes to the global includes-listing
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ -I$(RIOTBASE)/drivers/at86rf231/include -I$(RIOTBASE)/sys/net/include
# TODO -> move this to the appropriate Makefile.dep!!!
ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
USEMODULE += transceiver
endif
# TODO -> is this needed?
TERM = miniterm.py -b 115200
include $(RIOTBOARD)/$(BOARD)/Makefile.dep

8
boards/iot-lab_M3/board.c

@ -13,7 +13,7 @@
* @file board.c
* @brief Board specific implementations for the iot-lab_M3 board
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
@ -53,13 +53,13 @@ static void leds_init(void)
{
/* green pin */
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
GPIOB->CRL = (0x3 << (5*4));
LED_GREEN_PORT->CRL = (0x3 << (LED_GREEN_PIN*4));
/* orange pin */
RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
GPIOC->CRH = (0x3 << ((10-8)*4));
LED_ORANGE_PORT->CRH = (0x3 << ((LED_ORANGE_PIN-8)*4));
/* red pin */
RCC->APB2ENR |= RCC_APB2ENR_IOPDEN;
GPIOD->CRL = (0x3 << (2*4));
LED_RED_PORT->CRL = (0x3 << (LED_RED_PIN*4));
}

1067
boards/iot-lab_M3/board_init.c

File diff suppressed because it is too large Load Diff

4
boards/iot-lab_M3/dist/debug.sh vendored

@ -10,8 +10,8 @@ BIN_FOLDER=$(dirname "${FILE}")
openocd -f "${BIN_FOLDER}/${BOARD}_jtag.cfg" \
-f "target/stm32f1x.cfg" \
-c "tcl_port 6333"
-c "telnet_port 4444"
-c "tcl_port 6333" \
-c "telnet_port 4444" \
-c "init" \
-c "targets" \
-c "reset halt"

2
boards/iot-lab_M3/dist/flash.sh vendored

@ -1,7 +1,7 @@
#!/bin/bash
if [ -L "$0" ]; then
FILE=$(readlink "$0")
FILE=$(readlink -e "$0")
else
FILE="$0"
fi

2
boards/iot-lab_M3/dist/reset.sh vendored

@ -8,7 +8,7 @@ fi
BIN_FOLDER=$(dirname "${FILE}")
openocd -f "${BIN_FOLDER}/iot-lab_m3_jtag.cfg" \
openocd -f "${BIN_FOLDER}/${BOARD}_jtag.cfg" \
-f "target/stm32f1x.cfg" \
-c "init" \
-c "reset run" \

35
boards/iot-lab_M3/drivers/Makefile

@ -1,34 +1,5 @@
SRC = $(wildcard *.c)
#BINDIR = $(RIOTBOARD)/$(BOARD)/bin/
OBJ = $(SRC:%.c=$(BINDIR)%.o)
DEP = $(SRC:%.c=$(BINDIR)%.d)
MODULE =$(BOARD)_base
INCLUDES += -I../include
INCLUDES += -I$(RIOTCPU)/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/Include
INCLUDES += -I$(RIOTCPU)/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x
INCLUDES += -I$(RIOTCPU)/STM32F10x_StdPeriph_Lib_V3.5.0/Libraries/STM32F10x_StdPeriph_Driver/inc
INCLUDES += -I$(RIOTCPU)/stm32f103rey6/include
include $(RIOTBOARD)/$(BOARD)/Makefile.include
INCLUDES += -I$(RIOTBASE)/drivers/at86rf231/include
INCLUDES += -I$(RIOTBASE)/sys/include
INCLUDES += -I$(RIOTBASE)/sys/net/include
.PHONY: $(BINDIR)iot-lab_M3_drivers.a
$(BINDIR)iot-lab_M3_drivers.a: $(OBJ)
$(AD) $(AR) rcs $(BINDIR)iot-lab_M3_base.a $(OBJ)
# pull in dependency info for *existing* .o files
-include $(OBJ:.o=.d)
# compile and generate dependency info
$(BINDIR)%.o: %.c
$(AD) $(CC) $(CFLAGS) $(INCLUDES) $(BOARDINCLUDE) $(APPLICATIONINCLUDE) $(CPUINCLUDE) -c $*.c -o $(BINDIR)$*.o
$(AD) $(CC) $(CFLAGS) $(INCLUDES) $(BOARDINCLUDE) $(APPLICATIONINCLUDE) $(CPUINCLUDE) -MM $*.c > $(BINDIR)$*.d
@printf "$(BINDIR)" | cat - $(BINDIR)$*.d > /tmp/fw_out && mv /tmp/fw_out $(BINDIR)$*.d
# remove compilation products
clean:
rm -f $(OBJ) $(DEP)
include $(RIOTBASE)/Makefile.base

160
boards/iot-lab_M3/drivers/at86rf231_driver.c

@ -1,19 +1,36 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_iot-lab_M3
* @{
*
* @file at86rf231_driver.c
* @brief Board specific implementations for the at86rf231 radio driver
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include <stdio.h>
#include <stddef.h>
#include "cpu.h"
#include "sched.h"
#include "vtimer.h"
#include "arch/thread_arch.h"
#include "periph/gpio.h"
#include "spi.h"
#include "periph_conf.h"
#include "board.h"
#include "at86rf231.h"
#include "at86rf231_spi.h"
#include "at86rf231_spi1.h"
extern volatile unsigned int sched_context_switch_request;
/*
SPI1
@ -29,25 +46,25 @@ GPIO
SLEEP : PA2 : control sleep, tx & rx state
*/
inline static void RESET_CLR(void)
static inline void RESET_CLR(void)
{
GPIOC->BRR = 1 << 1;
SPI_0_RESET_PORT->BRR = (1 << SPI_0_RESET_PIN);
}
inline static void RESET_SET(void)
static inline void RESET_SET(void)
{
GPIOC->BSRR = 1 << 1;
SPI_0_RESET_PORT->BSRR = (1 << SPI_0_RESET_PIN);
}
inline static void CSn_SET(void)
static inline void CSn_SET(void)
{
GPIOA->BSRR = 1 << 4;
SPI_0_CS_PORT->BSRR = (1 << SPI_0_CS_PIN);
}
inline static void CSn_CLR(void)
static inline void CSn_CLR(void)
{
GPIOA->BRR = 1 << 4;
SPI_0_CS_PORT->BRR = (1 << SPI_0_CS_PIN);
}
inline static void SLEEP_CLR(void)
static inline void SLEEP_CLR(void)
{
GPIOA->BRR = 1 << 2;
SPI_0_SLEEP_PORT->BRR = (1 << SPI_0_SLEEP_PIN);
}
uint8_t at86rf231_get_status(void)
@ -57,82 +74,46 @@ uint8_t at86rf231_get_status(void)
}
extern void at86rf231_rx_irq(void);
static
void enable_exti_interrupt(void)
static void enable_exti_interrupt(void)
{
// EXTI_InitTypeDef EXTI_InitStructure;
// EXTI_InitStructure.EXTI_Line = EXTI_Line4;
// EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
// EXTI_InitStructure.EXTI_LineCmd = ENABLE;
// EXTI_Init(&EXTI_InitStructure);
gpio_init_int(GPIO_6, GPIO_NOPULL, GPIO_RISING, at86rf231_rx_irq);
gpio_irq_enable(SPI_0_IRQ0_GPIO);
}
static
void disable_exti_interrupt(void)
static void disable_exti_interrupt(void)
{
// EXTI_InitTypeDef EXTI_InitStructure;
// EXTI_InitStructure.EXTI_Line = EXTI_Line4;
// EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
// EXTI_InitStructure.EXTI_LineCmd = DISABLE;
// EXTI_Init(&EXTI_InitStructure);
#warning not implemented yet
gpio_irq_disable(SPI_0_IRQ0_GPIO);
}
void at86rf231_gpio_spi_interrupts_init(void)
{
/* SPI1 init */
at86rf231_spi1_init();
/* set up GPIO pins */
/* SCLK and MOSI*/
GPIOA->CRL &= ~(0xf << (5 * 4));
GPIOA->CRL |= (0xb << (5 * 4));
GPIOA->CRL &= ~(0xf << (7 * 4));
GPIOA->CRL |= (0xb << (7 * 4));
/* MISO */
gpio_init_in(SPI_0_MISO_GPIO, GPIO_NOPULL);
/* IRQ0 : PC4, INPUT and IRQ */
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
/* SPI init */
spi_init_master(SPI_0, SPI_CONF_FIRST_RISING, 4500000);
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
// GPIO_Init(GPIOC, &GPIO_InitStructure);
gpio_init_in(GPIO_4, GPIO_NOPULL);
spi_poweron(SPI_0);
/* Enable AFIO clock */
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
/* IRQ0 */
gpio_init_in(SPI_0_IRQ0_GPIO, GPIO_NOPULL);
gpio_init_int(SPI_0_IRQ0_GPIO, GPIO_NOPULL, GPIO_RISING, at86rf231_rx_irq);
/* Connect EXTI4 Line to PC4 pin */
// GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource4);
/* Configure EXTI4 line */
enable_exti_interrupt();
/* Enable and set EXTI4 Interrupt to the lowest priority */
// NVIC_InitStructure.NVIC_IRQChannel = EXTI4_IRQn;
// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01;
// NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
// NVIC_Init(&NVIC_InitStructure);
/* Init GPIOs */
/* CS & SLEEP */
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_4;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
// GPIO_Init(GPIOA, &GPIO_InitStructure);
gpio_init_out(GPIO_2, GPIO_NOPULL);
gpio_init_out(GPIO_4, GPIO_NOPULL);
/* CS */
gpio_init_out(SPI_0_CS_GPIO, GPIO_NOPULL);
/* SLEEP */
gpio_init_out(SPI_0_SLEEP_GPIO, GPIO_NOPULL);
/* RESET */
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
gpio_init_out(SPI_0_RESET_GPIO, GPIO_NOPULL);
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
// GPIO_Init(GPIOC, &GPIO_InitStructure);
gpio_init_out(GPIO_1, GPIO_NOPULL);
}
void at86rf231_reset(void)
@ -165,17 +146,18 @@ void at86rf231_reset(void)
vtimer_usleep(10);
if (!--max_wait) {
printf("at86rf231 : ERROR : could not enter TRX_OFF mode");
printf("at86rf231 : ERROR : could not enter TRX_OFF mode\n");
break;
}
}
while ((status & AT86RF231_TRX_STATUS_MASK__TRX_STATUS) != AT86RF231_TRX_STATUS__TRX_OFF);
} while ((status & AT86RF231_TRX_STATUS_MASK__TRX_STATUS)
!= AT86RF231_TRX_STATUS__TRX_OFF);
}
void at86rf231_spi_select(void)
{
CSn_CLR();
}
void at86rf231_spi_unselect(void)
{
CSn_SET();
@ -185,28 +167,8 @@ void at86rf231_enable_interrupts(void)
{
enable_exti_interrupt();
}
void at86rf231_disable_interrupts(void)
{
disable_exti_interrupt();
}
// extern void at86rf231_rx_irq(void);
// __attribute__((naked))
// void EXTI4_IRQHandler(void)
// {
// save_context();
// if (EXTI_GetITStatus(EXTI_Line4) != RESET) {
// /* IRQ_3 (TRX_END), read Frame Buffer */
// EXTI_ClearITPendingBit(EXTI_Line4);
// at86rf231_rx_irq();
// if (sched_context_switch_request) {
// /* scheduler */
// thread_yield();
// }
// }
// restore_context();
// }

87
boards/iot-lab_M3/drivers/at86rf231_spi1.c

@ -1,66 +1,45 @@
#include <stdio.h>
#include <stddef.h>
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_iot-lab_M3
* @{
*
* @file at86rf231_spi1.c
* @brief Board specific implementations for the at86rf231 SPI interface
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "spi.h"
#include "periph_conf.h"
#include "at86rf231_spi1.h"
void at86rf231_spi1_init(void)
{
// SPI_InitTypeDef SPI_InitStructure;
/* RCC */
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
// RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
/* GPIO */
/* Configure SPI MASTER pins */
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
// GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIOA->CRL &= ~(0xf << (5 * 4));
GPIOA->CRL |= (0xB << (5 * 4));
GPIOA->CRL &= ~(0xf << (7 * 4));
GPIOA->CRL |= (0xB << (7 * 4));
/*
SPI1
SCLK : PA5
MISO : PA6
MOSI : PA7
CS : PA4
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_Init(GPIOA, &GPIO_InitStructure);
gpio_init_in(GPIO_6, GPIO_NOPULL);
/* SPI
* NOTE: APB2 is 72MHz, prescaler 16 => SPI @ 4.5 MHz, radio spi max is 7.5MHz
* Clock idle low, rising edge
*/
// SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
// SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
// SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
// SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
// SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
// SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
// SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
// SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
// SPI_InitStructure.SPI_CRCPolynomial = 7;
//SPI_Init(SPI1, &SPI_InitStructure);
#warning implement spi
/* Enable interrupt */
//SPI_I2S_ITConfig(SPI1, SPI_I2S_IT_TXE, ENABLE);
/* Enable SPI */
// SPI_Cmd(SPI1, ENABLE);
}
GPIO
IRQ0 : PC4 : Frame buff empty indicator
DIG2 : ? : RX Frame Time stamping XXX : NOT USED
Reset : PC1 : active low, enable chip
SLEEP : PA2 : control sleep, tx & rx state
*/
uint8_t at86rf231_spi_transfer_byte(uint8_t byte)
{
char ret;
spi_transfer_byte(SPI_0, byte?byte:0, byte?0:&ret );
spi_transfer_byte(SPI_0, byte, &ret);
return ret;
}

22
boards/iot-lab_M3/drivers/iot-lab_M3-uart.c

@ -1,22 +0,0 @@
/**
* Copyright (C) 2014 Oliver Hahm <oliver.hahm@inria.fr>
*
* This file subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* details.
*
* @file iot-lab_M3-uart.c
* @author Oliver Hahm <oliver.hahm@inria.fr>
*/
#include "stm32f10x.h"
#include "periph/uart.h"
int fw_puts(char *astring, int length)
{
for (int i = 0; i < length; i++) {
uart_write_blocking(UART_0, astring[i]);
}
return length;
}

6
boards/iot-lab_M3/include/at86rf231_spi1.h

@ -1,6 +0,0 @@
#ifndef AT86RF231_SPI1_H_
#define AT86RF231_SPI1_H_
void at86rf231_spi1_init(void);
#endif

34
boards/iot-lab_M3/include/board.h

@ -1,8 +1,8 @@
/*
* Copyright (C) 2014 Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
@ -50,29 +50,29 @@
* @name LED pin definitions
* @{
*/
#define LED_RED_PORT (GPIOD->ODR)
#define LED_RED_PIN (1<<2)
#define LED_GREEN_PORT (GPIOB->ODR)
#define LED_GREEN_PIN (1<<5)
#define LED_ORANGE_PORT (GPIOC->ODR)
#define LED_ORANGE_PIN (1<<10)
#define LED_RED_PORT (GPIOD)
#define LED_RED_PIN (2)
#define LED_GREEN_PORT (GPIOB)
#define LED_GREEN_PIN (5)
#define LED_ORANGE_PORT (GPIOC)
#define LED_ORANGE_PIN (10)
/** @} */
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_RED_ON (LED_RED_PORT &= ~LED_RED_PIN)
#define LED_RED_OFF (LED_RED_PORT |= LED_RED_PIN)
#define LED_RED_TOGGLE (LED_RED_PORT ^= LED_RED_PIN)
#define LED_RED_ON (LED_RED_PORT->ODR &= ~(1<<LED_RED_PIN))
#define LED_RED_OFF (LED_RED_PORT->ODR |= (1<<LED_RED_PIN))
#define LED_RED_TOGGLE (LED_RED_PORT->ODR ^= (1<<LED_RED_PIN))
#define LED_GREEN_ON (LED_GREEN_PORT &= ~LED_GREEN_PIN)
#define LED_GREEN_OFF (LED_GREEN_PORT |= LED_GREEN_PIN)
#define LED_GREEN_TOGGLE (LED_GREEN_PORT ^= LED_GREEN_PIN)
#define LED_GREEN_ON (LED_GREEN_PORT->ODR &= ~(1<<LED_GREEN_PIN))
#define LED_GREEN_OFF (LED_GREEN_PORT->ODR |= (1<<LED_GREEN_PIN))
#define LED_GREEN_TOGGLE (LED_GREEN_PORT->ODR ^= (1<<LED_GREEN_PIN))
#define LED_ORANGE_ON (LED_ORANGE_PORT &= ~LED_ORANGE_PIN)
#define LED_ORANGE_OFF (LED_ORANGE_PORT |= LED_ORANGE_PIN)
#define LED_ORANGE_TOGGLE (LED_ORANGE_PORT ^= LED_ORANGE_PIN)
#define LED_ORANGE_ON (LED_ORANGE_PORT->ODR &= ~(1<<LED_ORANGE_PIN))
#define LED_ORANGE_OFF (LED_ORANGE_PORT->ODR |= (1<<LED_ORANGE_PIN))
#define LED_ORANGE_TOGGLE (LED_ORANGE_PORT->ODR ^= (1<<LED_ORANGE_PIN))
/** @} */
/**

179
boards/iot-lab_M3/include/periph_conf.h

@ -2,7 +2,7 @@
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
@ -24,7 +24,7 @@
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 2
#define TIMER_1_EN 1
/* Timer 0 configuration */
#define TIMER_0_DEV TIM2
@ -60,6 +60,7 @@
#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
#define UART_0_IRQ USART1_IRQn
#define UART_0_ISR isr_usart1
#define UART_0_BUS_FREQ 72000000
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
@ -72,6 +73,7 @@
#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_1_IRQ USART2_IRQn
#define UART_1_ISR isr_usart2
#define UART_1_BUS_FREQ 36000000
/* UART 1 pin configuration */
#define UART_1_PORT GPIOA
#define UART_1_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
@ -82,7 +84,7 @@
/**
* @brief GPIO configuration
*/
#define GPIO_NUMOF 12
#define GPIO_NUMOF 16
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
@ -95,6 +97,10 @@
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_12_EN 1
#define GPIO_13_EN 1
#define GPIO_14_EN 1
#define GPIO_15_EN 0 /* not configured */
#define GPIO_IRQ_PRIO 1
/* IRQ config */
@ -110,83 +116,123 @@
#define GPIO_IRQ_9 GPIO_0 /* not configured */
#define GPIO_IRQ_10 GPIO_6
#define GPIO_IRQ_11 GPIO_7
#define GPIO_IRQ_12 GPIO_8
#define GPIO_IRQ_12 GPIO_4
#define GPIO_IRQ_13 GPIO_9
#define GPIO_IRQ_14 GPIO_10
#define GPIO_IRQ_15 GPIO_11
/* GPIO channel 0 config */
#define GPIO_0_PORT GPIOA /* Used for user button 1 */
#define GPIO_0_PIN 0
#define GPIO_0_PIN 3
#define GPIO_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_0_EXTI_CFG() (AFIO->EXTICR[GPIO_0_PIN>>0x02] |= (((uint32_t)0x00) << (0x04 * (GPIO_0_PIN & (uint8_t)0x03))))
#define GPIO_0_IRQ EXTI0_IRQn
#define GPIO_0_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI3_PA)
#define GPIO_0_EXTI_LINE 4
#define GPIO_0_IRQ EXTI4_IRQn
/* GPIO channel 1 config */
#define GPIO_1_PORT GPIOA
#define GPIO_1_PIN 1
#define GPIO_1_PIN 8
#define GPIO_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_1_EXTI_CFG() (AFIO->EXTICR[GPIO_1_PIN>>0x02] |= (((uint32_t)0x00) << (0x04 * (GPIO_1_PIN & (uint8_t)0x03))))
#define GPIO_1_IRQ EXTI0_IRQn
#define GPIO_1_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PA)
#define GPIO_1_EXTI_LINE 4
#define GPIO_1_IRQ EXTI4_IRQn
/* GPIO channel 2 config */
#define GPIO_2_PORT GPIOF
#define GPIO_2_PIN 4
#define GPIO_2_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPFEN)
#define GPIO_2_EXTI_CFG() (AFIO->EXTICR[GPIO_2_PIN>>0x02] |= (((uint32_t)0x05) << (0x04 * (GPIO_2_PIN & (uint8_t)0x03))))
#define GPIO_2_PORT GPIOA
#define GPIO_2_PIN 12
#define GPIO_2_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_2_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI12_PA)
#define GPIO_2_EXTI_LINE 4
#define GPIO_2_IRQ EXTI4_IRQn
/* GPIO channel 3 config */
#define GPIO_3_PORT GPIOF
#define GPIO_3_PIN 5
#define GPIO_3_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPFEN)
#define GPIO_3_EXTI_CFG() (AFIO->EXTICR[GPIO_3_PIN>>0x02] |= (((uint32_t)0x05) << (0x04 * (GPIO_3_PIN & (uint8_t)0x03))))
#define GPIO_3_PORT GPIOB
#define GPIO_3_PIN 8
#define GPIO_3_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_3_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PB)
#define GPIO_3_EXTI_LINE 4
#define GPIO_3_IRQ EXTI4_IRQn
/* GPIO channel 4 config */
#define GPIO_4_PORT GPIOF
#define GPIO_4_PIN 6
#define GPIO_4_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPFEN)
#define GPIO_4_EXTI_CFG() (AFIO->EXTICR[GPIO_3_PIN>>0x02] |= (((uint32_t)0x05) << (0x04 * (GPIO_3_PIN & (uint8_t)0x03))))
#define GPIO_4_PORT GPIOB
#define GPIO_4_PIN 9
#define GPIO_4_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_4_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI9_PB)
#define GPIO_4_EXTI_LINE 4
#define GPIO_4_IRQ EXTI4_IRQn
/* GPIO channel 5 config */
#define GPIO_5_PORT GPIOF
#define GPIO_5_PORT GPIOC
#define GPIO_5_PIN 7
#define GPIO_5_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPFEN)
#define GPIO_5_EXTI_CFG() (AFIO->EXTICR[GPIO_5_PIN>>0x02] |= (((uint32_t)0x05) << (0x04 * (GPIO_5_PIN & (uint8_t)0x03))))
#define GPIO_5_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_5_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI7_PC)
#define GPIO_5_EXTI_LINE 4
#define GPIO_5_IRQ EXTI4_IRQn
/* GPIO channel 6 config */
#define GPIO_6_PORT GPIOC
#define GPIO_6_PIN 4
#define GPIO_6_PIN 8
#define GPIO_6_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_6_EXTI_CFG() (AFIO->EXTICR[GPIO_6_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_6_PIN & (uint8_t)0x03))))
#define GPIO_6_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PC)
#define GPIO_6_EXTI_LINE 4
#define GPIO_6_IRQ EXTI3_IRQn
/* GPIO channel 7 config */
#define GPIO_7_PORT GPIOC
#define GPIO_7_PIN 11
#define GPIO_7_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_7_EXTI_CFG() (AFIO->EXTICR[GPIO_7_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_7_PIN & (uint8_t)0x03))))
#define GPIO_7_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PC)
#define GPIO_7_EXTI_LINE 4
#define GPIO_7_IRQ EXTI3_IRQn
/* GPIO channel 8 config */
#define GPIO_8_PORT GPIOC
#define GPIO_8_PIN 12
#define GPIO_8_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_8_EXTI_CFG() (AFIO->EXTICR[GPIO_8_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_8_PIN & (uint8_t)0x03))))
#define GPIO_8_IRQ EXTI3_IRQn
#define GPIO_8_PORT GPIOA
#define GPIO_8_PIN 5
#define GPIO_8_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_8_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI5_PA)
#define GPIO_8_EXTI_LINE 4
#define GPIO_8_IRQ EXTI4_IRQn
/* GPIO channel 9 config */
#define GPIO_9_PORT GPIOC
#define GPIO_9_PIN 13
#define GPIO_9_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_9_EXTI_CFG() (AFIO->EXTICR[GPIO_9_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_9_PIN & (uint8_t)0x03))))
#define GPIO_9_IRQ EXTI3_IRQn
#define GPIO_9_PORT GPIOA
#define GPIO_9_PIN 6
#define GPIO_9_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_9_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI6_PA)
#define GPIO_9_EXTI_LINE 4
#define GPIO_9_IRQ EXTI4_IRQn
/* GPIO channel 10 config */
#define GPIO_10_PORT GPIOC
#define GPIO_10_PIN 14
#define GPIO_10_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_10_EXTI_CFG() (AFIO->EXTICR[GPIO_10_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_10_PIN & (uint8_t)0x03))))
#define GPIO_10_IRQ EXTI3_IRQn
#define GPIO_10_PORT GPIOA
#define GPIO_10_PIN 7
#define GPIO_10_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_10_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI7_PA)
#define GPIO_10_EXTI_LINE 4
#define GPIO_10_IRQ EXTI4_IRQn
/* GPIO channel 11 config */
#define GPIO_11_PORT GPIOC
#define GPIO_11_PIN 15
#define GPIO_11_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_11_EXTI_CFG() (AFIO->EXTICR[GPIO_11_PIN>>0x02] |= (((uint32_t)0x02) << (0x04 * (GPIO_11_PIN & (uint8_t)0x03))))
#define GPIO_11_IRQ EXTI3_IRQn
#define GPIO_11_PORT GPIOA
#define GPIO_11_PIN 4
#define GPIO_11_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_11_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI4_PA)
#define GPIO_11_EXTI_LINE 4
#define GPIO_11_IRQ EXTI4_IRQn
/* GPIO channel 12 config */
#define GPIO_12_PORT GPIOC
#define GPIO_12_PIN 4
#define GPIO_12_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_12_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI4_PC)
#define GPIO_12_EXTI_LINE 4
#define GPIO_12_IRQ EXTI4_IRQn
/* GPIO channel 13 config */
#define GPIO_13_PORT GPIOC
#define GPIO_13_PIN 1
#define GPIO_13_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_13_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI1_PC)
#define GPIO_13_EXTI_LINE 4
#define GPIO_13_IRQ EXTI4_IRQn
/* GPIO channel 14 config */
#define GPIO_14_PORT GPIOA
#define GPIO_14_PIN 2
#define GPIO_14_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_14_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI2_PA)
#define GPIO_14_EXTI_LINE 4
#define GPIO_14_IRQ EXTI4_IRQn
/* GPIO channel 15 config */
#define GPIO_15_PORT GPIOC
#define GPIO_15_PIN 15
#define GPIO_15_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPCEN)
#define GPIO_15_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI15_PC)
#define GPIO_15_EXTI_LINE 4
#define GPIO_15_IRQ EXTI4_IRQn
/**
* @brief SPI configuration
@ -194,14 +240,43 @@
#define SPI_NUM_OF 1
#define SPI_0_EN 1
#define SPI_0_DEV SPI1
#define SPI_IRQ_0 SPI_0
#define SPI_0_BR_PRESC 16
#define SPI_0_SCLK GPIO_5_PIN
#define SPI_0_MISO GPIO_6_PIN
#define SPI_0_MOSI GPIO_7_PIN
#define SPI_0_CS GPIO_4_PIN
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define SPI_0_SCLK_GPIO GPIO_8
#define SPI_0_SCLK_PIN GPIO_8_PIN
#define SPI_0_SCLK_PORT GPIO_8_PORT
#define SPI_0_MISO_GPIO GPIO_9
#define SPI_0_MISO_PIN GPIO_9_PIN
#define SPI_0_MISO_PORT GPIO_9_PORT
#define SPI_0_MOSI_GPIO GPIO_10
#define SPI_0_MOSI_PIN GPIO_10_PIN
#define SPI_0_MOSI_PORT GPIO_10_PORT
#define SPI_0_CS_GPIO GPIO_11
#define SPI_0_CS_PIN GPIO_11_PIN
#define SPI_0_CS_PORT GPIO_11_PORT
#define SPI_0_IRQ0_GPIO GPIO_12
#define SPI_0_IRQ0_PIN GPIO_12_PIN
#define SPI_0_IRQ0_PORT GPIO_12_PORT
#define SPI_0_RESET_GPIO GPIO_13
#define SPI_0_RESET_PIN GPIO_13_PIN
#define SPI_0_RESET_PORT GPIO_13_PORT
#define SPI_0_SLEEP_GPIO GPIO_14
#define SPI_0_SLEEP_PIN GPIO_14_PIN
#define SPI_0_SLEEP_PORT GPIO_14_PORT
#define SPI_2_LINES_FULL_DUPLEX (0x0000)
#define SPI_MASTER_MODE (0x0104)
#define SPI_DATA_SIZE_8B (0x0000)
#define SPI_CPOL_LOW (0x0000)
#define SPI_CPHA_1_EDGE (0x0000)
#define SPI_NSS_SOFT (0x0200)
#define SPI_BR_PRESCALER_16 (0x0018)
#define SPI_1ST_BIT_MSB (0x0000)
#endif /* __PERIPH_CONF_H */
/** @} */

128
boards/iot-lab_M3/system_stm32f1.c

@ -0,0 +1,128 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_iot-lab_M3
* @{
*
* @file system_stm32f1.c
* @brief Board specific clock setup
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include "stm32f10x.h"
#include "board.h"
uint32_t SystemCoreClock = F_CPU;
#define VECT_TAB_OFFSET 0x0
static void set_system_clock(void)
{
volatile uint32_t startup_counter = 0, HSE_status = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSE_status = RCC->CR & RCC_CR_HSERDY;
startup_counter++;
}
while ((HSE_status == 0) && (startup_counter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
HSE_status = (uint32_t)0x01;
}
else {
HSE_status = (uint32_t)0x00;
}
if (HSE_status == (uint32_t)0x01) {
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
/* NOTE : agilefox : modified to take into account the 16MHz
crystal instead of 8MHz */
/* PLL configuration: PLLCLK = HSE / 2 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC
| RCC_CFGR_PLLXTPRE
| RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE
| RCC_CFGR_PLLXTPRE_HSE_Div2
| RCC_CFGR_PLLMULL9);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) {
}
}
else {
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
set_system_clock();
/* Vector Table Relocation in Internal FLASH. */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
}

2
cpu/cortex-m3_common/include/cmsis_system.h

@ -11,7 +11,7 @@
* @{
*
* @file
* @brief CMSIS system header definitions for the Cortex-M0
* @brief CMSIS system header definitions for the Cortex-M3
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/

38
cpu/cortex-m3_common/thread_arch.c

@ -7,10 +7,10 @@
*/
/**
* @ingroup cpu_cortexm4_common
* @ingroup cpu_cortex-m3
* @{
*
* @file
* @file thread_arch.c
* @brief Implementation of the kernel's architecture dependent thread interface
*
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
@ -25,7 +25,6 @@
#include "arch/thread_arch.h"
#include "thread.h"
#include "sched.h"
#include "thread.h"
#include "irq.h"
#include "cpu.h"
#include "kernel_internal.h"
@ -47,14 +46,7 @@ static void context_save(void);
static void context_restore(void) NORETURN;
/**
* Cortex-M knows stacks and handles register backups, so use different stack frame layout
*
* TODO: How to handle different Cortex-Ms? Code is so far valid for M3 and M4 without FPU
*
* Layout with storage of floating point registers (applicable for Cortex-M4):
* ------------------------------------------------------------------------------------------------------------------------------------
* | R0 | R1 | R2 | R3 | LR | PC | xPSR | S0 | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 | S9 | S10 | S11 | S12 | S13 | S14 | S15 | FPSCR |
* ------------------------------------------------------------------------------------------------------------------------------------
* Cortex-M3 knows stacks and handles register backups, so use different stack frame layout
*
* Layout without floating point registers:
* --------------------------------------
@ -69,37 +61,23 @@ char *thread_arch_stack_init(void *(*task_func)(void *), void *arg, void *stack_
/* marker */
stk--;
*stk = STACK_MARKER;
/* TODO: fix FPU handling for Cortex-M4 */
/*
stk--;
*stk = (unsigned int) 0;
*/
/* S0 - S15 */
/*
for (int i = 15; i >= 0; i--) {
stk--;
*stk = i;
}
*/
*stk = (uint32_t)STACK_MARKER;
/* FIXME xPSR */
stk--;
*stk = (unsigned int) 0x01000200;
*stk = (uint32_t)0x01000200;
/* program counter */
stk--;
*stk = (unsigned int) task_func;
*stk = (uint32_t)task_func;
/* link register, jumped to when thread exits */
stk--;
*stk = (unsigned int) sched_task_exit;
*stk = (uint32_t)sched_task_exit;
/* r12 */
stk--;
*stk = (unsigned int) 0;
*stk = (uint32_t) 0;
/* r1 - r3 */
for (int i = 3; i >= 1; i--) {

67
cpu/cortexm_common/crash.c

@ -1,67 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup core_util
* @{
*
* @file crash.c
* @brief Crash handling functions implementation for ARM Cortex-based MCUs
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
*/
#include "cpu.h"
#include "lpm.h"
#include "crash.h"
#include <string.h>
#include <stdio.h>
/* "public" variables holding the crash data */
char panic_str[80];
int panic_code;
/* flag preventing "recursive crash printing loop" */
static int crashed = 0;
/* WARNING: this function NEVER returns! */
NORETURN void core_panic(int crash_code, const char *message)
{
/* copy panic datas to "public" global variables */
panic_code = crash_code;
strncpy(panic_str, message, 80);
/* print panic message to console (if possible) */
if (crashed == 0) {
crashed = 1;
puts("******** SYSTEM FAILURE ********\n");
puts(message);
#if DEVELHELP
puts("******** RIOT HALTS HERE ********\n");
#else
puts("******** RIOT WILL REBOOT ********\n");
#endif
puts("\n\n");
}
/* disable watchdog and all possible sources of interrupts */
//TODO
dINT();
#if DEVELHELP
/* enter infinite loop, into deepest possible sleep mode */
while (1) {
lpm_set(LPM_OFF);
}
#else
/* DEVELHELP not set => reboot system */
(void) reboot(RB_AUTOBOOT);
#endif
/* tell the compiler that we won't return from this function
(even if we actually won't even get here...) */
UNREACHABLE();
}

2
cpu/stm32f1/cpu.c

@ -11,7 +11,7 @@
* @ingroup cpu_stm32f1
* @{
*
* @file
* @file cpu.c
* @brief Implementation of the kernel cpu functions
*
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>

5
cpu/stm32f1/hwtimer_arch.c

@ -10,7 +10,7 @@
* @ingroup cpu_stm32f1
* @{
*
* @file
* @file hwtimer_arch.c
* @brief Implementation of the kernels hwtimer interface
*
* The hardware timer implementation uses the Coretex build-in system timer as backend.
@ -20,7 +20,7 @@
* @}
*/
#include "hwtimer_arch.h"
#include "arch/hwtimer_arch.h"
#include "thread.h"
#include "board.h"
#include "periph/timer.h"
@ -72,5 +72,4 @@ unsigned long hwtimer_arch_now(void)
void irq_handler(int channel)
{
timeout_handler((short)channel);
thread_yield();
}

8
cpu/stm32f1/include/cpu-conf.h

@ -31,13 +31,13 @@
* TODO: measure and adjust for the cortex-m3
* @{
*/
#define KERNEL_CONF_STACKSIZE_PRINTF (2500)
#define KERNEL_CONF_STACKSIZE_PRINTF (1024)
#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
#define KERNEL_CONF_STACKSIZE_DEFAULT (2500)
#define KERNEL_CONF_STACKSIZE_DEFAULT (1024)
#endif
#define KERNEL_CONF_STACKSIZE_IDLE (512)
#define KERNEL_CONF_STACKSIZE_IDLE (256)
/** @} */
/**
@ -69,5 +69,7 @@ typedef enum {
void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale);
#define TRANSCEIVER_BUFFER_SIZE (3)
#endif /* __CPU_CONF_H */
/** @} */

4
cpu/stm32f1/include/hwtimer_cpu.h

@ -2,12 +2,12 @@
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f0
* @ingroup cpu_stm32f1
* @{
*
* @file hwtimer_cpu.h

4
cpu/stm32f1/io_arch.c

@ -2,7 +2,7 @@
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
@ -10,7 +10,7 @@
* @ingroup cpu_stm32f1
* @{
*
* @file
* @file io_arch.c
* @brief Implementation of the kernel's architecture dependent IO interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>

4
cpu/stm32f1/lpm_arch.c

@ -3,7 +3,7 @@
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License. See the file LICENSE in the top level directory for more
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
@ -11,7 +11,7 @@
* @ingroup cpu_stm32f1
* @{
*
* @file
* @file lpm_arch.c
* @brief Implementation of the kernel's lpm interface
*
* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>

535
cpu/stm32f1/periph/gpio.c

@ -10,7 +10,7 @@
* @ingroup cpu_stm32f1
* @{
*
* @file
* @file gpio.c
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <mail@haukepetersen.de>
@ -20,8 +20,15 @@
*/
#include "cpu.h"
#include "stm32f10x.h"
#include "periph/gpio.h"
#include "periph_conf.h"
#include "board.h"
#include "thread.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
typedef struct {
void (*cb)(void);
@ -119,6 +126,35 @@ int gpio_init_out(gpio_t dev, gpio_pp_t pullup)
pin = GPIO_11_PIN;
break;
#endif
#ifdef GPIO_12_EN
case GPIO_12:
GPIO_12_CLKEN();
port = GPIO_12_PORT;
pin = GPIO_12_PIN;
break;
#endif
#ifdef GPIO_13_EN
case GPIO_13:
GPIO_13_CLKEN();
port = GPIO_13_PORT;
pin = GPIO_13_PIN;
break;
#endif
#ifdef GPIO_14_EN
case GPIO_14:
GPIO_14_CLKEN();
port = GPIO_14_PORT;
pin = GPIO_14_PIN;
break;
#endif
#ifdef GPIO_15_EN
case GPIO_15:
GPIO_15_CLKEN();
port = GPIO_15_PORT;
pin = GPIO_15_PIN;
break;
#endif