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cpus: adapted UART implementations to cb type change

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pr/gpio
Hauke Petersen 7 years ago
parent 18ae50ad4e
commit b23cde98cf
15 changed files with 17 additions and 20 deletions
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2
cpu/ezr32wg/periph/uart.c
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@ -101,7 +101,7 @@ void uart_poweroff(uart_t dev)
static inline void rx_irq(int dev)
{
if (_uart(dev)->IF & USART_IF_RXDATAV) {
char data = (char)_uart(dev)->RXDATA;
uint8_t data = (uint8_t)_uart(dev)->RXDATA;
isr_ctx[dev].rx_cb(isr_ctx[dev].arg, data);
}
if (sched_context_switch_request) {

7
cpu/lm4f120/periph/uart.c
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@ -135,11 +135,8 @@ void isr_uart0(void)
{
while(ROM_UARTCharsAvail(UART0_BASE))
{
char cChar;
long lChar;
lChar = ROM_UARTCharGetNonBlocking(UART0_BASE);
cChar = (unsigned char)(lChar & 0xFF);
config[UART_0].rx_cb(config[UART_0].arg, cChar);
long lchar = ROM_UARTCharGetNonBlocking(UART0_BASE);
config[UART_0].rx_cb(config[UART_0].arg, (uint8_t)lchar);
}
}
if (sched_context_switch_request) {

2
cpu/lpc11u34/periph/uart.c
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@ -133,7 +133,7 @@ void uart_poweroff(uart_t uart)
void UART_0_ISR(void)
{
if (UART_0_DEV->LSR & (1 << 0)) { /* is RDR flag set? */
char data = (char)UART_0_DEV->RBR;
uint8_t data = (uint8_t)UART_0_DEV->RBR;
config[UART_0].rx_cb(config[UART_0].arg, data);
}
if (sched_context_switch_request) {

4
cpu/lpc1768/periph/uart.c
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@ -200,7 +200,7 @@ void uart_poweroff(uart_t uart)
void UART_0_ISR(void)
{
if (UART_0_DEV->LSR & (1 << 0)) { /* is RDR flag set? */
char data = (char)UART_0_DEV->RBR;
uint8_t data = (uint8_t)UART_0_DEV->RBR;
config[UART_0].rx_cb(config[UART_0].arg, data);
}
if (sched_context_switch_request) {
@ -213,7 +213,7 @@ void UART_0_ISR(void)
void UART_1_ISR(void)
{
if (UART_1_DEV->LSR & (1 << 0)) { /* is RDR flag set? */
char data = (char)UART_1_DEV->RBR;
uint8_t data = (uint8_t)UART_1_DEV->RBR;
config[UART_1].rx_cb(config[UART_1].arg, data);
}
if (sched_context_switch_request) {

2
cpu/lpc2387/periph/uart.c
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@ -84,7 +84,7 @@ void UART0_IRQHandler(void)
case UIIR_CTI_INT: /* Character Timeout Indicator */
case UIIR_RDA_INT: /* Receive Data Available */
do {
char c = (char)U0RBR;
uint8_t c = (uint8_t)U0RBR;
_rx_cb(_cb_arg, c);
} while (U0LSR & ULSR_RDR);
break;

2
cpu/msp430fxyz/periph/uart.c
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@ -204,7 +204,7 @@ ISR(UART_RX_ISR, isr_uart_0_rx)
__enter_isr();
uint8_t stat = UART_BASE->ASTAT;
char data = (char)UART_BASE->ARXBUF;
uint8_t data = (uint8_t)UART_BASE->ARXBUF;
if (stat & (USCI_ASTAT_FE | USCI_ASTAT_OE | USCI_ASTAT_PE | USCI_ASTAT_BRK)) {
/* some error which we do not handle, just do a pseudo read to reset the

2
cpu/nrf5x_common/periph/uart.c
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@ -167,7 +167,7 @@ void isr_uart0(void)
{
if (NRF_UART0->EVENTS_RXDRDY == 1) {
NRF_UART0->EVENTS_RXDRDY = 0;
char byte = (char)(NRF_UART0->RXD & 0xff);
uint8_t byte = (uint8_t)(NRF_UART0->RXD & 0xff);
uart_config.rx_cb(uart_config.arg, byte);
}
if (sched_context_switch_request) {

2
cpu/sam3/periph/uart.c
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@ -99,7 +99,7 @@ static inline void isr_handler(int num)
Uart *dev = uart_config[num].dev;
if (dev->UART_SR & UART_SR_RXRDY) {
ctx[num].rx_cb(ctx[num].arg, (char)dev->UART_RHR);
ctx[num].rx_cb(ctx[num].arg, (uint8_t)dev->UART_RHR);
}
if (sched_context_switch_request) {
thread_yield();

2
cpu/samd21/periph/uart.c
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@ -135,7 +135,7 @@ static inline void irq_handler(int dev)
if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
/* interrupt flag is cleared by reading the data register */
uart_ctx[dev].rx_cb(uart_ctx[dev].arg, (char)(uart->DATA.reg));
uart_ctx[dev].rx_cb(uart_ctx[dev].arg, (uint8_t)(uart->DATA.reg));
}
else if (uart->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
/* clear error flag */

2
cpu/saml21/periph/uart.c
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@ -136,7 +136,7 @@ static inline void irq_handler(uint8_t uartnum, SercomUsart *dev)
{
if (dev->INTFLAG.bit.RXC) {
/* cleared by reading DATA regiser */
char data = (char)dev->DATA.reg;
uint8_t data = (uint8_t)dev->DATA.reg;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
}
else if (dev->INTFLAG.bit.ERROR) {

2
cpu/stm32f0/periph/uart.c
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@ -191,7 +191,7 @@ void uart_poweroff(uart_t uart)
static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev)
{
if (dev->ISR & USART_ISR_RXNE) {
char data = (char)dev->RDR;
uint8_t data = (uint8_t)dev->RDR;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
}
else if (dev->ISR & USART_ISR_ORE) {

2
cpu/stm32f1/periph/uart.c
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@ -147,7 +147,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
static inline void irq_handler(uart_t uartnum, USART_TypeDef *dev)
{
if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR;
uint8_t data = (uint8_t)dev->DR;
config[uartnum].rx_cb(config[uartnum].arg, data);
}
else if (dev->SR & USART_SR_ORE) {

2
cpu/stm32f3/periph/uart.c
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@ -187,7 +187,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev)
{
if (dev->ISR & USART_ISR_RXNE) {
char data = (char)dev->RDR;
uint8_t data = (uint8_t)dev->RDR;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
}
else if (dev->ISR & USART_ISR_ORE) {

2
cpu/stm32f4/periph/uart.c
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@ -165,7 +165,7 @@ void uart_poweroff(uart_t uart)
static inline void irq_handler(int uart, USART_TypeDef *dev)
{
if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR;
uint8_t data = (uint8_t)dev->DR;
uart_ctx[uart].rx_cb(uart_ctx[uart].arg, data);
}
if (sched_context_switch_request) {

2
cpu/stm32l1/periph/uart.c
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@ -166,7 +166,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev)
{
if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR;
uint8_t data = (uint8_t)dev->DR;
uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data);
}
if (sched_context_switch_request) {

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