boards/nucleo-f103: adapted UART configuration

boards/nucleo-f103/include/periph_conf.h

@@ -41,6 +41,10 @@ extern "C" {
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2    /* max 36 MHz (!) */
 
+/* resulting bus clocks */
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2          (CLOCK_CORECLOCK)
+
 /* Flash latency */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2    /* for >= 72 MHz */
 /** @} */
@@ -72,41 +76,38 @@ static const timer_conf_t timer_config[] = {
  * @brief UART configuration
  * @{
  */
-#define UART_NUMOF          (3U)
-#define UART_0_EN           0
-#define UART_1_EN           1
-#define UART_2_EN           0
-#define UART_IRQ_PRIO       1
-
-/* UART 0 device configuration */
-#define UART_0_DEV          USART1
-#define UART_0_CLKEN()      (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
-#define UART_0_IRQ          USART1_IRQn
-#define UART_0_ISR          isr_usart1
-#define UART_0_BUS_FREQ     CLOCK_CORECLOCK
-/* UART 0 pin configuration */
-#define UART_0_RX_PIN       GPIO_PIN(PORT_A, 10)
-#define UART_0_TX_PIN       GPIO_PIN(PORT_A, 9)
-
-/* UART 1 device configuration */
-#define UART_1_DEV          USART2
-#define UART_1_CLKEN()      (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
-#define UART_1_IRQ          USART2_IRQn
-#define UART_1_ISR          isr_usart2
-#define UART_1_BUS_FREQ     CLOCK_CORECLOCK / 2
-/* UART 1 pin configuration */
-#define UART_1_RX_PIN       GPIO_PIN(PORT_A, 3)
-#define UART_1_TX_PIN       GPIO_PIN(PORT_A, 2)
-
-/* UART 2 device configuration */
-#define UART_2_DEV          USART3
-#define UART_2_CLKEN()      (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
-#define UART_2_IRQ          USART3_IRQn
+static const uart_conf_t uart_config[] = {
+    {
+        .dev     = USART2,
+        .rx_pin  = GPIO_PIN(PORT_A, 3),
+        .tx_pin  = GPIO_PIN(PORT_A, 2),
+        .rcc_pin = RCC_APB1ENR_USART2EN,
+        .bus     = APB1,
+        .irqn    = USART2_IRQn
+    },
+    {
+        .dev     = USART1,
+        .rx_pin  = GPIO_PIN(PORT_A, 10),
+        .tx_pin  = GPIO_PIN(PORT_A, 9),
+        .rcc_pin = RCC_APB2ENR_USART1EN,
+        .bus     = APB2,
+        .irqn    = USART1_IRQn
+    },
+    {
+        .dev     = USART3,
+        .rx_pin  = GPIO_PIN(PORT_B, 11),
+        .tx_pin  = GPIO_PIN(PORT_B, 10),
+        .rcc_pin = RCC_APB1ENR_USART3EN,
+        .bus     = APB1,
+        .irqn    = USART3_IRQn
+    }
+};
+
+#define UART_0_ISR          isr_usart2
+#define UART_1_ISR          isr_usart1
 #define UART_2_ISR          isr_usart3
-#define UART_2_BUS_FREQ     CLOCK_CORECLOCK / 2
-/* UART 2 pin configuration */
-#define UART_2_RX_PIN       GPIO_PIN(PORT_B, 11)
-#define UART_2_TX_PIN       GPIO_PIN(PORT_B, 10)
+
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
 /** @} */
 
 /**