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cpu: atmega2560: simplify periph/timer implementation

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dev/timer
Kaspar Schleiser 8 years ago
parent 7fcb2b718e
commit bd27feefec
2 changed files with 146 additions and 327 deletions
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6
boards/arduino-mega2560/include/periph_conf.h
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@ -64,6 +64,8 @@ extern "C" {
#define TIMER0_COMP_B_EN OCIE1B
#define TIMER0_COMP_C_EN OCIE1C
#define TIMER0_FREQ_16MHZ (0 << CS12) | (0 << CS11) | (1 << CS10)
#define TIMER0_FREQ_2MHZ (0 << CS12) | (1 << CS11) | (0 << CS10)
#define TIMER0_FREQ_250KHZ (0 << CS12) | (1 << CS11) | (1 << CS10)
#define TIMER0_FREQ_DISABLE (0 << CS12) | (0 << CS11) | (0 << CS10)
#define TIMER0_COMPA_ISR TIMER1_COMPA_vect
#define TIMER0_COMPB_ISR TIMER1_COMPB_vect
@ -90,6 +92,8 @@ extern "C" {
#define TIMER1_COMP_B_EN OCIE3B
#define TIMER1_COMP_C_EN OCIE3C
#define TIMER1_FREQ_16MHZ (0 << CS32) | (0 << CS31) | (1 << CS30)
#define TIMER1_FREQ_2MHZ (0 << CS32) | (1 << CS31) | (0 << CS30)
#define TIMER1_FREQ_250KHZ (0 << CS32) | (1 << CS31) | (1 << CS30)
#define TIMER1_FREQ_DISABLE (0 << CS32) | (0 << CS31) | (0 << CS30)
#define TIMER1_COMPA_ISR TIMER3_COMPA_vect
#define TIMER1_COMPB_ISR TIMER3_COMPB_vect
@ -116,6 +120,8 @@ extern "C" {
#define TIMER2_COMP_B_EN OCIE4B
#define TIMER2_COMP_C_EN OCIE4C
#define TIMER2_FREQ_16MHZ (0 << CS42) | (0 << CS41) | (1 << CS40)
#define TIMER2_FREQ_2MHZ (0 << CS42) | (1 << CS41) | (0 << CS40)
#define TIMER2_FREQ_250KHZ (0 << CS42) | (1 << CS41) | (1 << CS40)
#define TIMER2_FREQ_DISABLE (0 << CS42) | (0 << CS41) | (0 << CS40)
#define TIMER2_COMPA_ISR TIMER4_COMPA_vect
#define TIMER2_COMPB_ISR TIMER4_COMPB_vect

467
cpu/atmega2560/periph/timer.c
Unescape Escape View File

@ -26,27 +26,15 @@
#include "board.h"
#include "cpu.h"
#include "thread.h"
#include "periph/timer.h"
#include "periph_conf.h"
static inline int __set_timer(tim_t dev,
int channel,
unsigned int timeout,
unsigned int interval
);
#define IRQ_DISABLED 0x00
typedef struct {
void (*cb)(int);
volatile uint8_t ctr_a;
volatile uint8_t ctr_b;
volatile uint8_t ctr_c;
uint8_t limit;
uint16_t timeout_a;
uint16_t timeout_b;
uint16_t timeout_c;
} timer_conf_t;
/**
@ -58,17 +46,13 @@ timer_conf_t config[TIMER_NUMOF];
* @brief Setup the given timer
*
*/
int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
int timer_init(tim_t dev, unsigned int us_per_ticks, void (*callback)(int))
{
/* reject impossible ticks_per_us values */
if ((ticks_per_us > 16) && (ticks_per_us == 0)) {
/* reject impossible us_per_ticks values */
if ((us_per_ticks != 4)) {
return -1;
}
config[dev].limit = 16 / ticks_per_us;
config[dev].ctr_a = 0x00;
config[dev].ctr_b = 0x00;
config[dev].ctr_c = 0x00;
/* select the timer and enable the timer specific peripheral clocks */
switch (dev) {
@ -76,21 +60,21 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
case TIMER_0:
TIMER0_COUNTER = 0;
TIMER0_CONTROL_B |= TIMER0_FREQ_16MHZ;
TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER1_COUNTER = 0;
TIMER1_CONTROL_B |= TIMER1_FREQ_16MHZ;
TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
break;
#endif
#if TIMER_2_EN
case TIMER_2:
TIMER2_COUNTER = 0;
TIMER2_CONTROL_B |= TIMER2_FREQ_16MHZ;
TIMER2_CONTROL_B |= TIMER2_FREQ_250KHZ;
break;
#endif
@ -107,35 +91,128 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
return __set_timer(dev, channel, timer_read(dev) + timeout, timeout);
return timer_set_absolute(dev, channel, timer_read(dev) + timeout);
}
int timer_set_absolute(tim_t dev, int channel, unsigned int timeout)
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
return __set_timer(dev, channel, timeout, timeout);
unsigned state = disableIRQ();
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
switch (channel) {
case 0:
TIMER0_COMP_A = (uint16_t) value;
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_A_EN);
break;
case 1:
TIMER0_COMP_B = (uint16_t) value;
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_B_EN);
break;
case 2:
TIMER0_COMP_C = (uint16_t) value;
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_C_EN);
break;
default:
restoreIRQ(state);
return -1;
}
break;
#endif
#if TIMER_1_EN
case TIMER_1:
switch (channel) {
case 0:
TIMER1_COMP_A = (uint16_t) value;
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_A_EN);
break;
case 1:
TIMER1_COMP_B = (uint16_t) value;
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_B_EN);
break;
case 2:
TIMER1_COMP_C = (uint16_t) value;
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_C_EN);
break;
default:
restoreIRQ(state);
return -1;
}
break;
#endif
#if TIMER_2_EN
case TIMER_2:
switch (channel) {
case 0:
TIMER2_COMP_A = (uint16_t) value;
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_A_EN);
break;
case 1:
TIMER2_COMP_B = (uint16_t) value;
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_B_EN);
break;
case 2:
TIMER2_COMP_C = (uint16_t) value;
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_C_EN);
break;
default:
restoreIRQ(state);
return -1;
}
break;
#endif
case TIMER_UNDEFINED:
default:
restoreIRQ(state);
return -1;
}
/* enable interrupts for given timer */
timer_irq_enable(dev);
restoreIRQ(state);
return 1;
}
int timer_clear(tim_t dev, int channel)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
switch (channel) {
case 0:
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
config[dev].timeout_a = IRQ_DISABLED;
break;
case 1:
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
config[dev].timeout_b = IRQ_DISABLED;
break;
case 2:
TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
config[dev].timeout_c = IRQ_DISABLED;
break;
default:
@ -145,22 +222,18 @@ int timer_clear(tim_t dev, int channel)
break;
#endif
#if TIMER_1_EN
case TIMER_1:
switch (channel) {
case 0:
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
config[dev].timeout_a = IRQ_DISABLED;
break;
case 1:
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
config[dev].timeout_b = IRQ_DISABLED;
break;
case 2:
TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
config[dev].timeout_c = IRQ_DISABLED;
break;
default:
@ -176,17 +249,14 @@ int timer_clear(tim_t dev, int channel)
switch (channel) {
case 0:
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
config[dev].timeout_a = IRQ_DISABLED;
break;
case 1:
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
config[dev].timeout_b = IRQ_DISABLED;
break;
case 2:
TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
config[dev].timeout_c = IRQ_DISABLED;
break;
default:
@ -213,7 +283,7 @@ unsigned int timer_read(tim_t dev)
* Disabling interrupts globally because read from 16 Bit register can
* otherwise be messed up
*/
disableIRQ();
unsigned state = disableIRQ();
switch (dev) {
#if TIMER_0_EN
@ -238,10 +308,9 @@ unsigned int timer_read(tim_t dev)
case TIMER_UNDEFINED:
default:
value = 0;
enableIRQ();
}
enableIRQ();
restoreIRQ(state);
return value;
}
@ -278,19 +347,19 @@ void timer_start(tim_t dev)
#if TIMER_0_EN
case TIMER_0:
TIMER0_CONTROL_B |= TIMER0_FREQ_16MHZ;
TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER1_CONTROL_B |= TIMER1_FREQ_16MHZ;
TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
break;
#endif
#if TIMER_2_EN
case TIMER_2:
TIMER1_CONTROL_B |= TIMER1_FREQ_16MHZ;
TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
break;
#endif
@ -301,121 +370,35 @@ void timer_start(tim_t dev)
void timer_irq_enable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
if (config[dev].timeout_a != IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_A_EN);
}
if (config[dev].timeout_b != IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_B_EN);
}
if (config[dev].timeout_c != IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_C_EN);
}
break;
#endif
#if TIMER_1_EN
case TIMER_1:
if (config[dev].timeout_a != IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_A_EN);
}
if (config[dev].timeout_b != IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_B_EN);
}
if (config[dev].timeout_c != IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_C_EN);
}
break;
#endif
#if TIMER_2_EN
case TIMER_2:
if (config[dev].timeout_a != IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_A_EN);
}
if (config[dev].timeout_b != IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_B_EN);
}
if (config[dev].timeout_c != IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_C_EN);
}
break;
#ifdef DEVELHELP
printf("timer_irq_enable not implemented\n");
#endif
case TIMER_UNDEFINED:
break;
}
enableIRQ();
}
void timer_irq_disable(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
if (config[dev].timeout_a == IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_A_EN);
}
if (config[dev].timeout_b == IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_B_EN);
}
if (config[dev].timeout_c == IRQ_DISABLED) {
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_C_EN);
}
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_A_EN);
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_B_EN);
TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_C_EN);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
if (config[dev].timeout_a == IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_A_EN);
}
if (config[dev].timeout_b == IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_B_EN);
}
if (config[dev].timeout_c == IRQ_DISABLED) {
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_C_EN);
}
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_A_EN);
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_B_EN);
TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_C_EN);
break;
#endif
#if TIMER_2_EN
case TIMER_2:
if (config[dev].timeout_a == IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_A_EN);
}
if (config[dev].timeout_b == IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_B_EN);
}
if (config[dev].timeout_c == IRQ_DISABLED) {
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_C_EN);
}
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_A_EN);
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_B_EN);
TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_C_EN);
break;
#endif
case TIMER_UNDEFINED:
break;
}
@ -425,255 +408,85 @@ void timer_reset(tim_t dev)
{
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER0_COUNTER = 0;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER1_COUNTER = 0;
break;
#endif
#if TIMER_2_EN
case TIMER_2:
TIMER2_COUNTER = 0;
break;
#endif
case TIMER_UNDEFINED:
break;
}
}
inline int __set_timer(tim_t dev, int channel, unsigned int timeout, unsigned int interval)
static inline void _isr(int timer, int chan)
{
/*
* Disabling interrupts globally because write to 16 Bit register can
* otherwise be messed up
*/
disableIRQ();
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
switch (channel) {
case 0:
TIMER0_COMP_A = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_a = interval;
break;
case 1:
TIMER0_COMP_B = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_b = interval;
break;
case 2:
TIMER0_COMP_C = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_c = interval;
break;
default:
enableIRQ();
return -1;
}
break;
#endif
#if TIMER_1_EN
case TIMER_1:
switch (channel) {
case 0:
TIMER1_COMP_A = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_a = interval;
break;
case 1:
TIMER1_COMP_B = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_b = interval;
break;
case 2:
TIMER1_COMP_C = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_c = interval;
break;
default:
enableIRQ();
return -1;
}
break;
#endif
#if TIMER_2_EN
case TIMER_2:
switch (channel) {
case 0:
TIMER2_COMP_A = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_a = interval;
break;
__enter_isr();
timer_clear(timer, chan);
case 1:
TIMER2_COMP_B = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_b = interval;
break;
case 2:
TIMER2_COMP_C = (uint16_t) timeout * config[dev].limit;
config[dev].timeout_c = interval;
break;
default:
enableIRQ();
return -1;
}
break;
#endif
config[timer].cb(chan);
case TIMER_UNDEFINED:
default:
enableIRQ();
return -1;
if (sched_context_switch_request) {
thread_yield();
}
/* enable interrupts for given timer */
timer_irq_enable(dev);
enableIRQ();
return 1;
__exit_isr();
}
#if TIMER_0_EN
ISR(TIMER0_COMPA_ISR, ISR_BLOCK)
{
config[TIMER_0].ctr_a++;
if (config[TIMER_0].ctr_a >= config[TIMER_0].limit) {
config[TIMER_0].limit = 0;
config[TIMER_0].cb(0);
TIMER0_COMP_A = TIMER0_COMP_A + config[TIMER_0].timeout_a * config[TIMER_0].limit;
}
_isr(0, 0);
}
ISR(TIMER0_COMPB_ISR, ISR_BLOCK)
{
config[TIMER_0].ctr_b++;
if (config[TIMER_0].ctr_b >= config[TIMER_0].limit) {
config[TIMER_0].limit = 0;
config[TIMER_0].cb(1);
TIMER0_COMP_B = TIMER0_COMP_B + config[TIMER_0].timeout_b * config[TIMER_0].limit;
}
_isr(0, 1);
}
ISR(TIMER0_COMPC_ISR, ISR_BLOCK)
{
config[TIMER_0].ctr_c++;
if (config[TIMER_0].ctr_c >= config[TIMER_0].limit) {
config[TIMER_0].limit = 0;
config[TIMER_0].cb(2);
TIMER0_COMP_C = TIMER0_COMP_C + config[TIMER_0].timeout_c * config[TIMER_0].limit;
}
_isr(0, 2);
}
#endif /* TIMER_0_EN */
#if TIMER_1_EN
ISR(TIMER1_COMPA_ISR, ISR_BLOCK)
{
config[TIMER_1].ctr_a++;
if (config[TIMER_1].ctr_a >= config[TIMER_1].limit) {
config[TIMER_1].limit = 0;
config[TIMER_1].cb(0);
TIMER1_COMP_A = TIMER1_COMP_A + config[TIMER_1].timeout_a * config[TIMER_1].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(1, 0);
}
ISR(TIMER1_COMPB_ISR, ISR_BLOCK)
{
config[TIMER_1].ctr_b++;
if (config[TIMER_1].ctr_b >= config[TIMER_1].limit) {
config[TIMER_1].limit = 0;
config[TIMER_1].cb(1);
TIMER1_COMP_B = TIMER1_COMP_B + config[TIMER_1].timeout_b * config[TIMER_1].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(1, 1);
}
ISR(TIMER1_COMPC_ISR, ISR_BLOCK)
{
config[TIMER_1].ctr_c++;
if (config[TIMER_1].ctr_c >= config[TIMER_1].limit) {
config[TIMER_1].limit = 0;
config[TIMER_1].cb(2);
TIMER1_COMP_C = TIMER1_COMP_C + config[TIMER_1].timeout_c * config[TIMER_1].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(1, 2);
}
#endif /* TIMER_1_EN */
#if TIMER_2_EN
ISR(TIMER2_COMPA_ISR, ISR_BLOCK)
{
config[TIMER_2].ctr_a++;
if (config[TIMER_2].ctr_a >= config[TIMER_2].limit) {
config[TIMER_2].limit = 0;
config[TIMER_2].cb(0);
TIMER2_COMP_A = TIMER2_COMP_A + config[TIMER_2].timeout_a * config[TIMER_2].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(2, 0);
}
ISR(TIMER2_COMPB_ISR, ISR_BLOCK)
{
config[TIMER_2].ctr_b++;
if (config[TIMER_2].ctr_b >= config[TIMER_2].limit) {
config[TIMER_2].limit = 0;
config[TIMER_2].cb(1);
TIMER2_COMP_B = TIMER2_COMP_B + config[TIMER_2].timeout_b * config[TIMER_2].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(2, 1);
}
ISR(TIMER2_COMPC_ISR, ISR_BLOCK)
{
config[TIMER_2].ctr_c++;
if (config[TIMER_2].ctr_c >= config[TIMER_2].limit) {
config[TIMER_2].limit = 0;
config[TIMER_2].cb(2);
TIMER2_COMP_C = TIMER2_COMP_C + config[TIMER_2].timeout_c * config[TIMER_2].limit;
}
if (sched_context_switch_request) {
thread_yield();
}
_isr(2, 2);
}
#endif /* TIMER_2_EN */

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