drivers: add encx24j600 ethernet driver
This commit is contained in:
Kaspar Schleiser
parent
c84199ce10
commit
bd698bf574
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@ -278,3 +278,8 @@ endif
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ifneq (,$(filter hih6130,$(USEMODULE)))
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USEMODULE += vtimer
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endif
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ifneq (,$(filter encx24j600,$(USEMODULE)))
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USEMODULE += timex
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USEMODULE += vtimer
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endif
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@ -43,3 +43,6 @@ endif
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ifneq (,$(filter pcd8544,$(USEMODULE)))
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USEMODULE_INCLUDES += $(RIOTBASE)/drivers/pcd8544/include
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endif
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ifneq (,$(filter encx24j600,$(USEMODULE)))
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USEMODULE_INCLUDES += $(RIOTBASE)/drivers/encx24j600/include
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endif
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@ -0,0 +1 @@
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include $(RIOTBASE)/Makefile.base
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@ -0,0 +1,447 @@
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/*
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* Copyright (C) 2015 Ell-i open source co-operative
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* Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup driver_encx24j600
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* @{
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*
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* @file
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* @brief Internal functions for the ENCX24J600 driver
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*
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* @}
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*/
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#include <assert.h>
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#include <errno.h>
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#include "mutex.h"
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#include "encx24j600.h"
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#include "encx24j600_internal.h"
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#include "encx24j600_defines.h"
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#include "vtimer.h"
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#include "net/netdev2.h"
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#include "net/eui64.h"
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#include "net/ethernet.h"
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//#include "net/ethernet/hdr.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define ENCX24J600_SPI_SPEED SPI_SPEED_1MHZ
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#define ENCX24J600_INIT_DELAY 100000U
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#define ENC_BUFFER_START 0x0000
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#define ENC_BUFFER_SIZE 0x6000
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#define ENC_BUFFER_END 0x5FFF
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#define RX_BUFFER_START (0x5340) /* Default value */
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#define RX_BUFFER_END (ENC_BUFFER_END)
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#define TX_BUFFER_LEN (0x2000)
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#define TX_BUFFER_END (RX_BUFFER_START)
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#define TX_BUFFER_START (TX_BUFFER_END - TX_BUFFER_LEN)
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static void cmd(encx24j600_t *dev, char cmd);
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static void reg_set(encx24j600_t *dev, uint8_t reg, uint16_t value);
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static uint16_t reg_get(encx24j600_t *dev, uint8_t reg);
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static void reg_clear_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask);
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static inline int _packets_available(encx24j600_t *dev);
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static int _get_iid(netdev2_t *netdev, eui64_t *value, size_t max_len);
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static void _get_mac_addr(netdev2_t *dev, uint8_t* buf);
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/* netdev2 interface */
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static int _send(netdev2_t *netdev, const struct iovec *vector, int count);
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static int _recv(netdev2_t *netdev, char* buf, int len);
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static int _init(netdev2_t *dev);
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static void _isr(netdev2_t *dev);
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int _get(netdev2_t *dev, netopt_t opt, void *value, size_t max_len);
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int _set(netdev2_t *dev, netopt_t opt, void *value, size_t value_len);
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const static netdev2_driver_t netdev2_driver_encx24j600 = {
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.send = _send,
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.recv = _recv,
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.init = _init,
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.isr = _isr,
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.get = _get,
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.set = _set,
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};
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static inline void lock(encx24j600_t *dev) {
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mutex_lock(&dev->mutex);
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}
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static inline void unlock(encx24j600_t *dev) {
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mutex_unlock(&dev->mutex);
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}
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void encx24j600_setup(encx24j600_t *dev, spi_t spi, gpio_t cs, gpio_t int_pin)
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{
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dev->netdev.driver = &netdev2_driver_encx24j600;
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dev->spi = spi;
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dev->cs = cs;
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dev->int_pin = int_pin;
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dev->rx_next_ptr = RX_BUFFER_START;
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mutex_init(&dev->mutex);
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}
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static void encx24j600_isr(void *arg)
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{
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encx24j600_t *dev = (encx24j600_t *) arg;
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/* disable interrupt line */
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gpio_irq_disable(dev->int_pin);
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/* call netdev2 hook */
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dev->netdev.event_callback((netdev2_t*) dev, NETDEV2_EVENT_ISR, NULL);
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}
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static void _isr(netdev2_t *netdev)
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{
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encx24j600_t *dev = (encx24j600_t *) netdev;
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uint16_t eir;
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lock(dev);
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cmd(dev, CLREIE);
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eir = reg_get(dev, EIR);
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/* check & handle link state change */
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if (eir & LINKIF) {
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uint16_t estat = reg_get(dev, ESTAT);
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netdev2_event_t event = (estat & PHYLNK) ?
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NETDEV2_EVENT_LINK_DOWN :
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NETDEV2_EVENT_LINK_UP;
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netdev->event_callback(netdev, event, NULL);
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}
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/* check & handle available packets */
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if (eir & PKTIF) {
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while (_packets_available(dev)) {
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unlock(dev);
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netdev->event_callback(netdev, NETDEV2_EVENT_RX_COMPLETE,
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NULL);
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lock(dev);
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}
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}
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/* drop all flags */
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reg_clear_bits(dev, EIR, LINKIF);
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/* re-enable interrupt */
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gpio_irq_enable(dev->int_pin);
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cmd(dev, SETEIE);
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unlock(dev);
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}
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static inline void enc_spi_transfer(encx24j600_t *dev, char *out, char *in, int len)
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{
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spi_acquire(dev->spi);
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gpio_clear(dev->cs);
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spi_transfer_bytes(dev->spi, out, in, len);
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gpio_set(dev->cs);
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spi_release(dev->spi);
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}
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static inline uint16_t reg_get(encx24j600_t *dev, uint8_t reg)
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{
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char cmd[4] = { RCRU, reg, 0, 0 };
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char result[4];
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enc_spi_transfer(dev, cmd, result, 4);
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return result[2] | (result[3] << 8);
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}
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static void phy_reg_set(encx24j600_t *dev, uint8_t reg, uint16_t value) {
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reg_set(dev, MIREGADR, reg | (1<<8));
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reg_set(dev, MIWR, value);
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}
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static void cmd(encx24j600_t *dev, char cmd) {
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spi_acquire(dev->spi);
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gpio_clear(dev->cs);
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spi_transfer_byte(dev->spi, cmd, NULL);
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gpio_set(dev->cs);
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spi_release(dev->spi);
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}
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static void cmdn(encx24j600_t *dev, uint8_t cmd, char *out, char *in, int len) {
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spi_acquire(dev->spi);
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gpio_clear(dev->cs);
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spi_transfer_byte(dev->spi, cmd, NULL);
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spi_transfer_bytes(dev->spi, out, in, len);
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gpio_set(dev->cs);
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spi_release(dev->spi);
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}
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static void reg_set(encx24j600_t *dev, uint8_t reg, uint16_t value)
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{
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char cmd[4] = { WCRU, reg, value, value >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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static void reg_set_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask)
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{
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char cmd[4] = { BFSU, reg, mask, mask >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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static void reg_clear_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask)
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{
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char cmd[4] = { BFCU, reg, mask, mask >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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/*
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* @brief Read/Write to encx24j600's SRAM
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*
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* @param[in] dev ptr to encx24j600 device handle
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* @param[in] cmd either WGPDATA, RGPDATA, WRXDATA, RRXDATA, WUDADATA, RUDADATA
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* @param[in] addr SRAM address to start reading. 0xFFFF means continue from old address
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* @param ptr pointer to buffer to read from / write to
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* @param[in] len nr of bytes to read/write
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*/
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static void sram_op(encx24j600_t *dev, uint16_t cmd, uint16_t addr, char *ptr, int len)
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{
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uint16_t reg;
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char* in = NULL;
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char* out = NULL;
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/* determine pointer addr
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*
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* all SRAM access commands have an
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* offset 0x5e to their pointer registers
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* */
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reg = cmd + 0x5e;
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/* read or write? bit 1 tells us */
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if (reg & 0x2) {
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out = ptr;
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} else {
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in = ptr;
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}
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/* set pointer */
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if (addr != 0xFFFF) {
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reg_set(dev, reg, addr);
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}
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/* copy data */
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cmdn(dev, cmd, in, out, len);
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}
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static int _init(netdev2_t *encdev)
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{
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encx24j600_t *dev = (encx24j600_t *) encdev;
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DEBUG("encx24j600: starting initialization...\n");
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/* setup IO */
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gpio_init(dev->cs, GPIO_DIR_OUT, GPIO_PULLUP);
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gpio_set(dev->cs);
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gpio_init_int(dev->int_pin, GPIO_PULLUP, GPIO_FALLING, encx24j600_isr, (void*)dev);
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if (spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, ENCX24J600_SPI_SPEED) < 0) {
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return -1;
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}
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lock(dev);
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/* initialization procedure as described in data sheet (39935c.pdf) */
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do {
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do {
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vtimer_usleep(ENCX24J600_INIT_DELAY);
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reg_set(dev, EUDAST, 0x1234);
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vtimer_usleep(ENCX24J600_INIT_DELAY);
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} while (reg_get(dev, EUDAST) != 0x1234);
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while (!(reg_get(dev, ESTAT) & CLKRDY));
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/* issue System Reset */
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cmd(dev, SETETHRST);
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/* make sure initialization finalizes */
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vtimer_usleep(1000);
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} while (!(reg_get(dev, EUDAST) == 0x0000));
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/* configure flow control */
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phy_reg_set(dev, PHANA, 0x05E1);
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reg_set_bits(dev, ECON2, AUTOFC);
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/* setup receive buffer */
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reg_set(dev, ERXST, RX_BUFFER_START);
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reg_set(dev, ERXTAIL, RX_BUFFER_END);
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dev->rx_next_ptr = RX_BUFFER_START;
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/* configure receive filter to receive multicast frames */
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reg_set_bits(dev, ERXFCON, MCEN);
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/* setup interrupts */
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reg_set_bits(dev, EIE, PKTIE | LINKIE);
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cmd(dev, ENABLERX);
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cmd(dev, SETEIE);
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DEBUG("encx24j600: initialization complete.\n");
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unlock(dev);
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return 0;
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}
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static int _send(netdev2_t *netdev, const struct iovec *vector, int count) {
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encx24j600_t * dev = (encx24j600_t *) netdev;
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lock(dev);
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/* wait until previous packet has been sent */
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while ((reg_get(dev, ECON1) & TXRTS));
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/* copy packet to SRAM */
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size_t len = 0;
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for (int i = 0; i < count; i++) {
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sram_op(dev, WGPDATA, (i ? 0xFFFF : TX_BUFFER_START), vector[i].iov_base, vector[i].iov_len);
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len += vector[i].iov_len;
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}
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/* set start of TX packet and length */
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reg_set(dev, ETXST, TX_BUFFER_START);
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reg_set(dev, ETXLEN, len);
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/* initiate sending */
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cmd(dev, SETTXRTS);
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/* wait for sending to complete */
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/* (not sure if it is needed, keeping the line uncommented) */
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/*while ((reg_get(dev, ECON1) & TXRTS));*/
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unlock(dev);
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return len;
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}
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static inline int _packets_available(encx24j600_t *dev)
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{
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/* return PKTCNT (low byte of ESTAT) */
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return reg_get(dev, ESTAT) & ~0xFF00;
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}
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static void _get_mac_addr(netdev2_t *encdev, uint8_t* buf)
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{
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encx24j600_t * dev = (encx24j600_t *) encdev;
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uint16_t *addr = (uint16_t *) buf;
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lock(dev);
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addr[0] = reg_get(dev, MAADR1);
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addr[1] = reg_get(dev, MAADR2);
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addr[2] = reg_get(dev, MAADR3);
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unlock(dev);
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}
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static int _recv(netdev2_t *netdev, char* buf, int len)
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{
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encx24j600_t * dev = (encx24j600_t *) netdev;
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encx24j600_frame_hdr_t hdr;
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lock(dev);
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/* read frame header */
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sram_op(dev, RRXDATA, dev->rx_next_ptr, (char*)&hdr, sizeof(hdr));
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/* hdr.frame_len given by device contains 4 bytes checksum */
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size_t payload_len = hdr.frame_len - 4;
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if (buf) {
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/* read packet (without 4 bytes checksum) */
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sram_op(dev, RRXDATA, 0xFFFF, buf, payload_len);
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/* decrement available packet count */
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cmd(dev, SETPKTDEC);
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dev->rx_next_ptr = hdr.rx_next_ptr;
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reg_set(dev, ERXTAIL, dev->rx_next_ptr - 2);
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}
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unlock(dev);
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return payload_len;
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}
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static int _get_iid(netdev2_t *netdev, eui64_t *value, size_t max_len)
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{
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if (max_len < sizeof(eui64_t)) {
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return -EOVERFLOW;
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}
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uint8_t addr[ETHERNET_ADDR_LEN];
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_get_mac_addr(netdev, addr);
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ethernet_get_iid(value, addr);
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return sizeof(eui64_t);
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}
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int _get(netdev2_t *dev, netopt_t opt, void *value, size_t max_len)
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{
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int res = 0;
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switch (opt) {
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case NETOPT_DEVICE_TYPE:
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{
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uint16_t *tgt = (uint16_t *)value;
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*tgt = NETDEV2_TYPE_ETHERNET;
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res = 2;
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break;
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}
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case NETOPT_ADDRESS:
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if (max_len < ETHERNET_ADDR_LEN) {
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res = -EINVAL;
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}
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else {
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_get_mac_addr(dev, (uint8_t*)value);
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res = ETHERNET_ADDR_LEN;
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}
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break;
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case NETOPT_ADDR_LEN:
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case NETOPT_SRC_LEN:
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assert(max_len == 2);
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uint16_t *tgt = (uint16_t*)value;
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*tgt=6;
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res = sizeof(uint16_t);
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break;
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case NETOPT_IPV6_IID:
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return _get_iid(dev, value, max_len);
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default:
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res = -ENOTSUP;
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break;
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}
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return res;
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}
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int _set(netdev2_t *dev, netopt_t opt, void *value, size_t value_len)
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{
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int res = 0;
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switch (opt) {
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default:
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return -ENOTSUP;
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}
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return res;
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}
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@ -0,0 +1,206 @@
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/*
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* Copyright (C) 2015 Ell-i open source co-operative
|
||||
* Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup driver_encx24j600
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* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Register definitions for the ENCX24J600 Ethernet device
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*/
|
||||
|
||||
#ifndef ENCX24J600_REGS_H
|
||||
#define ENCX24J600_REGS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name SPI instruction set
|
||||
* @{
|
||||
*/
|
||||
#define RCR 0x00 /* read control register */
|
||||
#define WCR 0x04 /* write control register */
|
||||
|
||||
#define RCRU 0x20 /* read control register unbanked */
|
||||
#define WCRU 0x22 /* write control register unbanked */
|
||||
|
||||
#define BFSU 0x24 /* set bits unbanked */
|
||||
#define BFCU 0x26 /* clear bits unbanked */
|
||||
|
||||
#define RGPDATA 0x28 /* Read EGPDATA */
|
||||
#define WGPDATA 0x2a /* Write EGPDATA */
|
||||
|
||||
#define RRXDATA 0x2c /* Read ERXDATA */
|
||||
#define WRXDATA 0x2e /* Write ERXDATA */
|
||||
|
||||
#define RUDADATA 0x30 /* Read EUDADATA */
|
||||
#define WUDADATA 0x32 /* Write EUDADATA */
|
||||
|
||||
#define BFS 0x80 /* Bit Field Set */
|
||||
#define BFC 0xa0 /* Bit Field Clear */
|
||||
|
||||
#define SETETHRST 0xca /* System Reset */
|
||||
#define SETPKTDEC 0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
|
||||
#define ENABLERX 0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
|
||||
#define DISABLERX 0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
|
||||
#define SETEIE 0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
|
||||
#define CLREIE 0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
|
||||
|
||||
#define B0SEL 0xc0 /* select bank 0 */
|
||||
#define B1SEL 0xc2 /* select bank 0 */
|
||||
#define B2SEL 0xc4 /* select bank 0 */
|
||||
#define B3SEL 0xc6 /* select bank 0 */
|
||||
#define RBSEL 0xc8 /* Read Bank Select */
|
||||
|
||||
#define SETTXRTS 0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name 16bit Registers
|
||||
* @{
|
||||
*/
|
||||
#define ETXST 0x00
|
||||
#define ETXLEN 0x02
|
||||
#define ERXST 0x04
|
||||
#define ERXTAIL 0x06
|
||||
#define ERXHEAD 0x08
|
||||
#define ETXSTAT 0x12
|
||||
#define ETXWIRE 0x14
|
||||
#define EUDAST 0x16
|
||||
#define ESTAT 0x1a
|
||||
#define EIR 0x1c /* Interrupt Flag Register */
|
||||
#define ECON1 0x1e
|
||||
|
||||
#define ERXFCON 0x34 /* Receive filter control register */
|
||||
|
||||
#define MACON2 0x42
|
||||
#define MAMXFL 0x4a /* MAC maximum frame length */
|
||||
|
||||
#define MAADR3 0x60 /* MAC address byte 5&6 */
|
||||
#define MAADR2 0x62 /* MAC address byte 3&4 */
|
||||
#define MAADR1 0x64 /* MAC address byte 1&2 */
|
||||
|
||||
#define MIWR 0x66
|
||||
#define MIREGADR 0x54
|
||||
|
||||
#define ECON2 0x6e
|
||||
|
||||
#define EIE 0x72 /* Interrupt Enable Register */
|
||||
|
||||
#define EGPRDPT 0x86 /* General Purpose SRAM read pointer */
|
||||
#define EGPWRPT 0x88 /* General Purpose SRAM write pointer */
|
||||
|
||||
#define ERXRDPT 0x8a /* RX buffer read pointer */
|
||||
#define ERXWRPT 0x8c /* RX buffer write pointer */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PHY Registers
|
||||
*
|
||||
* (access with phy_reg_* functions)
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define PHCON1 0x00
|
||||
#define PHSTAT1 0x01
|
||||
#define PHANA 0x04
|
||||
#define PHANLPA 0x05
|
||||
#define PHANE 0x06
|
||||
#define PHCON2 0x11
|
||||
#define PHSTAT2 0x1b
|
||||
#define PHSTAT3 0x1f
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ESTAT bits
|
||||
* @{
|
||||
*/
|
||||
#define PHYLNK (1<<8)
|
||||
#define CLKRDY (1<<12)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ECON1 bits
|
||||
* @{
|
||||
*/
|
||||
#define RXEN (1<<0)
|
||||
#define TXRTS (1<<1)
|
||||
#define DMANOCS (1<<2)
|
||||
#define DMACSSD (1<<3)
|
||||
#define DMACPY (1<<4)
|
||||
#define DMAST (1<<5)
|
||||
#define FCOP0 (1<<6)
|
||||
#define FCOP1 (1<<7)
|
||||
#define PKTDEC (1<<8)
|
||||
#define AESOP0 (1<<9)
|
||||
#define AESOP1 (1<<10)
|
||||
#define AESST (1<<11)
|
||||
#define HASHLST (1<<12)
|
||||
#define HASHOP (1<<13)
|
||||
#define HASHEN (1<<14)
|
||||
#define MODEXST (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ECON2 bits
|
||||
* @{
|
||||
*/
|
||||
#define ETHRST (1<<4)
|
||||
#define AUTOFC (1<<7) /* automatic flow control enable bit */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EIR bits
|
||||
* @{
|
||||
*/
|
||||
#define PCFULIE (1<<0)
|
||||
#define RXABTIE (1<<1)
|
||||
#define TXABTIE (1<<2)
|
||||
#define TXIE (1<<3)
|
||||
#define DMAIE (1<<5)
|
||||
#define PKTIE (1<<6)
|
||||
#define LINKIE (1<<11)
|
||||
#define AESIE (1<<12)
|
||||
#define HASHIE (1<<13)
|
||||
#define MODEXIE (1<<14)
|
||||
#define INTIE (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EIR bits
|
||||
* @{
|
||||
*/
|
||||
#define PCFULIF (1<<0)
|
||||
#define RXABTIF (1<<1)
|
||||
#define TXABTIF (1<<2)
|
||||
#define TXIF (1<<3)
|
||||
#define DMAIF (1<<5)
|
||||
#define PKTIF (1<<6)
|
||||
#define LINKIF (1<<11)
|
||||
#define AESIF (1<<12)
|
||||
#define HASHIF (1<<13)
|
||||
#define MODEXIF (1<<14)
|
||||
#define CRYPTEN (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ERXFCON bits
|
||||
*/
|
||||
#define MCEN (1<<1)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ENCX24J600_REGS_H */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Ell-i open source co-operative
|
||||
* Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup driver_encx24j600
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Internal definitions for the ENCX24J600 Ethernet device
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*/
|
||||
|
||||
#ifndef ENCX24J600_INTERNAL_H
|
||||
#define ENCX24J600_INTERNAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief structure resembling format as sent by device
|
||||
*/
|
||||
typedef struct __attribute__((packed)) encx24j600_frame_hdr {
|
||||
uint16_t rx_next_ptr; /**< ptr to next packet whithin devices memory */
|
||||
|
||||
/* Receive Status Vector */
|
||||
uint16_t frame_len; /**< lenght of ethernet frame including 4 bytes
|
||||
checksum */
|
||||
uint32_t flags; /**< random flag field just mentioned for the
|
||||
sake of documentation completeness */
|
||||
} encx24j600_frame_hdr_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ENCX24J600_INTERNAL_H */
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup driver_encx24j600 ENCX24J600
|
||||
* @ingroup drivers
|
||||
* @brief Driver for the ENCX24J600 Ethernet Adapter
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Interface definition for the ENCX24J600 driver
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*/
|
||||
|
||||
#ifndef ENCX24J600_H
|
||||
#define ENCX24J600_H
|
||||
|
||||
#include "mutex.h"
|
||||
#include "kernel_types.h"
|
||||
#include "periph/spi.h"
|
||||
#include "periph/gpio.h"
|
||||
#include "net/netdev2.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief encx24j600 netdev2 device
|
||||
* @extends netdev2_t
|
||||
*/
|
||||
typedef struct {
|
||||
netdev2_t netdev; /**< extended netdev2 structure */
|
||||
spi_t spi; /**< SPI device the enc is connected to*/
|
||||
gpio_t cs; /**< SPI chip select pin */
|
||||
gpio_t int_pin; /**< SPI interrupt pin */
|
||||
uint16_t rx_next_ptr; /**< ptr to next packet whithin devices memory */
|
||||
mutex_t mutex; /**< mutex used to lock device access */
|
||||
} encx24j600_t;
|
||||
|
||||
/**
|
||||
* @brief Setup an encx24j600 based device state.
|
||||
*
|
||||
* This function sets SPI pins, initializes the device state structure.
|
||||
* It does not initialize the device itself.
|
||||
*
|
||||
* @param[out] dev the handle of the device to initialize
|
||||
* @param[in] spi SPI device the device is connected to
|
||||
* @param[in] cs_pin SPI chip select pin used to select the device
|
||||
* @param[in] int_pin pin the device will trigger an interrupt on
|
||||
*/
|
||||
void encx24j600_setup(encx24j600_t *dev, spi_t spi, gpio_t cs_pin, gpio_t int_pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* ENCX24J600_H */
|
||||
/** @} */
|
||||
|
|
@ -166,6 +166,11 @@ void auto_init(void)
|
|||
auto_init_at86rf2xx();
|
||||
#endif
|
||||
|
||||
#ifdef MODULE_ENCX24J600
|
||||
extern void auto_init_encx24j600(void);
|
||||
auto_init_encx24j600();
|
||||
#endif
|
||||
|
||||
#ifdef MODULE_GNRC_SLIP
|
||||
extern void auto_init_slip(void);
|
||||
auto_init_slip();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup auto_init_gnrc_netif
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Auto initialization for ENCx24j600 ethernet devices
|
||||
*
|
||||
* @author Kaspar Schleiser <kaspar@schleiser.de>
|
||||
*/
|
||||
|
||||
#ifdef MODULE_ENCX24J600
|
||||
|
||||
#define ENABLE_DEBUG (0)
|
||||
#include "debug.h"
|
||||
|
||||
#include "encx24j600.h"
|
||||
#include "net/gnrc/gnrc_netdev2_eth.h"
|
||||
|
||||
static encx24j600_t encx24j600;
|
||||
|
||||
/**
|
||||
* @brief Define stack parameters for the MAC layer thread
|
||||
* @{
|
||||
*/
|
||||
#define MAC_STACKSIZE (THREAD_STACKSIZE_DEFAULT + DEBUG_EXTRA_STACKSIZE)
|
||||
#define MAC_PRIO (THREAD_PRIORITY_MAIN - 4)
|
||||
|
||||
/**
|
||||
* @brief Stacks for the MAC layer threads
|
||||
*/
|
||||
static char _netdev2_eth_stack[MAC_STACKSIZE + DEBUG_EXTRA_STACKSIZE];
|
||||
static gnrc_netdev2_t _gnrc_encx24j600;
|
||||
|
||||
void auto_init_encx24j600(void)
|
||||
{
|
||||
DEBUG("auto_init_encx24j600(): initializing device...\n");
|
||||
/* setup netdev2 device */
|
||||
encx24j600_setup(&encx24j600, ENCX24J600_SPI, ENCX24J600_CS, ENCX24J600_INT);
|
||||
|
||||
/* initialize netdev2<->gnrc adapter state */
|
||||
gnrc_netdev2_eth_init(&_gnrc_encx24j600, (netdev2_t*)&encx24j600);
|
||||
|
||||
/* start gnrc netdev2 thread */
|
||||
gnrc_netdev2_init(_netdev2_eth_stack, MAC_STACKSIZE,
|
||||
MAC_PRIO, "gnrc_encx24j600", &_gnrc_encx24j600);
|
||||
}
|
||||
|
||||
#else
|
||||
typedef int dont_be_pedantic;
|
||||
#endif /* MODULE_ENCX24J600 */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue