boards: limifrog-v1 initial commit
parent
03b7c7349a
commit
bda86cfcd3
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MODULE =$(BOARD)_base
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include $(RIOTBASE)/Makefile.base
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += cpp
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FEATURES_MCU_GROUP = cortex_m3_2
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## the cpu to build for
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export CPU = stm32l1
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export CPU_MODEL = stm32l151rc
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# define the default port depending on the host OS
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
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# setup serial terminal
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include $(RIOTBOARD)/Makefile.include.serial
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# this board uses openocd
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include $(RIOTBOARD)/Makefile.include.openocd
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# include cortex defaults
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include $(RIOTBOARD)/Makefile.include.cortexm_common
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_limifrog-v1
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* @{
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*
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* @file
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* @brief Board specific implementations for the limifrog-v1 board
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*
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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*
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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static void leds_init(void);
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void board_init(void)
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{
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/* initialize the boards LEDs */
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leds_init();
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/* initialize the CPU */
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cpu_init();
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}
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/**
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* @brief Initialize the boards on-board LEDs
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*
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* The LED initialization is hard-coded in this function.
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* As the LED is soldered onto the board it is fixed to
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* its CPU pins.
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*
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* The red LED is connected to pin PC3
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*/
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static void leds_init(void)
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{
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/* enable clock for port GPIOC */
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RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
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/* set output speed to 50MHz */
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LED_RED_PORT->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3;
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/* set output type to push-pull */
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LED_RED_PORT->OTYPER &= ~(GPIO_OTYPER_OT_3);
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/* configure pin as general output */
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LED_RED_PORT->MODER &= ~(GPIO_MODER_MODER3);
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LED_RED_PORT->MODER |= GPIO_MODER_MODER3_0;
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/* disable pull resistors */
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LED_RED_PORT->PUPDR &= ~(GPIO_PUPDR_PUPDR3);
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/* turn all LEDs off */
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LED_RED_PORT->BRR = (1 << 3);
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}
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source [find interface/stlink-v2.cfg]
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transport select hla_swd
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set WORKAREASIZE 0x2800
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source [find target/stm32l1.cfg]
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup boards_limifrog-v1 LimiFrog Version 1
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* @ingroup boards
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* @brief Board specific files for the limifrog-v1 board.
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* @{
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*
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* @file
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* @brief Board specific definitions for the limifrog-v1 board.
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*
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Define the nominal CPU core clock in this board
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*/
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#define F_CPU CLOCK_CORECLOCK
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/** @} */
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/**
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* @name Define the UART to be used as stdio and its baudrate
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* @{
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*/
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#define STDIO UART_0
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#define STDIO_BAUDRATE (115200U)
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#define STDIO_RX_BUFSIZE (64U)
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/** @} */
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/**
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* @name Assign the hardware timer
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*/
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#define HW_TIMER TIMER_0
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/**
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* @name LED pin definitions
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* @{
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*/
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#define LED_RED_PORT (GPIOC)
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#define LED_RED_PIN (3)
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#define LED_RED_GPIO GPIO(PORT_C,3)
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/** @} */
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LED_GREEN_ON
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#define LED_GREEN_OFF
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#define LED_GREEN_TOGGLE
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#define LED_ORANGE_ON
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#define LED_ORANGE_OFF
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#define LED_ORANGE_TOGGLE
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#define LED_RED_ON (LED_RED_PORT->BSRRL = (1 << LED_RED_PIN))
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#define LED_RED_OFF (LED_RED_PORT->BSRRH = (1 << LED_RED_PIN))
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#define LED_RED_TOGGLE (LED_RED_PORT->ODR ^= (1 << LED_RED_PIN))
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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/** @} */
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_limifrog-v1
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the limifrog-v1 board
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*
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (32U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (2U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART3
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_0_CLK (CLOCK_CORECLOCK)
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#define UART_0_IRQ USART3_IRQn
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#define UART_0_ISR isr_usart3
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOC
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define UART_0_RX_PIN 11
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#define UART_0_TX_PIN 10
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART3 /* Panasonic PAN1740 BLE module */
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#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_1_CLK (CLOCK_CORECLOCK)
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#define UART_1_IRQ USART1_IRQn
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#define UART_1_ISR isr_usart1
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/* UART 1 pin configuration */
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#define UART_1_PORT GPIOA
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#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_1_RX_PIN 10
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#define UART_1_TX_PIN 9
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#define UART_1_AF 7
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/** @} */
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1 /* Densitron DD-160128FC-1a OLED display; external pins */
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_ISR isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_PORT GPIOA
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#define SPI_0_PIN_SCK 5
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#define SPI_0_PIN_MOSI 7
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#define SPI_0_PIN_MISO 6
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#define SPI_0_PIN_AF 5
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/* SPI 1 device configuration */
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#define SPI_1_DEV SPI3 /* Adesto AT45DB641E data flash */
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#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI3EN)
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#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
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#define SPI_1_IRQ SPI3_IRQn
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#define SPI_1_ISR isr_spi3
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/* SPI 1 pin configuration */
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#define SPI_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define SPI_1_PORT GPIOB
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#define SPI_1_PIN_SCK 3
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#define SPI_1_PIN_MOSI 5
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#define SPI_1_PIN_MISO 4
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#define SPI_1_PIN_AF 6
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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#define I2C_1_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_0_PORT GPIOB
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#define I2C_0_SCL_PIN 8
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#define I2C_0_SCL_AF 4
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#define I2C_0_SDA_PIN 9
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#define I2C_0_SDA_AF 4
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C2 /* ST VL6180X, ST LSM6DS3, ST LIS3MDL, ST SLPS25H */
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#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
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#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define I2C_1_EVT_IRQ I2C2_EV_IRQn
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_IRQ I2C2_ER_IRQn
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#define I2C_1_ERR_ISR isr_i2c2_er
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/* I2C 1 pin configuration */
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#define I2C_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_1_PORT GPIOB
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#define I2C_1_SCL_PIN 10
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#define I2C_1_SCL_AF 4
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#define I2C_1_SDA_PIN 11
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#define I2C_1_SDA_AF 4
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PERIPH_CONF_H */
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/** @} */
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@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_stm32l1
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* @{
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*
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* @file
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* @brief Memory definitions for the STM32L151RC
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*
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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*
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* @}
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*/
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MEMORY
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{
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
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ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
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}
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INCLUDE cortexm_base.ld
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