
11 changed files with 6 additions and 955 deletions
@ -1,5 +1,5 @@
|
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# define the module that is build
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MODULE = cpu
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# add a list of subdirectories, that should also be build
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DIRS = periph $(ATMEGA_COMMON)
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DIRS = $(ATMEGA_COMMON)
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include $(RIOTBASE)/Makefile.base |
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|
@ -1,96 +0,0 @@
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/*
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* Copyright (C) 2016 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup cpu_atmega2560 |
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* @{ |
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* |
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* @file |
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* @brief CMSIS style register definitions for the atmega2560 |
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* |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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*/ |
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#ifndef ATMEGA2560_REGS_H |
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#define ATMEGA2560_REGS_H |
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#include <avr/io.h> |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/**
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* @brief Register types |
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* @{ |
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*/ |
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#define REG8 volatile uint8_t |
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#define REG16 volatile uint16_t |
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/** @} */ |
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/**
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* @brief Timer register map |
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*/ |
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typedef struct { |
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REG8 CRA; /**< control A */ |
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REG8 CRB; /**< control B */ |
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REG8 CRC; /**< control C */ |
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REG8 reserved; /**< reserved */ |
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REG16 CNT; /**< counter */ |
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REG16 ICR; /**< input capture */ |
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REG16 OCR[3]; /**< output compare */ |
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} mega_timer_t; |
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/**
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* @brief UART register map |
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*/ |
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typedef struct { |
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REG8 CSRA; /**< control and status register A */ |
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REG8 CSRB; /**< control and status register B */ |
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REG8 CSRC; /**< control and status register C */ |
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REG8 reserved; /**< reserved */ |
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REG16 BRR; /**< baud rate register */ |
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REG8 DR; /**< data register */ |
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} mega_uart_t; |
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/**
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* @brief Base register address definitions |
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* @{ |
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*/ |
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#define MEGA_TIMER1_BASE (uint16_t *)(&TCCR1A) |
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#define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A) |
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#define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A) |
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#define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A) |
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#define MEGA_UART0_BASE ((uint16_t *)(&UCSR0A)) |
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#define MEGA_UART1_BASE ((uint16_t *)(&UCSR1A)) |
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#define MEGA_UART2_BASE ((uint16_t *)(&UCSR2A)) |
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#define MEGA_UART3_BASE ((uint16_t *)(&UCSR3A)) |
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/** @} */ |
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/**
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* @brief Peripheral instances |
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* @{ |
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*/ |
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#define MEGA_TIMER1 ((mega_timer_t *)MEGA_TIMER1_BASE) |
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#define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE) |
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#define MEGA_TIMER4 ((mega_timer_t *)MEGA_TIMER4_BASE) |
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#define MEGA_TIMER5 ((mega_timer_t *)MEGA_TIMER5_BASE) |
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#define MEGA_UART0 ((mega_uart_t *)MEGA_UART0_BASE) |
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#define MEGA_UART1 ((mega_uart_t *)MEGA_UART1_BASE) |
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#define MEGA_UART2 ((mega_uart_t *)MEGA_UART2_BASE) |
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#define MEGA_UART3 ((mega_uart_t *)MEGA_UART3_BASE) |
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/** @} */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* ATMEGA2560_REGS_H */ |
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/** @} */ |
@ -1,3 +0,0 @@
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MODULE = periph
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include $(RIOTBASE)/Makefile.base |
@ -1,257 +0,0 @@
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/*
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* Copyright (C) 2015 HAW Hamburg |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup driver_periph |
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* @{ |
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* |
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* @file |
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* @brief Low-level GPIO driver implementation for ATmega2560 |
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* |
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* @author René Herthel <rene-herthel@outlook.de> |
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* |
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* @} |
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*/ |
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#include <stdio.h> |
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#include <avr/interrupt.h> |
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#include "cpu.h" |
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#include "periph/gpio.h" |
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#include "periph_conf.h" |
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#define GPIO_BASE_PORT_A (0x20) |
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#define GPIO_OFFSET_PORT_H (0xCB) |
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#define GPIO_OFFSET_PIN_PORT (0x02) |
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#define GPIO_OFFSET_PIN_PIN (0x03) |
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#define GPIO_EXT_INT_NUMOF (8U) |
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static gpio_isr_ctx_t config[GPIO_EXT_INT_NUMOF]; |
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/**
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* @brief Extract the pin number of the given pin |
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*/ |
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static inline uint8_t _pin_num(gpio_t pin) |
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{ |
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return (pin & 0x0f); |
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} |
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/**
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* @brief Extract the port number of the given pin |
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*/ |
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static inline uint8_t _port_num(gpio_t pin) |
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{ |
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return (pin >> 4) & 0x0f; |
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} |
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/**
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* @brief Generate the PORTx address of the give pin. |
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*/ |
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static inline uint16_t _port_addr(gpio_t pin) |
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{ |
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uint8_t port_num = _port_num(pin); |
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uint16_t port_addr = port_num * GPIO_OFFSET_PIN_PIN; |
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port_addr += GPIO_BASE_PORT_A; |
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port_addr += GPIO_OFFSET_PIN_PORT; |
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if (port_num > PORT_G) { |
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port_addr += GPIO_OFFSET_PORT_H; |
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} |
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return port_addr; |
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} |
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/**
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* @brief Generate the DDRx address of the given pin |
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*/ |
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static inline uint16_t _ddr_addr(gpio_t pin) |
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{ |
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return (_port_addr(pin) - 0x01); |
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} |
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/**
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* @brief Generate the PINx address of the given pin. |
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*/ |
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static inline uint16_t _pin_addr(gpio_t pin) |
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{ |
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return (_port_addr(pin) - 0x02); |
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} |
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int gpio_init(gpio_t pin, gpio_mode_t mode) |
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{ |
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switch (mode) { |
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case GPIO_OUT: |
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_SFR_MEM8(_ddr_addr(pin)) |= (1 << _pin_num(pin)); |
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break; |
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case GPIO_IN: |
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_SFR_MEM8(_ddr_addr(pin)) &= ~(1 << _pin_num(pin)); |
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_SFR_MEM8(_port_addr(pin)) &= ~(1 << _pin_num(pin)); |
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break; |
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case GPIO_IN_PU: |
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_SFR_MEM8(_port_addr(pin)) |= (1 << _pin_num(pin)); |
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break; |
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default: |
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return -1; |
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} |
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return 0; |
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} |
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, |
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gpio_cb_t cb, void *arg) |
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{ |
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uint8_t pin_num = _pin_num(pin); |
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if ((_port_num(pin) == PORT_D && pin_num > 3) |
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|| (_port_num(pin) == PORT_E && pin_num < 4) |
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|| ((mode != GPIO_IN) && (mode != GPIO_IN_PU))) { |
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return -1; |
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} |
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gpio_init(pin, mode); |
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/* clear global interrupt flag */ |
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cli(); |
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EIMSK |= (1 << pin_num); |
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/* configure the flank */ |
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switch (flank) { |
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case GPIO_RISING: |
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if (pin_num < 4) { |
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EICRA |= (3 << pin_num * 2); |
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} |
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else { |
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EICRB |= (3 << (pin_num * 2) % 4); |
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} |
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break; |
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case GPIO_FALLING: |
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if (pin_num < 4) { |
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EICRA |= (2 << pin_num * 2); |
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} |
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else { |
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EICRB |= (2 << (pin_num * 2) % 4); |
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} |
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break; |
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case GPIO_BOTH: |
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if (pin_num < 4) { |
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EICRA |= (1 << pin_num * 2); |
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} |
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else { |
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EICRB |= (1 << (pin_num * 2) % 4); |
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} |
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break; |
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default: |
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return -1; |
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}; |
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/* set callback */ |
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config[pin_num].cb = cb; |
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config[pin_num].arg = arg; |
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/* set global interrupt flag */ |
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sei(); |
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return 0; |
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} |
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void gpio_irq_enable(gpio_t pin) |
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{ |
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EIMSK |= (1 << _pin_num(pin)); |
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} |
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void gpio_irq_disable(gpio_t pin) |
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{ |
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EIMSK &= ~(1 << _pin_num(pin)); |
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} |
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int gpio_read(gpio_t pin) |
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{ |
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return (_SFR_MEM8(_pin_addr(pin)) & (1 << _pin_num(pin))); |
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} |
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void gpio_set(gpio_t pin) |
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{ |
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_SFR_MEM8(_port_addr(pin)) |= (1 << _pin_num(pin)); |
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} |
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void gpio_clear(gpio_t pin) |
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{ |
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_SFR_MEM8(_port_addr(pin)) &= ~(1 << _pin_num(pin)); |
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} |
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void gpio_toggle(gpio_t pin) |
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{ |
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if (gpio_read(pin)) { |
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gpio_clear(pin); |
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} |
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else { |
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gpio_set(pin); |
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} |
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} |
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void gpio_write(gpio_t pin, int value) |
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{ |
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if (value) { |
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gpio_set(pin); |
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} |
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else { |
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gpio_clear(pin); |
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} |
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} |
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static inline void irq_handler(uint8_t pin_num) |
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{ |
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__enter_isr(); |
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config[pin_num].cb(config[pin_num].arg); |
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__exit_isr(); |
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} |
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ISR(INT0_vect, ISR_BLOCK) |
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{ |
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irq_handler(0); /**< predefined interrupt pin */ |
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} |
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ISR(INT1_vect, ISR_BLOCK) |
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{ |
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irq_handler(1); /**< predefined interrupt pin */ |
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} |
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ISR(INT2_vect, ISR_BLOCK) |
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{ |
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irq_handler(2); /**< predefined interrupt pin */ |
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} |
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ISR(INT3_vect, ISR_BLOCK) |
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{ |
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irq_handler(3); /**< predefined interrupt pin */ |
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} |
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ISR(INT4_vect, ISR_BLOCK) |
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{ |
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irq_handler(4); /**< predefined interrupt pin */ |
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} |
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ISR(INT5_vect, ISR_BLOCK) |
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{ |
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irq_handler(5); /**< predefined interrupt pin */ |
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} |
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ISR(INT6_vect, ISR_BLOCK) |
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{ |
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irq_handler(6); /**< predefined interrupt pin */ |
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} |
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ISR(INT7_vect, ISR_BLOCK) |
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{ |
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irq_handler(7); /**< predefined interrupt pin */ |
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} |
@ -1,145 +0,0 @@
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/*
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* Copyright (C) 2015 Daniel Amkaer Sorensen |
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* 2016 Freie Universität Berlin |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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|
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/**
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* @ingroup cpu_atmega2560 |
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* @{ |
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* |
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* @file |
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* @brief Low-level SPI driver implementation |
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* |
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* @author Daniel Amkaer Sorensen <daniel.amkaer@gmail.com> |
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
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* |
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* @} |
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*/ |
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#include "cpu.h" |
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#include "mutex.h" |
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#include "periph/spi.h" |
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/* guard this file in case no SPI device is defined */ |
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#if SPI_NUMOF |
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/**
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* @brief Extract BR0, BR1 and SPI2X bits from speed value |
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* @{ |
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*/ |
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#define SPEED_MASK (0x3) |
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#define S2X_SHIFT (2) |
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/** @} */ |
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static mutex_t lock = MUTEX_INIT; |
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int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) |
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{ |
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/* make sure device is valid (there is only one...) */ |
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if (dev != 0) { |
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return -1; |
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} |
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/* the pin configuration for this CPU is fixed:
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* - PB3: MISO (configure as input - done automatically) |
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* - PB2: MOSI (configure as output) |
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* - PB1: SCK (configure as output) |
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* - PB0: SS (configure as output, but unused) |
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* |
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* The SS pin must be configured as output for the SPI device to work as |
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* master correctly, though we do not use it for now (as we handle the chip |
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* select externally for now) |
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*/ |
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DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0)); |
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/* make sure the SPI is not powered off */ |
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PRR0 &= ~(1 << PRSPI); |
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/* configure as master, with given mode and clock */ |
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SPSR = (speed >> S2X_SHIFT); |
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SPCR = ((1 << SPE) | (1 << MSTR) | conf | (speed & SPEED_MASK)); |
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/* clear interrupt flag */ |
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(void)SPSR; |
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(void)SPDR; |
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return 0; |
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} |
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int spi_acquire(spi_t dev) |
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{ |
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mutex_lock(&lock); |
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return 0; |
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} |
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|
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int spi_release(spi_t dev) |
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{ |
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mutex_unlock(&lock); |
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return 0; |
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} |
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|
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int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data)) |
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{ |
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(void) dev; |
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(void) conf; |
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(void) cb; |
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|
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/* not implemented */ |
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return -1; |
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} |
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|
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void spi_transmission_begin(spi_t dev, char reset_val) |
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{ |
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(void)dev; |
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(void)reset_val; |
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|
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/* not implemented */ |
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} |
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int spi_transfer_byte(spi_t dev, char out, char *in) |
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{ |
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return spi_transfer_bytes(dev, &out, in, 1); |
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} |
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|
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int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length) |
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{ |
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for (unsigned int i = 0; i < length; i++) { |
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char tmp = (out) ? out[i] : 0; |
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SPDR = tmp; |
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while (!(SPSR & (1 << SPIF))) {} |
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tmp = SPDR; |
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if (in) { |
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in[i] = tmp; |
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} |
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} |
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return (int)length; |
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} |
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|
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int spi_transfer_reg(spi_t dev, uint8_t reg, char out, char *in) |
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{ |
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spi_transfer_bytes(dev, (char *)®, NULL, 1); |
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return spi_transfer_bytes(dev, &out, in, 1); |
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} |
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|
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int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length) |
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{ |
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spi_transfer_bytes(dev, (char *)®, NULL, 1); |
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return spi_transfer_bytes(dev, out, in, length); |
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} |
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|
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void spi_poweron(spi_t dev) |
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{ |
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SPCR |= (1 << SPE); |
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} |
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|
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void spi_poweroff(spi_t dev) |
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{ |
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SPCR &= ~(1 << SPE); |
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} |
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|
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#endif /* SPI_NUMOF */ |
@ -1,258 +0,0 @@
|
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/*
|
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* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
||||
* General Public License v2.1. See the file LICENSE in the top level |
||||
* directory for more details. |
||||
*/ |
||||
|
||||
/**
|
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* @ingroup driver_periph |
||||
* @{ |
||||
* |
||||
* @file |
||||
* @brief Low-level timer driver implementation for the ATmega2560 CPU |
||||
* |
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
||||
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de> |
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* |
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* @} |
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*/ |
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|
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#include <avr/interrupt.h> |
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|
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#include "board.h" |
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#include "cpu.h" |
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#include "thread.h" |
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|
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#include "periph/timer.h" |
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#include "periph_conf.h" |
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|
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/**
|
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* @brief All timers have three channels |
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*/ |
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#define CHANNELS (3) |
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|
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/**
|
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* @brief We have 5 possible prescaler values |
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*/ |
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#define PRESCALE_NUMOF (5U) |
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|
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/**
|
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* @brief Possible prescaler values, encoded as 2 ^ val |
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*/ |
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static const uint8_t prescalers[] = { 0, 3, 6, 8, 10 }; |
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|
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/**
|
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* @brief Timer state context |
||||
*/ |
||||
typedef struct { |
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mega_timer_t *dev; /**< timer device */ |
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volatile uint8_t *mask; /**< address of interrupt mask register */ |
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volatile uint8_t *flag; /**< address of interrupt flag register */ |
||||
timer_cb_t cb; /**< interrupt callback */ |
||||
void *arg; /**< interrupt callback argument */ |
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uint8_t mode; /**< remember the configured mode */ |
||||
uint8_t isrs; /**< remember the interrupt state */ |
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} ctx_t; |
||||
|
||||
/**
|
||||
* @brief Allocate memory for saving the device states |
||||
* @{ |
||||
*/ |
||||
#if TIMER_NUMOF |
||||
static ctx_t ctx[] = { |
||||
#ifdef TIMER_0 |
||||
{ TIMER_0, TIMER_0_MASK, TIMER_0_FLAG, NULL, NULL, 0, 0 }, |
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#endif |
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#ifdef TIMER_1 |
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{ TIMER_1, TIMER_1_MASK, TIMER_1_FLAG, NULL, NULL, 0, 0 }, |
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#endif |
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#ifdef TIMER_2 |
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{ TIMER_2, TIMER_2_MASK, TIMER_2_FLAG, NULL, NULL, 0, 0 }, |
||||
#endif |
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#ifdef TIMER_3 |
||||
{ TIMER_3, TIMER_3_MASK, TIMER_3_FLAG, NULL, NULL, 0, 0 }, |
||||
#endif |
||||
}; |
||||
#else |
||||
/* fallback if no timer is configured */ |
||||
static ctx_t *ctx[] = {{ NULL }}; |
||||
#endif |
||||
/** @} */ |
||||
|
||||
/**
|
||||
* @brief Setup the given timer |
||||
*/ |
||||
int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg) |
||||
{ |
||||
uint8_t pre = 0; |
||||
|
||||
/* make sure given device is valid */ |
||||
if (tim >= TIMER_NUMOF) { |
||||
return -1; |
||||
} |
||||
|
||||
/* figure out if freq is applicable */ |
||||
for (; pre < PRESCALE_NUMOF; pre++) { |
||||
if ((CLOCK_CORECLOCK >> prescalers[pre]) == freq) { |
||||
break; |
||||
} |
||||
} |
||||
if (pre == PRESCALE_NUMOF) { |
||||
return -1; |
||||
} |
||||
|
||||
/* stop and reset timer */ |
||||
ctx[tim].dev->CRA = 0; |
||||
ctx[tim].dev->CRB = 0; |
||||
ctx[tim].dev->CRC = 0; |
||||
ctx[tim].dev->CNT = 0; |
||||
|
||||
/* save interrupt context and timer mode */ |
||||
ctx[tim].cb = cb; |
||||
ctx[tim].arg = arg; |
||||
ctx[tim].mode = (pre + 1); |
||||
|
||||
/* enable timer with calculated prescaler */ |
||||
ctx[tim].dev->CRB = (pre + 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int timer_set(tim_t tim, int channel, unsigned int timeout) |
||||
{ |
||||
return timer_set_absolute(tim, channel, timer_read(tim) + timeout); |
||||
} |
||||
|
||||
int timer_set_absolute(tim_t tim, int channel, unsigned int value) |
||||
{ |
||||
if (channel >= CHANNELS) { |
||||
return -1; |
||||
} |
||||
|
||||
ctx[tim].dev->OCR[channel] = (uint16_t)value; |
||||
*ctx[tim].flag &= ~(1 << (channel + OCF1A)); |
||||
*ctx[tim].mask |= (1 << (channel + OCIE1A)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int timer_clear(tim_t tim, int channel) |
||||
{ |
||||
if (channel >= CHANNELS) { |
||||
return -1; |
||||
} |
||||
|
||||
*ctx[tim].mask &= ~(1 << (channel + OCIE1A)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned int timer_read(tim_t tim) |
||||
{ |
||||
return (unsigned int)ctx[tim].dev->CNT; |
||||
} |
||||
|
||||
void timer_stop(tim_t tim) |
||||
{ |
||||
ctx[tim].dev->CRB = 0; |
||||
} |
||||
|
||||
void timer_start(tim_t tim) |
||||
{ |
||||
ctx[tim].dev->CRB = ctx[tim].mode; |
||||
} |
||||
|
||||
void timer_irq_enable(tim_t tim) |
||||
{ |
||||
*ctx[tim].mask = ctx[tim].isrs; |
||||
} |
||||
|
||||
void timer_irq_disable(tim_t tim) |
||||
{ |
||||
ctx[tim].isrs = *(ctx[tim].mask); |
||||
*ctx[tim].mask = 0; |
||||
} |
||||
|
||||
static inline void _isr(int num, int chan) |
||||
{ |
||||
__enter_isr(); |
||||
|
||||
*ctx[num].mask &= ~(1 << (chan + OCIE1A)); |
||||
ctx[num].cb(ctx[num].arg, chan); |
||||
|
||||
if (sched_context_switch_request) { |
||||
thread_yield(); |
||||
} |
||||
|
||||
__exit_isr(); |
||||
} |
||||
|
||||
#ifdef TIMER_0 |
||||
ISR(TIMER_0_ISRA, ISR_BLOCK) |
||||
{ |
||||
_isr(0, 0); |
||||
} |
||||
|
||||
ISR(TIMER_0_ISRB, ISR_BLOCK) |
||||
{ |
||||
_isr(0, 1); |
||||
} |
||||
|
||||
ISR(TIMER_0_ISRC, ISR_BLOCK) |
||||
{ |
||||
_isr(0, 2); |
||||
} |
||||
#endif /* TIMER_0 */ |
||||
|
||||
#ifdef TIMER_1 |
||||
ISR(TIMER_1_ISRA, ISR_BLOCK) |
||||
{ |
||||
_isr(1, 0); |
||||
} |
||||
|
||||
ISR(TIMER_1_ISRB, ISR_BLOCK) |
||||
{ |
||||
_isr(1, 1); |
||||
} |
||||
|
||||
ISR(TIMER_1_ISRC, ISR_BLOCK) |
||||
{ |
||||
_isr(1, 2); |
||||
} |
||||
#endif /* TIMER_1 */ |
||||
|
||||
#ifdef TIMER_2 |
||||
ISR(TIMER_2_ISRA, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 0); |
||||
} |
||||
|
||||
ISR(TIMER_2_ISRB, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 1); |
||||
} |
||||
|
||||
ISR(TIMER_2_ISRC, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 2); |
||||
} |
||||
#endif /* TIMER_2 */ |
||||
|
||||
#ifdef TIMER_3 |
||||
ISR(TIMER_3_ISRA, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 0); |
||||
} |
||||
|
||||
ISR(TIMER_3_ISRB, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 1); |
||||
} |
||||
|
||||
ISR(TIMER_3_ISRC, ISR_BLOCK) |
||||
{ |
||||
_isr(2, 2); |
||||
} |
||||
#endif /* TIMER_3 */ |
@ -1,133 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU Lesser |
||||
* General Public License v2.1. See the file LICENSE in the top level |
||||
* directory for more details. |
||||
*/ |
||||
|
||||
/**
|
||||
* @ingroup driver_periph |
||||
* @{ |
||||
* |
||||
* @file |
||||
* @brief Low-level UART driver implementation |
||||
* |
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de> |
||||
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de> |
||||
* |
||||
* @} |
||||
*/ |
||||
|
||||
#include "cpu.h" |
||||
#include "sched.h" |
||||
#include "thread.h" |
||||
|
||||
#include "periph/uart.h" |
||||
|
||||
/**
|
||||
* @brief Configured device map |
||||
* @{ |
||||
*/ |
||||
#if UART_NUMOF |
||||
static mega_uart_t *dev[] = { |
||||
#ifdef UART_0 |
||||
UART_0, |
||||
#endif |
||||
#ifdef UART_1 |
||||
UART_1, |
||||
#endif |
||||
#ifdef UART_2 |
||||
UART_2, |
||||
#endif |
||||
#ifdef UART_3 |
||||
UART_3 |
||||
#endif |
||||
}; |
||||
#else |
||||
/* fallback if no UART is defined */ |
||||
static const mega_uart_t *dev[] = { NULL }; |
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Allocate memory to store the callback functions. |
||||
*/ |
||||
static uart_isr_ctx_t isr_ctx[UART_NUMOF]; |
||||
|
||||
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) |
||||
{ |
||||
/* make sure the given device is valid */ |
||||
if (uart >= UART_NUMOF) { |
||||
return -1; |
||||
} |
||||
|
||||
/* register interrupt context */ |
||||
isr_ctx[uart].rx_cb = rx_cb; |
||||
isr_ctx[uart].arg = arg; |
||||
|
||||
/* disable and reset UART */ |
||||
dev[uart]->CSRB = 0; |
||||
dev[uart]->CSRA = 0; |
||||
|
||||
/* configure UART to 8N1 mode */ |
||||
dev[uart]->CSRC = (1 << UCSZ00) | (1 << UCSZ01); |
||||
/* set clock divider */ |
||||
dev[uart]->BRR = CLOCK_CORECLOCK / (16 * baudrate); |
||||
/* enable RX and TX and the RX interrupt */ |
||||
dev[uart]->CSRB = ((1 << RXCIE0) | (1 << RXEN0) | (1 << TXEN0)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void uart_write(uart_t uart, const uint8_t *data, size_t len) |
||||
{ |
||||
for (size_t i = 0; i < len; i++) { |
||||
while (!(dev[uart]->CSRA & (1 << UDRE0))); |
||||
dev[uart]->DR = data[i]; |
||||
} |
||||
} |
||||
|
||||
static inline void isr_handler(int num) |
||||
{ |
||||
isr_ctx[num].rx_cb(isr_ctx[num].arg, dev[num]->DR); |
||||
|
||||
if (sched_context_switch_request) { |
||||
thread_yield(); |
||||
} |
||||
} |
||||
|
||||
#ifdef UART_0_ISR |
||||
ISR(UART_0_ISR, ISR_BLOCK) |
||||
{ |
||||
__enter_isr(); |
||||
isr_handler(0); |
||||
__exit_isr(); |
||||
} |
||||
#endif /* UART_0_ISR */ |
||||
|
||||
#ifdef UART_1_ISR |
||||
ISR(UART_1_ISR, ISR_BLOCK) |
||||
{ |
||||
__enter_isr(); |
||||
isr_handler(1); |
||||
__exit_isr(); |
||||
} |
||||
#endif /* UART_1_ISR */ |
||||
|
||||
#ifdef UART_2_ISR |
||||
ISR(UART_2_ISR, ISR_BLOCK) |
||||
{ |
||||
__enter_isr(); |
||||
isr_handler(2); |
||||
__exit_isr(); |
||||
} |
||||
#endif /* UART_2_ISR */ |
||||
|
||||
#ifdef UART_3_ISR |
||||
ISR(UART_3_ISR, ISR_BLOCK) |
||||
{ |
||||
__enter_isr(); |
||||
isr_handler(3); |
||||
__exit_isr(); |
||||
} |
||||
#endif /* UART_3_ISR */ |
Loading…
Reference in new issue