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boards/nucleo32-f303: initial support

pr/spi.typo
Alexandre Abadie 6 years ago
parent
261965d936
commit
c35411c588
9 changed files with 316 additions and 0 deletions
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  1. 3
      boards/nucleo32-f303/Makefile
  2. 3
      boards/nucleo32-f303/Makefile.dep
  3. 12
      boards/nucleo32-f303/Makefile.features
  4. 13
      boards/nucleo32-f303/Makefile.include
  5. 31
      boards/nucleo32-f303/board.c
  6. 1
      boards/nucleo32-f303/dist/openocd.cfg
  7. 51
      boards/nucleo32-f303/include/board.h
  8. 46
      boards/nucleo32-f303/include/gpio_params.h
  9. 156
      boards/nucleo32-f303/include/periph_conf.h

3
boards/nucleo32-f303/Makefile
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MODULE = board
include $(RIOTBASE)/Makefile.base

3
boards/nucleo32-f303/Makefile.dep
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ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif

12
boards/nucleo32-f303/Makefile.features
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Various common features of Nucleo boards
FEATURES_PROVIDED += cpp
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_2

13
boards/nucleo32-f303/Makefile.include
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## the cpu to build for
export CPU = stm32f3
export CPU_MODEL = stm32f303k8
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTBOARD)/Makefile.include.serial
# this board uses openocd
include $(RIOTBOARD)/Makefile.include.openocd

31
boards/nucleo32-f303/board.c
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-f303
* @{
*
* @file
* @brief Board specific implementations for the nucleo32-f303 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the boards LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
}

1
boards/nucleo32-f303/dist/openocd.cfg vendored
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source [find board/st_nucleo_f3.cfg]

51
boards/nucleo32-f303/include/board.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo32-f303 Nucleo32-F303
* @ingroup boards
* @brief Board specific files for the nucleo32-f303 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo32-f303 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef BOARD_H_
#define BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Macros for controlling the on-board LED.
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_B, 3)
#define LED0_MASK (1 << 3)
#define LED0_ON (GPIOB->BSRRL = LED0_MASK)
#define LED0_OFF (GPIOB->BSRRH = LED0_MASK)
#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H_ */
/** @} */

46
boards/nucleo32-f303/include/gpio_params.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-f303
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD3",
.pin = LED0_PIN,
.mode = GPIO_OUT
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

156
boards/nucleo32-f303/include/periph_conf.h
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-f303
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo32-f303 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSI (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
/* the actual PLL values are automatically generated */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @brief Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @brief UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 15),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn
}
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @brief PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM3,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
{ .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 3 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF2,
.bus = APB1
},
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF6,
.bus = APB2
}
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (0U)
/** @} */
/**
* @brief ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @brief DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H_ */
/** @} */
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