From c4d28cb5e26e80ae7778503c92ef96ded2d5b275 Mon Sep 17 00:00:00 2001 From: Neil Jones Date: Mon, 7 Nov 2016 13:35:17 +0000 Subject: [PATCH] boards: pic32-wifire: Add support for the Digilent WiFire board. This board features a pic32mz2048efg100 PIC32 device with a MIPS core. --- boards/pic32-wifire/Makefile | 2 + boards/pic32-wifire/Makefile.features | 9 + boards/pic32-wifire/Makefile.include | 4 + boards/pic32-wifire/include/board.h | 58 +++ boards/pic32-wifire/include/periph_conf.h | 62 +++ boards/pic32-wifire/pic32_config_settings.c | 419 ++++++++++++++++++ boards/pic32-wifire/wifire.c | 45 ++ cpu/Makefile.include.mips_common | 43 ++ cpu/mips32r2_common/Makefile.include | 42 +- cpu/mips_pic32_common/reset_mod.S | 4 +- cpu/mips_pic32mz/Makefile.include | 76 +--- .../include/{ => vendor}/p32mz2048efg100.h | 0 12 files changed, 666 insertions(+), 98 deletions(-) create mode 100644 boards/pic32-wifire/Makefile create mode 100644 boards/pic32-wifire/Makefile.features create mode 100644 boards/pic32-wifire/Makefile.include create mode 100644 boards/pic32-wifire/include/board.h create mode 100644 boards/pic32-wifire/include/periph_conf.h create mode 100644 boards/pic32-wifire/pic32_config_settings.c create mode 100644 boards/pic32-wifire/wifire.c create mode 100644 cpu/Makefile.include.mips_common rename cpu/mips_pic32mz/include/{ => vendor}/p32mz2048efg100.h (100%) diff --git a/boards/pic32-wifire/Makefile b/boards/pic32-wifire/Makefile new file mode 100644 index 000000000..72ba6f362 --- /dev/null +++ b/boards/pic32-wifire/Makefile @@ -0,0 +1,2 @@ +MODULE = board +include $(RIOTBASE)/Makefile.base diff --git a/boards/pic32-wifire/Makefile.features b/boards/pic32-wifire/Makefile.features new file mode 100644 index 000000000..bf4ba1fe2 --- /dev/null +++ b/boards/pic32-wifire/Makefile.features @@ -0,0 +1,9 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Various other features (if any) +FEATURES_PROVIDED += cpp + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = mips32r2 diff --git a/boards/pic32-wifire/Makefile.include b/boards/pic32-wifire/Makefile.include new file mode 100644 index 000000000..acac07dac --- /dev/null +++ b/boards/pic32-wifire/Makefile.include @@ -0,0 +1,4 @@ +export CPU = mips_pic32mz +export CPU_MODEL=p32mz2048efg100 +export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ +export APPDEPS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)/$(CPU_MODEL).S diff --git a/boards/pic32-wifire/include/board.h b/boards/pic32-wifire/include/board.h new file mode 100644 index 000000000..02c4db1dc --- /dev/null +++ b/boards/pic32-wifire/include/board.h @@ -0,0 +1,58 @@ +/* + * Copyright(C) 2017, Imagination Technologies Limited and/or its + * affiliated group companies. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +/** + * @defgroup boards_pic32-wifire Digilent PIC32 WiFire + * @ingroup boards + * @brief board configuration for the Digilent PIC32 WiFire + * @details + * See: + * http://store.digilentinc.com/chipkit-wi-fire-wifi-enabled-mz-microcontroller-board/ + * for more information on the board. + * + * @{ + * + * @file + * @brief board configuration for the Digilent PIC32 WiFire + * + * @author Neil Jones + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vendor/p32mz2048efg100.h" + +/** + * @brief Set how many increments of the count register per uS + * needed by the timer code. + */ +#define TICKS_PER_US (100) + +/** + * @brief We are using an External Interrupt Controller (all pic32 devices use this mode) + */ +#define EIC_IRQ (1) + +/** + * @brief Board level initialisation + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARD_H_ */ +/** @} */ diff --git a/boards/pic32-wifire/include/periph_conf.h b/boards/pic32-wifire/include/periph_conf.h new file mode 100644 index 000000000..d53ea72b4 --- /dev/null +++ b/boards/pic32-wifire/include/periph_conf.h @@ -0,0 +1,62 @@ +/* + * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its + * affiliated group companies. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +/** + * @defgroup boards_pic32-wifire Digilent PIC32 WiFire + * @ingroup boards + * @brief peripheral configuration for the Digilent PIC32 WiFire + * @{ + * + * @file + * @brief peripheral configuration for the Digilent PIC32 WiFire + * + * @author Neil Jones + */ +#ifndef _PERIPH_CONF_H_ +#define _PERIPH_CONF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The peripheral clock is required for the UART Baud rate calculation + * It is configured by the 'config' registers (see pic32_config_settings.c) + */ +#define PERIPHERAL_CLOCK (100000000) /* Hz */ + +/** + * @brief Timer definitions + * @{ + */ +#define TIMER_NUMOF (1) +#define TIMER_0_CHANNELS (3) +/** @} */ + +/** + * @brief UART Definitions + * There are 6 UARTS available on this CPU. + * We route debug via UART4 on this board, + * this is the UART connected to the FTDI USB <-> UART device. + * + * Note Microchip number the UARTS 1->4. + * @{ + */ +#define UART_NUMOF (6) +#define DEBUG_VIA_UART (4) +#define DEBUG_UART_BAUD (9600) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif +/** @} */ diff --git a/boards/pic32-wifire/pic32_config_settings.c b/boards/pic32-wifire/pic32_config_settings.c new file mode 100644 index 000000000..f45d18a44 --- /dev/null +++ b/boards/pic32-wifire/pic32_config_settings.c @@ -0,0 +1,419 @@ +/* + * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its + * affiliated group companies. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +#include +#include "vendor/p32mz2048efg100.h" + +/* + * Note banked access only applies to MZ part MX only has 1 set of registers + * similar to the MZ's lower alias.Thus when working with MX parts comment + * out the *_B* entries, note the address in the comments are different for MX + * too so a different linker script is required between MX and MZ to place + * these registers at the correct addresses. MM parts have completely different + * config registers, so this file is not applicable. + * + * Note when programming via Microchip IPE (tested using a Pickit-3) entries + * need to exist in the programming file for both the lower alias and the + * config1 configuration spaces (starting at 0x1FC0FFC0 and 0x1FC4FFC0) + * hence the duplicate entries in different sections allowing the linker to + * place them at different addresses. + */ + + +/* + * DEVCFG3_LA @ 0x1FC0FFC0 (lower alias) + * ADEVFGC3_LA @ 0x1FC0FF40 (alternate devcfg3 in lower alias) + * DEVCFG3_B1 @ 0x1FC4FFC0 (config space 1) + * ADEVCFG3_B1 @ 0x1FC4FF40 (alternate devcfg3 in config space 1) + * DEVCFG3_B2 @ 0x1FC6FFC0 (config space 1) + * ADEVCFG3_B2 @ 0x1FC6FF40 (alternate devcfg3 in config space 2) + * + * + * USERID + * FMIIEN OFF Ethernet RMII/MII Enable RMII Enabled + * FETHIO ON Ethernet I/O Pin Select Default Ethernet I/O + * PGL1WAY OFF Permission Group Lock One Way Configuration Allow multiple reconfigurations + * PMDL1WAY OFF Peripheral Module Disable Configuration Allow multiple reconfigurations + * IOL1WAY OFF Peripheral Pin Select Configuration Allow multiple reconfigurations + * FUSBIDIO OFF USB USBID Selection Controlled by Port Function + */ +volatile uint32_t DEVCFG3_LA __attribute__((used, section(".devcfg3_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION) + & (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION) + & (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION) + & (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION) + & (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION) + & (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION) + & (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION); + +volatile uint32_t ADEVCFG3_LA __attribute__((used, section(".adevcfg3_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION) + & (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION) + & (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION) + & (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION) + & (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION) + & (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION) + & (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION); + +volatile uint32_t DEVCFG3_B1 __attribute__((used, section(".devcfg3_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION) + & (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION) + & (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION) + & (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION) + & (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION) + & (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION) + & (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION); + +volatile uint32_t ADEVCFG3_B1 __attribute__((used, section(".adevcfg3_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION) + & (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION) + & (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION) + & (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION) + & (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION) + & (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION) + & (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION); +/* + * Not needed by default: + * volatile uint32_t DEVCFG3_B2 __attribute__((used,section(".devcfg3_b2"))) + * = DEVCFG3_LA; + * volatile uint32_t ADEVCFG3_B2 __attribute__((used,section(".adevcfg3_la"))) + * = DEVCFG3_LA; + * + */ + +/* + * DEVCFG2_LA @ 0x1FC0FFC4 (lower alias) + * ADEVFGC2_LA @ 0x1FC0FF44 (alternate devcfg2 in lower alias) + * DEVCFG2_B1 @ 0x1FC4FFC4 (config space 1) + * ADEVCFG2_B1 @ 0x1FC4FF44 (alternate devcfg2 in config space 1) + * DEVCFG2_B2 @ 0x1FC6FFC4 (config space 1) + * ADEVCFG2_B2 @ 0x1FC6FF44 (alternate devcfg2 in config space 2) + * + * 24MHz OSC / 3 * 50 / 2 = 200MHz + * + * FPLLIDIV DIV_3 System PLL Input Divider 3x Divider + * FPLLRNG RANGE_5_10_MHZ System PLL Input Range 5-10 MHz Input + * FPLLICLK PLL_POSC System PLL Input Clock Selection POSC is input to the System PLL + * FPLLMULT MUL_50 System PLL Multiplier PLL Multiply by 50 + * FPLLODIV DIV_2 System PLL Output Clock Divider 2x Divider + * UPLLFSEL FREQ_24MHZ USB PLL Input Frequency Selection USB PLL input is 24 MHz + */ + +volatile uint32_t DEVCFG2_LA __attribute__ ((used, section(".devcfg2_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION) + & (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION) + & (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION) + & (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION) + & (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION) + & (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION); + +volatile uint32_t ADEVCFG2_LA __attribute__ ((used, section(".adevcfg2_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION) + & (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION) + & (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION) + & (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION) + & (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION) + & (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION); + +volatile uint32_t DEVCFG2_B1 __attribute__ ((used, section(".devcfg2_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION) + & (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION) + & (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION) + & (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION) + & (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION) + & (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION); + +volatile uint32_t ADEVCFG2_B1 __attribute__ ((used, section(".adevcfg2_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION) + & (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION) + & (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION) + & (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION) + & (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION) + & (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION); +/* Not needed by default: */ +/* uint32_t DEVCFG2_B2 __attribute__ ((section(".devcfg2_b2"))) = DEVCFG2_LA; */ +/* uint32_t ADEVCFG2_B2 __attribute__ ((section(".adevcfg2_b2"))) = DEVCFG2_LA; */ + + +/* + * DEVCFG1_LA @ 0x1FC0FFC8 (lower alias) + * ADEVFGC1_LA @ 0x1FC0FF48 (alternate devcfg1 in lower alias) + * DEVCFG1_B1 @ 0x1FC4FFC8 (config space 1) + * ADEVCFG1_B1 @ 0x1FC4FF48 (alternate devcfg1 in config space 1) + * DEVCFG1_B2 @ 0x1FC6FFC8 (config space 1) + * ADEVCFG1_B2 @ 0x1FC6FF48 (alternate devcfg1 in config space 2) + * + * FNOSC SPLL Oscillator Selection Bits System PLL + * DMTINTV WIN_127_128 DMT Count Window Interval Window/Interval value is 127/128 counter value + * FSOSCEN OFF Secondary Oscillator Enable Disable SOSC + * IESO ON Internal/External Switch Over Enabled + * POSCMOD EC Primary Oscillator Configuration External clock mode + * OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled (1) + * FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disabled, FSCM Disabled + * WDTPS PS1048576 Watchdog Timer Postscaler 1:1048576 + * WDTSPGM STOP Watchdog Timer Stop During Flash Programming WDT stops during Flash programming + * WINDIS NORMAL Watchdog Timer Window Mode Watchdog Timer is in non-Window mode + * FWDTEN OFF Watchdog Timer Enable WDT Disabled + * FWDTWINSZ WINSZ_25 Watchdog Timer Window Size Window size is 25% + * DMTCNT DMT8 Deadman Timer Count Selection 2^8 (256) + * FDMTEN OFF Deadman Timer Enable Deadman Timer is disabled + */ + +volatile uint32_t DEVCFG1_LA __attribute__ ((used, section(".devcfg1_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION) + & (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION) + & (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION) + & (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) + & (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION) + & (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) + & (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION) + & (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION) + & (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION) + & (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION) + & (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) + & (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION) + & (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION) + & (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION); + +volatile uint32_t ADEVCFG1_LA __attribute__ ((used, section(".adevcfg1_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION) + & (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION) + & (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION) + & (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) + & (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION) + & (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) + & (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION) + & (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION) + & (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION) + & (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION) + & (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) + & (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION) + & (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION) + & (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION); + +volatile uint32_t DEVCFG1_B1 __attribute__ ((used, section(".devcfg1_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION) + & (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION) + & (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION) + & (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) + & (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION) + & (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) + & (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION) + & (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION) + & (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION) + & (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION) + & (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) + & (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION) + & (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION) + & (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION); + +volatile uint32_t ADEVCFG1_B1 __attribute__ ((used, section(".adevcfg1_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION) + & (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION) + & (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION) + & (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION) + & (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION) + & (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION) + & (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION) + & (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION) + & (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION) + & (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION) + & (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION) + & (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION) + & (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION) + & (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION); + +/* Not needed by default: */ +/* uint32_t DEVCFG1_B2 __attribute__ ((section(".devcfg1_b2"))) = DEVCFG1_LA; */ +/* uint32_t ADEVCFG1_B2 __attribute__ ((section(".adevcfg1_b2"))) = DEVCFG1_LA */ + +/* + * DEVCFG0_LA @ 0x1FC0FFCC (lower alias) + * ADEVFGC0_LA @ 0x1FC0FF4C (alternate devcfg0 in lower alias) + * DEVCFG0_B1 @ 0x1FC4FFCC (config space 1) + * ADEVCFG0_B1 @ 0x1FC4FF4C (alternate devcfg0 in config space 1) + * DEVCFG0_B2 @ 0x1FC6FFCC (config space 1) + * ADEVCFG0_B2 @ 0x1FC6FF4C (alternate devcfg0 in config space 2) + * + * DEBUG OFF Background Debugger Enable Debugger is disabled + * JTAGEN ON JTAG Enable JTAG Port Enabled + * ICESEL ICS_PGx2 ICE/ICD Comm Channel Select Communicate on PGEC2/PGED2 + * TRCEN ON Trace Enable Trace features in the CPU are disabled + * BOOTISA MIPS32 Boot ISA Selection Boot code and Exception code is MIPS32 + * FECCCON OFF_UNLOCKED Dynamic Flash ECC Configuration ECC and Dynamic ECC are disabled (ECCCON bits are writable) + * FSLEEP OFF Flash Sleep Mode Flash is powered down when the device is in Sleep mode + * DBGPER PG_ALL Debug Mode CPU Access Permission Allow CPU access to all permission regions + * SMCLR MCLR_NORM Soft Master Clear Enable bit MCLR pin generates a normal system Reset + * SOSCGAIN GAIN_2X Secondary Oscillator Gain Control bits 2x gain setting + * SOSCBOOST ON Secondary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator + * POSCGAIN GAIN_2X Primary Oscillator Gain Control bits 2x gain setting + * POSCBOOST ON Primary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator + * EJTAGBEN NORMAL EJTAG Boot Normal EJTAG functionality + */ + +volatile uint32_t DEVCFG0_LA __attribute__ ((used, section(".devcfg0_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION) + & (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION) + & (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION) + & (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION) + & (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION) + & (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION) + & (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION) + & (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION) + & (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION) + & (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION) + & (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION) + & (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION) + & (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION) + & (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION); + +volatile uint32_t ADEVCFG0_LA __attribute__ ((used, section(".adevcfg0_la"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION) + & (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION) + & (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION) + & (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION) + & (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION) + & (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION) + & (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION) + & (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION) + & (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION) + & (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION) + & (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION) + & (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION) + & (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION) + & (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION); + +volatile uint32_t DEVCFG0_B1 __attribute__ ((used, section(".devcfg0_b1"))) = + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION) + & (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION) + & (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION) + & (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION) + & (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION) + & (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION) + & (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION) + & (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION) + & (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION) + & (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION) + & (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION) + & (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION) + & (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION) + & (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION); + +volatile uint32_t ADEVCFG0_B1 __attribute__ ((used, section(".adevcfg0_b1")))= + 0xffffffff /* unused bits must be 1 */ + & (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION) + & (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION) + & (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION) + & (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION) + & (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION) + & (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION) + & (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION) + & (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION) + & (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION) + & (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION) + & (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION) + & (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION) + & (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION) + & (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION); + +/* + * uint32_t DEVCFG0_B2 __attribute__ ((section(".devcfg0_b2"))) + * = 0xFFFFF7D7; + * uint32_t ADEVCFG0_B2 __attribute__ ((section(".adevcfg0_b2"))) + * = 0xFFFFF7D7; + * + */ + + +/* + * DEVCP0_LA @ 0x1FC0FFDC (lower alias) + * ADEVCP0_LA @ 0x1FC0FF5C (alternate devcp0 in lower alias) + * DEVCP0_B1 @ 0x1FC4FFDC (config space 1) + * ADEVCP0_B1 @ 0x1FC4FF5C (alternate devcp0 in config space 1) + * DEVCP0_B2 @ 0x1FC6FFDC (config space 1) + * ADEVCP0_B2 @ 0x1FC6FF5C (alternate devcp0 in config space 2 + * + * CP OFF Code Protect Protection Disabled, unused bits must be 1. + */ + +volatile uint32_t DEVCP0_LA __attribute__ ((used, section(".devcp0_la"))) = + 0xFFFFFFFF | _DEVCP0_CP_MASK; +volatile uint32_t ADEVCP0_LA __attribute__ ((used, section(".adevcp0_la"))) = + 0xFFFFFFFF | _DEVCP0_CP_MASK; +volatile uint32_t DEVCP0_B1 __attribute__ ((used, section(".devcp0_b1"))) = + 0xFFFFFFFF | _DEVCP0_CP_MASK; +volatile uint32_t ADEVCP0_B1 __attribute__ ((used, section(".adevcp0_b1"))) = + 0xFFFFFFFF | _DEVCP0_CP_MASK; +/* not needed by default */ +/* uint32_t DEVCP0_B2 __attribute__ ((section(".devcp0_b1"))) = 0xFFFFFFFF; */ +/* uint32_t ADEVCP0_B2 __attribute__ ((section(".adevcp0_b1"))) = 0xFFFFFFFF; */ + +/* + * SEQ_B1[0..3] @ 1FC0FFF0 + * SEQ_B1[0..3] @ 1FC4FFF0 + * + * TSEQ Boot Flash True Sequence Number + * CSEQ Boot Flash Complement Sequence Number + */ + +volatile uint32_t SEQ_LA[4] __attribute__ ((used, section(".seq_la"))) = + { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; +volatile uint32_t SEQ_B1[4] __attribute__ ((used, section(".seq_b1"))) = + { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; +/* + * Not needed by default: + * uint32_t SEQ_B2[4] __attribute__ ((section(".seq_b2"))) = + * {0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF}; + */ + + +/* + * STUPIDLY Microchip has hard coded the MSB bit of devsign to 0, So even if + * you erase the whole device, everything returns 0xFFFFFFF except this 1 + * register (and its alternate) which return 0x7FFFFFF!! + * + * We set it in the output image so verification doesn't fail + * + * DEVSIGN0 @ 0xBFC0FFEC + * ADEVSIGN0 @ 0xBFC0FF6C + * + */ + +volatile uint32_t DEVSIGN_LA __attribute__ ((used, section(".devsign_la"))) = 0x7FFFFFFF; +volatile uint32_t ADEVSIGN_LA __attribute__ ((used, section(".adevsign_la"))) = 0x7FFFFFFF; +volatile uint32_t DEVSIGN_B1 __attribute__ ((used, section(".devsign_b1"))) = 0x7FFFFFFF; +volatile uint32_t ADEVSIGN_B1 __attribute__ ((used, section(".adevsign_b1"))) = 0x7FFFFFFF; +volatile uint32_t DEVSIGN_B2 __attribute__ ((used, section(".devsign_b2"))) = 0x7FFFFFFF; +volatile uint32_t ADEVSIGN_B2 __attribute__ ((used, section(".adevsign_b2"))) = 0x7FFFFFFF; + + +/* + * Without a reference to this function from elsewhere LD throws the whole + * compile unit away even though the data is 'volatile' and 'used' !!! + */ +void dummy(void) +{ + (void)1; +} diff --git a/boards/pic32-wifire/wifire.c b/boards/pic32-wifire/wifire.c new file mode 100644 index 000000000..857bc90c6 --- /dev/null +++ b/boards/pic32-wifire/wifire.c @@ -0,0 +1,45 @@ +/* + * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its + * affiliated group companies. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + * + */ + +#include +#include +#include "periph/uart.h" +#include "bitarithm.h" +#include "board.h" +#include "periph_conf.h" + +extern void dummy(void); + +void board_init(void) +{ + /* + * Setup pin mux for UART4 this is the one connected + * to the ftdi chip (usb<->uart) + */ + U4RXREG = 0xb; /* connect pin RPF2 to UART 4 RX */ + RPF8R = 0x2; /* connect pin RPF8 to UART 4 TX */ + PORTFCLR = BIT8 | BIT2; /* clear down port F pins 2 and 8 */ + TRISFCLR = BIT2; /* set portf pin 2 as input */ + TRISFSET = BIT8; /* set portf pin 8 as output */ + ODCFCLR = BIT8 | BIT2; /* set portf pint 2 and 8 as not open-drain */ + + /* intialise UART used for debug (printf) */ +#ifdef DEBUG_VIA_UART + uart_init(DEBUG_VIA_UART, DEBUG_UART_BAUD, NULL, 0); +#endif + + /* Stop the linker from throwing away the PIC32 config register settings */ + dummy(); +} + +void pm_reboot(void) +{ + /* TODO, note this is needed to get 'default' example to build */ +} diff --git a/cpu/Makefile.include.mips_common b/cpu/Makefile.include.mips_common new file mode 100644 index 000000000..f4bb05caf --- /dev/null +++ b/cpu/Makefile.include.mips_common @@ -0,0 +1,43 @@ +ifndef MIPS_ELF_ROOT +ifneq ($(BUILD_IN_DOCKER),1) #Don't error when BUILD_IN_DOCKER=1 as it _is_ set in DOCKER + $(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH") +endif +endif + +# Target triple for the build. +export TARGET_ARCH ?= mips-mti-elf + +export ABI=32 + +ifneq ($(BUILD_IN_DOCKER),1) #Don't error when BUILD_IN_DOCKER=1 as MIPS_ELF_ROOT _is_ set in DOCKER +include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk +endif + +# define build specific options +export CFLAGS_CPU = -EL -std=gnu99 +export CFLAGS_LINK = -ffunction-sections -fno-builtin -fshort-enums #-fdata-sections +export CFLAGS_DBG = -O0 -g2 +export CFLAGS_OPT = -Os -g2 + +export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT) +#$(CFLAGS_DBG) + +ifeq ($(USE_HARD_FLOAT),1) + export CFLAGS += -mhard-float +else + export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float + export LINKFLAGS += -msoft-float +endif + +ifeq ($(USE_DSP),1) + export CFLAGS += -mdsp +endif + +export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG) + +export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI) +export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) +export LINKFLAGS += -Wl,--gc-sections + +# This CPU implementation is using the new core/CPU interface: +export CFLAGS += -DCOREIF_NG=1 diff --git a/cpu/mips32r2_common/Makefile.include b/cpu/mips32r2_common/Makefile.include index d0c9b7a76..644a65df4 100644 --- a/cpu/mips32r2_common/Makefile.include +++ b/cpu/mips32r2_common/Makefile.include @@ -1,48 +1,8 @@ -ifndef MIPS_ELF_ROOT - $(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH") -endif - -# Target triple for the build. -export TARGET_ARCH ?= mips-mti-elf - -export ABI=32 export MEMORY_BASE=0x80000000 export MEMORY_SIZE=1M export APP_START=0x80000000 -include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk - -# define build specific options -export CFLAGS_CPU = -EL -march=mips32r2 -std=gnu99 -export CFLAGS_LINK = -ffunction-sections -fdata-sections -fno-builtin -fshort-enums -export CFLAGS_DBG = -O0 -g2 -export CFLAGS_OPT = -Os -g2 - -export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT) -#$(CFLAGS_DBG) - -ifeq ($(USE_HARD_FLOAT),1) - export CFLAGS += -mhard-float -else - export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float - export LINKFLAGS += -msoft-float -endif +include $(RIOTCPU)/Makefile.include.mips_common -ifeq ($(USE_DSP),1) - export CFLAGS += -mdsp -endif - -export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG) - -export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI) export LINKFLAGS += -Tuhi32.ld -export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) -export LINKFLAGS += -Wl,--gc-sections - -# This CPU implementation is using the new core/CPU interface: -export CFLAGS += -DCOREIF_NG=1 - -# use newlib as libc, Actually use toolchains newlib. -#export USEMODULE += newlib - export USEMODULE += periph diff --git a/cpu/mips_pic32_common/reset_mod.S b/cpu/mips_pic32_common/reset_mod.S index 85940d850..078c2c52d 100644 --- a/cpu/mips_pic32_common/reset_mod.S +++ b/cpu/mips_pic32_common/reset_mod.S @@ -81,7 +81,7 @@ LEAF(__cpu_init) mfc0 s1, C0_STATUS # Read CP0 Status ext s1, s1, SR_NMI_SHIFT, 1 # extract NMI - beqz s1, init_resources # Branch if this is NOT an NMI exception. + beqz s1, init_resources # /* Branch if this is NOT an NMI exception. */ move k0, t9 # Preserve t9 move k1, a0 # Preserve a0 li $25, 15 # UHI exception operation @@ -179,7 +179,7 @@ $Lall_done: # If _start returns it will return to this point. # Just spin here reporting the exit. li $25, 1 # UHI exit operation - move $4, v0 # Collect exit code for UHI exit + move $4, v0 # /* Collect exit code for UHI exit */ sdbbp 1 # Invoke UHI operation b $Lall_done END(__cpu_init) diff --git a/cpu/mips_pic32mz/Makefile.include b/cpu/mips_pic32mz/Makefile.include index 0fbfc688b..7a36d5131 100644 --- a/cpu/mips_pic32mz/Makefile.include +++ b/cpu/mips_pic32mz/Makefile.include @@ -1,69 +1,35 @@ -ifndef MIPS_ELF_ROOT - $(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH") -endif - -# Target triple for the build. -export TARGET_ARCH ?= mips-mti-elf - -export ABI=32 export MEMORY_BASE=0x80000000 export MEMORY_SIZE=512K export APP_START=0x80000000 export ROMABLE = 1 -include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk +include $(RIOTCPU)/Makefile.include.mips_common # define build specific options -export CFLAGS_CPU = -EL -march=m5101 -mmicromips -std=gnu99 -export CFLAGS_LINK = -ffunction-sections -fno-builtin -fshort-enums -export CFLAGS_DBG = -O0 -g2 -export CFLAGS_OPT = -Os -g2 - -export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT) -DSKIP_COPY_TO_RAM -#$(CFLAGS_DBG) - -ifeq ($(USE_HARD_FLOAT),1) - export CFLAGS += -mhard-float -else - export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float - export LINKFLAGS += -msoft-float -endif - -ifeq ($(USE_DSP),1) - export CFLAGS += -mdsp -endif - -export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG) - -export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI) -Wl,--defsym,__use_excpt_boot=0 -export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mz2048_uhi.ld -export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) #$(CFLAGS_OPT) -export LINKFLAGS += -Wl,--gc-sections - -# This CPU implementation is using the new core/CPU interface: -export CFLAGS += -DCOREIF_NG=1 - -# The M51xx supports micromips ISA for reduced code size. +export CFLAGS += -march=m5101 -mmicromips -DSKIP_COPY_TO_RAM export CFLAGS += -DMIPS_MICROMIPS export USEMODULE += periph +export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS) +export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mz2048_uhi.ld + # the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!! export OBJCOPY = objcopy #use system objcopy as toolchain one is broken. export OFLAGS += -O ihex \ - --change-section-lma .lowerbootflashalias-0xA0000000 \ - --change-section-lma .bootflash1-0xA0000000 \ - --change-section-lma .bootflash2-0xA0000000 \ - --change-section-lma .exception_vector-0x80000000 \ - --change-section-lma .text-0x80000000 \ - --change-section-lma .init-0x80000000 \ - --change-section-lma .fini-0x80000000 \ - --change-section-lma .eh_frame-0x80000000 \ - --change-section-lma .gcc_except_table-0x80000000 \ - --change-section-lma .jcr-0x80000000 \ - --change-section-lma .ctors-0x80000000 \ - --change-section-lma .dtors-0x80000000 \ - --change-section-lma .rodata-0x80000000 \ - --change-section-lma .data-0x80000000 \ - --change-section-lma .bss-0x80000000 \ - --change-section-lma .startdata-0x80000000 \ + --change-section-lma .lowerbootflashalias-0xA0000000 \ + --change-section-lma .bootflash1-0xA0000000 \ + --change-section-lma .bootflash2-0xA0000000 \ + --change-section-lma .exception_vector-0x80000000 \ + --change-section-lma .text-0x80000000 \ + --change-section-lma .init-0x80000000 \ + --change-section-lma .fini-0x80000000 \ + --change-section-lma .eh_frame-0x80000000 \ + --change-section-lma .gcc_except_table-0x80000000 \ + --change-section-lma .jcr-0x80000000 \ + --change-section-lma .ctors-0x80000000 \ + --change-section-lma .dtors-0x80000000 \ + --change-section-lma .rodata-0x80000000 \ + --change-section-lma .data-0x80000000 \ + --change-section-lma .bss-0x80000000 \ + --change-section-lma .startdata-0x80000000 diff --git a/cpu/mips_pic32mz/include/p32mz2048efg100.h b/cpu/mips_pic32mz/include/vendor/p32mz2048efg100.h similarity index 100% rename from cpu/mips_pic32mz/include/p32mz2048efg100.h rename to cpu/mips_pic32mz/include/vendor/p32mz2048efg100.h