Remove Not yet supported ADC peripheral. ToDo task
parent
dad274ccea
commit
c99de05d23
@ -1,5 +1,4 @@
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FEATURES_PROVIDED += cpp
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#FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_MCU_GROUP = cortex_m4
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@ -1,220 +0,0 @@
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/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lm4f120
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* @{
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*
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* @file adc.c
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* @brief Low-level ADC driver implementation
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*/
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#include "cpu.h"
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#include "periph/adc.h"
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#include "periph_conf.h"
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/* guard in case that no ADC device is defined */
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#if ADC_NUMOF
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typedef struct {
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int max_value;
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} adc_config_t;
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adc_config_t adc_config[ADC_NUMOF];
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int adc_init(adc_t dev, adc_precision_t precision)
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{
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adc_poweron(dev);
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// ADC0 is used with AIN0 on port E3.
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// ADC1 is used with AIN1 on port E2.
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// GPIO port E needs to be enabled so that these pinds can be used
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
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// Set the ADC to 125KSPS.
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// This requires less power and produce longer samping time,
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// creating accurate conversions
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ROM_SysCtlADCSpeedSet(SYSCTL_ADCSPEED_125KSPS);
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switch (precision) {
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case ADC_RES_6BIT:
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case ADC_RES_8BIT:
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case ADC_RES_10BIT:
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#if ADC_0_EN
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ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_10BIT_S);
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#endif
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#if ADC_1_EN
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ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_10BIT_S);
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#endif
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adc_config[dev].max_value = 0x3ff;
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break;
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case ADC_RES_12BIT:
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#if ADC_0_EN
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ROM_ADCResolutionSet(ADC0_BASE, ADC_RES_12BIT_S);
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#endif
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#if ADC_1_EN
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ROM_ADCResolutionSet(ADC1_BASE, ADC_RES_12BIT_S);
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#endif
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adc_config[dev].max_value = 0xfff;
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break;
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case ADC_RES_14BIT:
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case ADC_RES_16BIT:
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break;
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}
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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// Select the Analog ADC Function for these pins.
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ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);
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// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
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ROM_ADCSequenceDisable(ADC0_BASE, 3);
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// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
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// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
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// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
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ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
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// Configure step 0 on sequence 3.
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// Sample channel 0 (ADC_CTL_CH0) in single-ended mode and configure the interrupt flag.
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// (ADC_CTL_IE) to be set to enable Interrupt.
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ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
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ADC_CTL_CH0 | ADC_CTL_IE | ADC_CTL_END);
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// Clear the interrupt status flag. This is done to make sure
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// the interrupt flag is cleared before we sample.
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ROM_ADCIntClear(ADC0_BASE, 3);
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// Since sample sequence 3 is now configured, it must be enabled.
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ROM_ADCSequenceEnable(ADC0_BASE, 3);
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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// Select the Analog ADC Function for these pins.
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ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);
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// Before configuring the sequencer, we need to disable ita to prevent errorneous execution
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ROM_ADCSequenceDisable(ADC1_BASE, 3);
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// Enable Sample Sequence 3 with a Software Start (Processor signal trigger).
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// The software writes an 8 (SS3) to ADC_PSSI_R to initiate a conversion on sequencer 3.
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// Sequence 3 will do a single sample when the processor sends a signal to start the conversion.
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ROM_ADCSequenceConfigure(ADC1_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);
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// Configure step 0 on sequence 3.
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// Sample channel 0 (ADC_CTL_CH1) in single-ended mode and configure the interrupt flag.
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// (ADC_CTL_IE) to be set to enable Interrupt.
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ROM_ADCSequenceStepConfigure(ADC1_BASE, 3, 0,
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ADC_CTL_CH1 | ADC_CTL_IE | ADC_CTL_END);
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// Clear the interrupt status flag. This is done to make sure
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// the interrupt flag is cleared before we sample.
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ROM_ADCIntClear(ADC1_BASE, 3);
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// Since sample sequence 3 is now configured, it must be enabled.
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ROM_ADCSequenceEnable(ADC1_BASE, 3);
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break;
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#endif
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default:
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return -1;
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}
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return 0;
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}
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int adc_sample(adc_t dev, int channel)
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{
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unsigned long ulADC_val=0;
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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// Trigger the ADC conversion
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ROM_ADCProcessorTrigger(ADC0_BASE, 3);
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// Wait for conversion to be completed.
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while(!ROM_ADCIntStatus(ADC0_BASE, 3, false));
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// Read ADC value.
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ROM_ADCSequenceDataGet(ADC0_BASE, 3, &ulADC_val);
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// Clear the ADC interrupt flag
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ROM_ADCIntClear(ADC0_BASE, 3);
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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// Trigger the ADC conversion
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ROM_ADCProcessorTrigger(ADC1_BASE, 3);
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// Wait for conversion to be completed.
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while(!ROM_ADCIntStatus(ADC1_BASE, 3, false));
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// Read ADC value.
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ROM_ADCSequenceDataGet(ADC1_BASE, 3, &ulADC_val);
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// Clear the ADC interrupt flag
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ROM_ADCIntClear(ADC1_BASE, 3);
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break;
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#endif
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default:
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return -1;
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}
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/* return result */
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return ((int)ulADC_val);
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}
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void adc_poweron(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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// The ADC0 Peripheral must be enabled for use
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
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break;
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#endif
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}
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}
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void adc_poweroff(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
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break;
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#endif
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}
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}
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int adc_map(adc_t dev, int value, int min, int max)
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{
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return (int)adc_mapf(dev, value, (float)min, (float)max);
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}
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float adc_mapf(adc_t dev, int value, float min, float max)
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{
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return ((max - min) / ((float)adc_config[dev].max_value)) * value;
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}
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#endif /* ADC_NUMOF */
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/** @} */
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