cpu/stm32f0: adapted to centralized cpu conf

cpu/stm32f0/cpu.c

@@ -28,11 +28,10 @@ static void clock_init(void);
  */
 void cpu_init(void)
 {
+    /* initialize the Cortex-M core */
+    cortexm_init();
     /* initialize the clock system */
     clock_init();
-
-    /* set pendSV interrupt to lowest possible priority */
-    NVIC_SetPriority(PendSV_IRQn, 0xff);
 }
 
 /**

cpu/stm32f0/include/cpu_conf.h

@@ -33,32 +33,11 @@ extern "C" {
 #endif
 
 /**
- * @name Kernel configuration
- *
- * The absolute minimum stack size is 140 byte (68 byte for the tcb + 72 byte
- * for a complete context save).
- *
- * TODO: measure and adjust for the Cortex-M0
+ * @brief   ARM Cortex-M specific CPU configuration
  * @{
  */
-#define THREAD_EXTRA_STACKSIZE_PRINTF    (512)
-
-#ifndef THREAD_STACKSIZE_DEFAULT
-#define THREAD_STACKSIZE_DEFAULT   (512)
-#endif
-
-#define THREAD_STACKSIZE_IDLE      (192)
-/** @} */
-
-/**
- * @name UART0 buffer size definition for compatibility reasons
- *
- * TODO: remove once the remodeling of the uart0 driver is done
- * @{
- */
-#ifndef UART0_BUFSIZE
-#define UART0_BUFSIZE                   (128)
-#endif
+#define CPU_DEFAULT_IRQ_PRIO            (1U)
+#define CPU_IRQ_NUMOF                   (31U)
 /** @} */
 
 /**
@@ -66,15 +45,6 @@ extern "C" {
  */
 #define CPUID_ID_LEN                    (12)
 
-/**
- * @brief Definition of different panic modes
- */
-typedef enum {
-    HARD_FAULT,             /**< hard fault */
-    NMI_HANDLER,            /**< non maskable interrupt */
-    DUMMY_HANDLER           /**< dummy interrupt handler */
-} panic_t;
-
 #ifdef __cplusplus
 }
 #endif

cpu/stm32f0/include/stm32f051x8.h

@@ -85,7 +85,7 @@ typedef enum
 /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */
 

cpu/stm32f0/include/stm32f091xc.h

@@ -84,7 +84,7 @@ typedef enum
 /******  Cortex-M0 Processor Exceptions Numbers **************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                        */
   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                                */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                                  */
   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                                  */
   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                              */
 

cpu/stm32f0/startup.c

@@ -80,17 +80,17 @@ void reset_handler(void)
  */
 void dummy_handler(void)
 {
-    core_panic(DUMMY_HANDLER, "DUMMY HANDLER");
+    core_panic(PANIC_DUMMY_HANDLER, "DUMMY HANDLER");
 }
 
 void isr_nmi(void)
 {
-    core_panic(NMI_HANDLER, "NMI HANDLER");
+    core_panic(PANIC_NMI_HANDLER, "NMI HANDLER");
 }
 
 void isr_hard_fault(void)
 {
-    core_panic(HARD_FAULT, "HARD FAULT");
+    core_panic(PANIC_HARD_FAULT, "HARD FAULT");
 }
 
 /* Cortex-M specific interrupt vectors */