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Merge pull request #6723 from aabadie/nucleo144_f412

boards/nucleo144-f412: initial support
master
Francisco Acosta 6 years ago committed by GitHub
parent
commit
cd824c3bc2
  1. 2
      boards/nucleo144-common/include/arduino_pinmap.h
  2. 3
      boards/nucleo144-f412/Makefile
  3. 1
      boards/nucleo144-f412/Makefile.dep
  4. 15
      boards/nucleo144-f412/Makefile.features
  5. 6
      boards/nucleo144-f412/Makefile.include
  6. 35
      boards/nucleo144-f412/board.c
  7. 1
      boards/nucleo144-f412/dist/openocd.cfg
  8. 47
      boards/nucleo144-f412/include/board.h
  9. 255
      boards/nucleo144-f412/include/periph_conf.h
  10. 2
      cpu/stm32f4/include/cpu_conf.h
  11. 7389
      cpu/stm32f4/include/vendor/stm32f412zx.h
  12. 32
      cpu/stm32f4/ldscripts/stm32f412zg.ld
  13. 1
      tests/unittests/Makefile

2
boards/nucleo144-common/include/arduino_pinmap.h

@ -59,7 +59,7 @@ extern "C" {
#define ARDUINO_PIN_A0 GPIO_PIN(PORT_A, 3)
#define ARDUINO_PIN_A1 GPIO_PIN(PORT_C, 0)
#define ARDUINO_PIN_A2 GPIO_PIN(PORT_C, 3)
#if defined(CPU_MODEL_STM32F413ZH)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F412ZG)
#define ARDUINO_PIN_A3 GPIO_PIN(PORT_C, 1)
#define ARDUINO_PIN_A4 GPIO_PIN(PORT_C, 4)
#define ARDUINO_PIN_A5 GPIO_PIN(PORT_C, 5)

3
boards/nucleo144-f412/Makefile

@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

1
boards/nucleo144-f412/Makefile.dep

@ -0,0 +1 @@
include $(RIOTBOARD)/nucleo-common/Makefile.dep

15
boards/nucleo144-f412/Makefile.features

@ -0,0 +1,15 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo-144 boards
include $(RIOTBOARD)/nucleo144-common/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_3

6
boards/nucleo144-f412/Makefile.include

@ -0,0 +1,6 @@
# define the cpu used by the nucleo-f412 board
export CPU = stm32f4
export CPU_MODEL = stm32f412zg
# load the common Makefile.include for Nucleo-144 boards
include $(RIOTBOARD)/nucleo144-common/Makefile.include

35
boards/nucleo144-f412/board.c

@ -0,0 +1,35 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo144-f412
* @{
*
* @file
* @brief Board specific implementations for the nucleo144-f412 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the boards LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_init(LED2_PIN, GPIO_OUT);
}

1
boards/nucleo144-f412/dist/openocd.cfg vendored

@ -0,0 +1 @@
source [find board/st_nucleo_f4.cfg]

47
boards/nucleo144-f412/include/board.h

@ -0,0 +1,47 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup boards_nucleo144-f412 Nucleo-F412
* @ingroup boards
* @brief Board specific files for the nucleo144-f412 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo144-f412 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name xtimer configuration
* @{
*/
#define XTIMER_DEV TIMER_DEV(0)
#define XTIMER_CHAN (0)
#define XTIMER_OVERHEAD (6)
#define XTIMER_BACKOFF (5)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

255
boards/nucleo144-f412/include/periph_conf.h

@ -0,0 +1,255 @@
/*
* Copyright (C) 2016 Inria
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo144-f412
* @{
*
* @file
* @name Peripheral MCU configuration for the nucleo144-f412 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSE (8000000U) /**< external oscillator */
#define CLOCK_CORECLOCK (100000000U) /**< desired core clock frequency */
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
#define CLOCK_PLL_P (2U)
#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM5,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM5EN,
.bus = APB1,
.irqn = TIM5_IRQn
}
};
#define TIMER_0_ISR isr_tim5
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_D, 9),
.tx_pin = GPIO_PIN(PORT_D, 8),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 6,
.dma_chan = 4
#endif
},
{
.dev = USART6,
.rcc_mask = RCC_APB2ENR_USART6EN,
.rx_pin = GPIO_PIN(PORT_G, 9),
.tx_pin = GPIO_PIN(PORT_G, 14),
.rx_af = GPIO_AF8,
.tx_af = GPIO_AF8,
.bus = APB2,
.irqn = USART6_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 5,
.dma_chan = 4
#endif
},
{
.dev = USART2,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_D, 6),
.tx_pin = GPIO_PIN(PORT_D, 5),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART2_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 4,
.dma_chan = 4
#endif
},
};
#define UART_0_ISR (isr_usart3)
#define UART_0_DMA_ISR (isr_dma1_stream6)
#define UART_1_ISR (isr_usart6)
#define UART_1_DMA_ISR (isr_dma1_stream5)
#define UART_2_ISR (isr_usart2)
#define UART_2_DMA_ISR (isr_dma1_stream4)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
{ .pin = GPIO_UNDEF, .cc_chan = 0} },
.af = GPIO_AF1,
.bus = APB2
},
{
.dev = TIM4,
.rcc_mask = RCC_APB1ENR_TIM4EN,
.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
{ .pin = GPIO_UNDEF, .cc_chan = 0},
{ .pin = GPIO_UNDEF, .cc_chan = 0},
{ .pin = GPIO_UNDEF, .cc_chan = 0} },
.af = GPIO_AF2,
.bus = APB1
},
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 50000000Hz */
7, /* -> 195312Hz */
6, /* -> 390625Hz */
5, /* -> 781250Hz */
2, /* -> 6250000Hz */
1 /* -> 12500000Hz */
},
{ /* for APB2 @ 100000000Hz */
7, /* -> 390625Hz */
7, /* -> 390625Hz */
6, /* -> 781250Hz */
3, /* -> 6250000Hz */
2 /* -> 12500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_PIN(PORT_A, 4),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_0_EN 1
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (42000000U)
/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 8
#define I2C_0_SCL_AF 4
#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 9
#define I2C_0_SDA_AF 4
#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

2
cpu/stm32f4/include/cpu_conf.h

@ -31,6 +31,8 @@
#include "vendor/stm32f410rx.h"
#elif defined(CPU_MODEL_STM32F411RE)
#include "vendor/stm32f411xe.h"
#elif defined(CPU_MODEL_STM32F412ZG)
#include "vendor/stm32f412zx.h"
#elif defined(CPU_MODEL_STM32F413ZH)
#include "vendor/stm32f413xx.h"
#elif defined(CPU_MODEL_STM32F415RG)

7389
cpu/stm32f4/include/vendor/stm32f412zx.h vendored

File diff suppressed because it is too large Load Diff

32
cpu/stm32f4/ldscripts/stm32f412zg.ld

@ -0,0 +1,32 @@
/*
* Copyright (C) 2015-2017 Freie Universität Berlin
* 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f4
* @{
*
* @file
* @brief Memory definitions for the STM32F412ZG
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

1
tests/unittests/Makefile

@ -92,6 +92,7 @@ ARM_CORTEX_M_BOARDS := airfy-beacon \
nrf52840dk \
nrf6310 \
nucleo144-f303 \
nucleo144-f412 \
nucleo144-f429 \
nucleo144-f446 \
nucleo32-f031 \

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