Browse Source
Adapt the kw2xrf driver for the netdev2 interface. This patch also adds overwrites.h, the header provides overwrite values for the kw2xrf PHY.patch-1
Johann Fischer
7 years ago
committed by
smlng
16 changed files with 2783 additions and 1352 deletions
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/*
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* Copyright (C) 2016 Phytec Messtechnik GmbH |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup |
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* @{ |
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* |
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* @file |
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* @brief get/set interfaces for kw2xrf driver |
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* |
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* @author Johann Fischer <j.fischer@phytec.de> |
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*/ |
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#include "kw2xrf.h" |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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void kw2xrf_set_tx_power(kw2xrf_t *dev, int16_t txpower); |
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uint16_t kw2xrf_get_txpower(kw2xrf_t *dev); |
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uint8_t kw2xrf_get_channel(kw2xrf_t *dev); |
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int kw2xrf_set_channel(kw2xrf_t *dev, uint8_t val); |
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void kw2xrf_abort_sequence(kw2xrf_t *dev); |
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void kw2xrf_set_idle_sequence(kw2xrf_t *dev); |
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void kw2xrf_set_sequence(kw2xrf_t *dev, kw2xrf_physeq_t seq); |
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void kw2xrf_set_pan(kw2xrf_t *dev, uint16_t pan); |
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void kw2xrf_set_addr_short(kw2xrf_t *dev, uint16_t addr); |
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void kw2xrf_set_addr_long(kw2xrf_t *dev, uint64_t addr); |
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uint16_t kw2xrf_get_addr_short(kw2xrf_t *dev); |
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uint64_t kw2xrf_get_addr_long(kw2xrf_t *dev); |
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int8_t kw2xrf_get_cca_threshold(kw2xrf_t *dev); |
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void kw2xrf_set_cca_threshold(kw2xrf_t *dev, int8_t value); |
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void kw2xrf_set_cca_mode(kw2xrf_t *dev, uint8_t mode); |
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uint8_t kw2xrf_get_cca_mode(kw2xrf_t *dev); |
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uint32_t kw2xrf_get_rssi(uint32_t value); |
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netopt_state_t kw2xrf_get_status(kw2xrf_t *dev); |
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int kw2xrf_cca(kw2xrf_t *dev); |
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void kw2xrf_set_rx_watermark(kw2xrf_t *dev, uint8_t value); |
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void kw2xrf_set_option(kw2xrf_t *dev, uint16_t option, bool state); |
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#ifdef __cplusplus |
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} |
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#endif |
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/** @} */ |
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/*
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* Copyright (C) 2016 Phytec Messtechnik GmbH |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup |
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* @{ |
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* |
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* @file |
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* @brief Internal function interfaces for kw2xrf driver |
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* |
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* @author Johann Fischer <j.fischer@phytec.de> |
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*/ |
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#include <stdint.h> |
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#include "kw2xrf.h" |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/** Power Modes */ |
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typedef enum { |
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KW2XRF_HIBERNATE = 0, |
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KW2XRF_DOZE, |
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KW2XRF_IDLE, |
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KW2XRF_AUTODOZE, |
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} kw2xrf_powermode_t; |
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inline void kw2xrf_set_dreg_bit(kw2xrf_t *dev, uint8_t reg, uint8_t bit) |
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{ |
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uint8_t tmp = kw2xrf_read_dreg(dev, reg); |
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tmp |= bit; |
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kw2xrf_write_dreg(dev, reg, tmp); |
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} |
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inline void kw2xrf_clear_dreg_bit(kw2xrf_t *dev, uint8_t reg, uint8_t bit) |
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{ |
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uint8_t tmp = kw2xrf_read_dreg(dev, reg); |
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tmp &= ~bit; |
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kw2xrf_write_dreg(dev, reg, tmp); |
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} |
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/** Enable any transceiver interrupt to assert IRQ_B */ |
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inline void kw2xrf_enable_irq_b(kw2xrf_t *dev) |
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{ |
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kw2xrf_clear_dreg_bit(dev, MKW2XDM_PHY_CTRL4, MKW2XDM_PHY_CTRL4_TRCV_MSK); |
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} |
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/** Mask all transceiver interrupts to assert IRQ_B */ |
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inline void kw2xrf_mask_irq_b(kw2xrf_t *dev) |
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{ |
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kw2xrf_set_dreg_bit(dev, MKW2XDM_PHY_CTRL4, MKW2XDM_PHY_CTRL4_TRCV_MSK); |
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} |
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void kw2xrf_disable_interrupts(kw2xrf_t *dev); |
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void kw2xrf_update_overwrites(kw2xrf_t *dev); |
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void kw2xrf_set_out_clk(kw2xrf_t *dev); |
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void kw2xrf_set_power_mode(kw2xrf_t *dev, kw2xrf_powermode_t pm); |
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int kw2xrf_can_switch_to_idle(kw2xrf_t *dev); |
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typedef enum kw2xrf_timer_timebase { |
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KW2XRF_TIMEBASE_500000HZ = 2, |
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KW2XRF_TIMEBASE_250000HZ, |
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KW2XRF_TIMEBASE_125000HZ, |
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KW2XRF_TIMEBASE_62500HZ, |
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KW2XRF_TIMEBASE_31250HZ, |
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KW2XRF_TIMEBASE_15625HZ, |
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} kw2xrf_timer_timebase_t; |
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/**
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* Initialize the Event Timer Block (up counter) |
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* The Event Timer Block provides: |
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* - Abort an RX and CCA sequence at pre-determined time |
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* - Latches "timestamp" value during packet reception |
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* - Initiates timer-triggered sequences |
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*/ |
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void kw2xrf_timer_init(kw2xrf_t *dev, kw2xrf_timer_timebase_t tb); |
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void kw2xrf_timer2_seq_start_on(kw2xrf_t *dev); |
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void kw2xrf_timer2_seq_start_off(kw2xrf_t *dev); |
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void kw2xrf_timer3_seq_abort_on(kw2xrf_t *dev); |
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void kw2xrf_timer3_seq_abort_off(kw2xrf_t *dev); |
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/**
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* Use T2CMP or T2PRIMECMP to Trigger Transceiver Operations |
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*/ |
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void kw2xrf_trigger_tx_ops_enable(kw2xrf_t *dev, uint32_t timeout); |
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/**
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* Disable Trigger for Transceiver Operations |
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* |
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*/ |
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void kw2xrf_trigger_tx_ops_disable(kw2xrf_t *dev); |
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/**
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* Use T3CMP to Abort an RX operation |
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*/ |
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void kw2xrf_abort_rx_ops_enable(kw2xrf_t *dev, uint32_t timeout); |
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/**
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* Disable Trigger to Abort an RX operation |
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*/ |
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void kw2xrf_abort_rx_ops_disable(kw2xrf_t *dev); |
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void kw2xrf_seq_timeout_on(kw2xrf_t *dev, uint32_t timeout); |
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void kw2xrf_seq_timeout_off(kw2xrf_t *dev); |
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/**
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* Returns Timestamp of the actual received packet |
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*/ |
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uint32_t kw2xrf_get_timestamp(kw2xrf_t *dev); |
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#ifdef __cplusplus |
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} |
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#endif |
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/** @} */ |
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/*
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* Copyright (C) 2016 Phytec Messtechnik GmbH |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup |
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* @{ |
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* |
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* @file |
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* @brief Netdev interface for kw2xrf driver |
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* |
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* @author Johann Fischer <j.fischer@phytec.de> |
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*/ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/**
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* @brief Reference to the netdev device driver struct |
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*/ |
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extern const netdev2_driver_t kw2xrf_driver; |
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#ifdef __cplusplus |
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} |
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#endif |
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/** @} */ |
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/*
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* Copyright (C) 2016 Phytec Messtechnik GmbH |
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* |
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* This file is subject to the terms and conditions of the GNU Lesser |
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* General Public License v2.1. See the file LICENSE in the top level |
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* directory for more details. |
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*/ |
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/**
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* @ingroup tests_kw2xrf |
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* @{ |
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* |
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* @file |
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* @brief Testing interfaces for kw2xrf driver |
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* |
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* @author Johann Fischer <j.fischer@phytec.de> |
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*/ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#ifdef KW2XRF_TESTMODE |
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#include "kw2xrf.h" |
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#include "kw2xrf_reg.h" |
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#include "kw2xrf_getset.h" |
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#include "net/netopt.h" |
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enum mkw2xrf_testmode { |
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KW2XRF_TM_CTX_PREAMBLE = NETOPT_RF_TESTMODE_CTX_PRBS9 + 1, |
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KW2XRF_TM_CTX_2MHZ, |
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KW2XRF_TM_CTX_200KHZ, |
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KW2XRF_TM_CTX_1MBPS_PRBS9, |
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KW2XRF_TM_CTX_EXT, |
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KW2XRF_TM_CTX_NM0, |
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KW2XRF_TM_CTX_NM1, |
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}; |
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int kw2xrf_set_test_mode(kw2xrf_t *dev, uint8_t mode); |
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#endif |
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#ifdef __cplusplus |
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} |
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#endif |
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/** @} */ |
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/*!
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* Copyright (c) 2015, Freescale Semiconductor, Inc. |
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* All rights reserved. |
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* |
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* \file MCR20Overwrites.h |
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* Description: Overwrites header file for MCR20 Register values |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* |
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* o Redistributions of source code must retain the above copyright notice, this list |
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* of conditions and the following disclaimer. |
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* |
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* o Redistributions in binary form must reproduce the above copyright notice, this |
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* list of conditions and the following disclaimer in the documentation and/or |
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* other materials provided with the distribution. |
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* |
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
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* contributors may be used to endorse or promote products derived from this |
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* software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef OVERWRITES_H_ |
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#define OVERWRITES_H_ |
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typedef struct overwrites_tag { |
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char address; |
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char data; |
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} overwrites_t; |
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/*****************************************************************************************************************/ |
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// This file is created exclusively for use with the transceiver 2.0 silicon
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// and is provided for the world to use. It contains a list of all
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// known overwrite values. Overwrite values are non-default register
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// values that configure the transceiver device to a more optimally performing
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// posture. It is expected that low level software (i.e. PHY) will
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// consume this file as a #include, and transfer the contents to the
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// the indicated addresses in the transceiver's memory space. This file has
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// at least one required entry, that being its own version current version
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// number, to be stored at transceiver's location 0x3B the
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// OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
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// the transceiver address space to assist in future debug efforts. The
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// analyst may read this location (once device has been booted with
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// mysterious software) and have a good indication of what register
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// overwrites were performed (with all versions of the overwrites.h file
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// being archived forever at the Compass location shown above.
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//
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// The transceiver has an indirect register (IAR) space. Write access to this space
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// requires 3 or more writes:
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// 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
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// 2nd) IAR Register #0x00 - 0xFF.
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// 3rd) The data to write
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// nth) Burst mode additional data if required.
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//
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// Write access to direct space requires only a single address, data pair.
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overwrites_t const overwrites_direct[] ={ |
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{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
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{0x23, 0x17} //PA_PWR new default Power Step is "23"
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}; |
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overwrites_t const overwrites_indirect[] ={ |
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{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
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{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
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{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
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{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
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{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
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{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
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{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
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{0x52, 0x55}, //AGC_THR1 RSSI tune up
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{0x53, 0x2D}, //AGC_THR2 RSSI tune up
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{0x66, 0x5F}, //ATT_RSSI1 tune up
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{0x67, 0x8F}, //ATT_RSSI2 tune up
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{0x68, 0x61}, //RSSI_OFFSET
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{0x78, 0x03}, //CHF_PMAGAIN
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{0x22, 0x50}, //CCA1_THRESH
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{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
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{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
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}; |
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/* begin of deprecated versions
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==VERSION 1== |
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(version 1 is empty) |
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==VERSION 2== |
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overwrites_t const overwrites_indirect[] ={ |
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{0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
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}; |
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==VERSION 3== |
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overwrites_t const overwrites_indirect[] ={ |
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{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
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{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
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{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
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}; |
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==VERSION 4== |
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overwrites_t const overwrites_direct[] ={ |
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{0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
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}; |
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overwrites_t const overwrites_indirect[] ={ |
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{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
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{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
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{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
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{0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
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}; |
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|
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==VERSION 5== |
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overwrites_t const overwrites_direct[] ={ |
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{0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
|
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}; |
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overwrites_t const overwrites_indirect[] ={ |
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{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
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{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
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{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
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{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
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{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
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{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
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{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
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{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
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{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
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{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
}; |
||||
|
||||
==VERSION 6== |
||||
overwrites_t const overwrites_direct[] ={ |
||||
{0x3B, 0x06} //version 06: disable PA calibration
|
||||
}; |
||||
|
||||
overwrites_t const overwrites_indirect[] ={ |
||||
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
||||
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
|
||||
{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
||||
{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
||||
{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
|
||||
}; |
||||
|
||||
==VERSION 7== |
||||
overwrites_t const overwrites_direct[] ={ |
||||
{0x3B, 0x07} //version 07: updated registers for ED/RSSI
|
||||
}; |
||||
|
||||
overwrites_t const overwrites_indirect[] ={ |
||||
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
||||
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
|
||||
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
||||
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
||||
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
|
||||
{0x52, 0x73}, //AGC_THR1 RSSI tune up
|
||||
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
|
||||
{0x66, 0x5F}, //ATT_RSSI1 tune up
|
||||
{0x67, 0x8F}, //ATT_RSSI2 tune up
|
||||
{0x68, 0x60}, //RSSI_OFFSET
|
||||
{0x69, 0x65} //RSSI_SLOPE
|
||||
}; |
||||
|
||||
|
||||
==VERSION 8== |
||||
overwrites_t const overwrites_direct[] ={ |
||||
{0x3B, 0x08} //version 08: updated registers for ED/RSSI
|
||||
}; |
||||
|
||||
overwrites_t const overwrites_indirect[] ={ |
||||
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
||||
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
|
||||
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
||||
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
||||
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
|
||||
{0x52, 0x73}, //AGC_THR1 RSSI tune up
|
||||
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
|
||||
{0x66, 0x5F}, //ATT_RSSI1 tune up
|
||||
{0x67, 0x8F}, //ATT_RSSI2 tune up
|
||||
{0x69, 0x65} //RSSI_SLOPE
|
||||
{0x68, 0x61}, //RSSI_OFFSET
|
||||
{0x78, 0x03} //CHF_PMAGAIN
|
||||
}; |
||||
|
||||
|
||||
==VERSION 9== |
||||
overwrites_t const overwrites_direct[] ={ |
||||
{0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
|
||||
{0x23, 0x17} //PA_PWR new default value
|
||||
}; |
||||
|
||||
overwrites_t const overwrites_indirect[] ={ |
||||
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
||||
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
|
||||
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
||||
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
||||
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
|
||||
{0x52, 0x55}, //AGC_THR1 RSSI tune up
|
||||
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
|
||||
{0x66, 0x5F}, //ATT_RSSI1 tune up
|
||||
{0x67, 0x8F}, //ATT_RSSI2 tune up
|
||||
{0x68, 0x61}, //RSSI_OFFSET
|
||||
{0x78, 0x03} //CHF_PMAGAIN
|
||||
}; |
||||
|
||||
==VERSION A== |
||||
overwrites_t const overwrites_direct[] ={ |
||||
{0x3B, 0x0A} //version 0A: updated registers for CCA
|
||||
{0x23, 0x17} //PA_PWR new default Power Step is "23"
|
||||
}; |
||||
|
||||
overwrites_t const overwrites_indirect[] ={ |
||||
{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
|
||||
{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
|
||||
{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
|
||||
{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
|
||||
{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
|
||||
{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
|
||||
{0x52, 0x55}, //AGC_THR1 RSSI tune up
|
||||
{0x53, 0x2D}, //AGC_THR2 RSSI tune up
|
||||
{0x66, 0x5F}, //ATT_RSSI1 tune up
|
||||
{0x67, 0x8F}, //ATT_RSSI2 tune up
|
||||
{0x68, 0x61}, //RSSI_OFFSET
|
||||
{0x78, 0x03} //CHF_PMAGAIN
|
||||
{0x22, 0x50} //CCA1_THRESH
|
||||
}; |
||||
|
||||
end of deprecated versions */ |
||||
|
||||
|
||||
#endif //OVERWRITES_H_
|
||||
@ -0,0 +1,516 @@
|
||||
/*
|
||||
* Copyright (C) 2016 PHYTEC Messtechnik GmbH |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU Lesser General |
||||
* Public License v2.1. See the file LICENSE in the top level directory for more |
||||
* details. |
||||
*/ |
||||
|
||||
/**
|
||||
* @ingroup drivers_kw2xrf |
||||
* @{ |
||||
* @file |
||||
* @brief get/set functionality of kw2xrf driver |
||||
* |
||||
* @author Johann Fischer <j.fischer@phytec.de> |
||||
* @author Jonas Remmert <j.remmert@phytec.de> |
||||
* @author Oliver Hahm <oliver.hahm@inria.fr> |
||||
* @} |
||||
*/ |
||||
|
||||
#include "kw2xrf.h" |
||||
#include "kw2xrf_spi.h" |
||||
#include "kw2xrf_reg.h" |
||||
#include "kw2xrf_getset.h" |
||||
#include "kw2xrf_intern.h" |
||||
|
||||
#define ENABLE_DEBUG (0) |
||||
#include "debug.h" |
||||
|
||||
#define KW2XRF_LQI_HW_MAX 230 /**< LQI Saturation Level */ |
||||
|
||||
/* Modem_PA_PWR Register (PA Power Control) has a valid range from 3-31 */ |
||||
#define MKW2XDRF_PA_RANGE_MAX 31 /**< Maximum value of PA Power Control Register */ |
||||
#define MKW2XDRF_PA_RANGE_MIN 3 /**< Minimum value of PA Power Control Register */ |
||||
|
||||
/* PLL integer and fractional lookup tables
|
||||
* |
||||
* Fc = 2405 + 5(k - 11) , k = 11,12,...,26 |
||||
* |
||||
* Equation for PLL frequency, MKW2xD Reference Manual, p.255 : |
||||
* F = ((PLL_INT0 + 64) + (PLL_FRAC0/65536))32MHz |
||||
* |
||||
*/ |
||||
static const uint8_t pll_int_lt[16] = { |
||||
11, 11, 11, 11, |
||||
11, 11, 12, 12, |
||||
12, 12, 12, 12, |
||||
13, 13, 13, 13 |
||||
}; |
||||
|
||||
static const uint16_t pll_frac_lt[16] = { |
||||
10240, 20480, 30720, 40960, |
||||
51200, 61440, 6144, 16384, |
||||
26624, 36864, 47104, 57344, |
||||
2048, 12288, 22528, 32768 |
||||
}; |
||||
|
||||
static const uint8_t pow_lt[44] = { |
||||
3, 4, 4, 5, |
||||
6, 6, 7, 7, |
||||
8, 9, 9, 10, |
||||
11, 11, 12, 13, |
||||
13, 14, 14, 15, |
||||
16, 16, 17, 18, |
||||
18, 19, 20, 20, |
||||
21, 21, 22, 23, |
||||
23, 24, 25, 25, |
||||
26, 27, 27, 28, |
||||
28, 29, 30, 31 |
||||
}; |
||||
|
||||
void kw2xrf_set_tx_power(kw2xrf_t *dev, int16_t txpower) |
||||
{ |
||||
if (txpower > MKW2XDRF_OUTPUT_POWER_MAX) { |
||||
txpower = MKW2XDRF_OUTPUT_POWER_MAX; |
||||
} |
||||
|
||||
if (txpower < MKW2XDRF_OUTPUT_POWER_MIN) { |
||||
txpower = MKW2XDRF_OUTPUT_POWER_MIN; |
||||
} |
||||
|
||||
uint8_t level = pow_lt[txpower - MKW2XDRF_OUTPUT_POWER_MIN]; |
||||
kw2xrf_write_dreg(dev, MKW2XDM_PA_PWR, MKW2XDM_PA_PWR(level)); |
||||
dev->tx_power = txpower; |
||||
} |
||||
|
||||
uint16_t kw2xrf_get_txpower(kw2xrf_t *dev) |
||||
{ |
||||
return dev->tx_power; |
||||
} |
||||
|
||||
uint8_t kw2xrf_get_channel(kw2xrf_t *dev) |
||||
{ |
||||
uint8_t pll_int = kw2xrf_read_dreg(dev, MKW2XDM_PLL_INT0); |
||||
uint16_t pll_frac = kw2xrf_read_dreg(dev, MKW2XDM_PLL_FRAC0_LSB); |
||||
pll_frac |= ((uint16_t)kw2xrf_read_dreg(dev, MKW2XDM_PLL_FRAC0_MSB) << 8); |
||||
|
||||
for (int i = 0; i < 16; i++) { |
||||
if ((pll_frac_lt[i] == pll_frac) && (pll_int_lt[i] == pll_int)) { |
||||
return i + 11; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int kw2xrf_get_sequence(kw2xrf_t *dev) |
||||
{ |
||||
int reg = 0; |
||||
reg = kw2xrf_read_dreg(dev, MKW2XDM_PHY_CTRL1); |
||||
reg &= MKW2XDM_PHY_CTRL1_XCVSEQ_MASK; |
||||
return reg; |
||||
} |
||||
|
||||
int kw2xrf_set_channel(kw2xrf_t *dev, uint8_t channel) |
||||
{ |
||||
/* Save old sequence to restore this state later */ |
||||
uint8_t old_seq = kw2xrf_get_sequence(dev); |
||||
|
||||
if (channel < KW2XRF_MIN_CHANNEL || channel > KW2XRF_MAX_CHANNEL) { |
||||
DEBUG("[kw2xrf]: Invalid channel %i set\n", channel); |
||||
return -1; |
||||
} |
||||
|
||||
if (old_seq) { |
||||
kw2xrf_abort_sequence(dev); |
||||
} |
||||
|
||||
uint8_t tmp = channel - 11; |
||||
kw2xrf_write_dreg(dev, MKW2XDM_PLL_INT0, MKW2XDM_PLL_INT0_VAL(pll_int_lt[tmp])); |
||||
kw2xrf_write_dreg(dev, MKW2XDM_PLL_FRAC0_LSB, (uint8_t)pll_frac_lt[tmp]); |
||||
kw2xrf_write_dreg(dev, MKW2XDM_PLL_FRAC0_MSB, (uint8_t)(pll_frac_lt[tmp] >> 8)); |
||||
|
||||
dev->netdev.chan = channel; |
||||
|
||||
if (old_seq) { |
||||
kw2xrf_set_sequence(dev, old_seq); |
||||
} |
||||
|
||||
DEBUG("[kw2xrf]: set channel to %u\n", channel); |
||||
return 0; |
||||
} |
||||
|
||||