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Converting C++ style coding to C style

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dev/timer
Rakendra Thapa 8 years ago
parent 3761ebcc21
commit da91eba1ca
3 changed files with 152 additions and 152 deletions
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16
cpu/lm4f120/periph/timer.c
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@ -44,14 +44,14 @@ static timer_conf_t config[TIMER_NUMOF];
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
{
if (dev == TIMER_0) {
config[dev].cb = callback; // User Function
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); // Activate Timer0
WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
config[dev].cb = callback; /* User Function */
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); /* Activate Timer0 */
WTIMER0_CTL_R &= ~0x00000001; /* Disable timer0A during setup */
WTIMER0_CFG_R = TIMER_CFG_16_BIT;
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // Configure for periodic mode
WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; /* Configure for periodic mode */
WTIMER0_TAPR_R = TIMER_0_PRESCALER; /* 1us timer0A */
WTIMER0_ICR_R = 0x00000001; /* clear timer0A timeout flag */
WTIMER0_IMR_R |= 0x00000001; /* arm timeout interrupt */
ROM_IntPrioritySet(INT_WTIMER0A, 32);
timer_irq_enable(dev);
timer_start(dev);
@ -75,7 +75,7 @@ int timer_set(tim_t dev, int channel, unsigned int timeout)
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
if (dev == TIMER_0) {
WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value
WTIMER0_TAILR_R = 0x00000000 | value; /* period; Reload value */
DEBUG("Setting timer absolute value=0x%x\n", value);
return 1;
}

10
cpu/lm4f120/periph/uart.c
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@ -78,9 +78,9 @@ static const unsigned long g_ulUARTInt[3] =
*/
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
{
// Check the arguments
/* Check the arguments */
ASSERT(uart == 0);
// Check to make sure the UART peripheral is present
/* Check to make sure the UART peripheral is present */
if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
return -1;
}
@ -95,7 +95,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
config[uart].tx_cb = tx_cb;
config[uart].arg = arg;
// ulBase = g_ulUARTBase[uart];
/* ulBase = g_ulUARTBase[uart]; */
switch (uart){
#if UART_0_EN
case UART_0:
@ -190,7 +190,7 @@ void isr_uart0(void)
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
ROM_UARTIntClear(UART0_BASE, ulStatus);
// Are we interrupted due to TX done
/* Are we interrupted due to TX done */
if(ulStatus & UART_INT_TX)
{
if (config[UART_0].tx_cb(config[UART_0].arg) == 0){
@ -198,7 +198,7 @@ void isr_uart0(void)
}
}
// Are we interrupted due to a recieved character
/* Are we interrupted due to a recieved character */
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
while(ROM_UARTCharsAvail(UART0_BASE))

278
cpu/lm4f120/vectors.c
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@ -122,144 +122,144 @@ ISR_VECTORS const void *interrupt_vector[] = {
* context switching is happening here */
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
/* Peripherial interrupts start here.*/
(void *) isr_gpio_porta, // GPIO Port A 16
(void *) isr_gpio_portb, // GPIO Port B 17
(void *) isr_gpio_portc, // GPIO Port C 18
(void *) isr_gpio_portd, // GPIO Port D 19
(void *) isr_gpio_porte, // GPIO Port E 20
(void *) isr_uart0, // UART 0 21
(void *) isr_uart1, // UART 1 22
(void *) isr_ssi0, // SSI 0 23
(void *) isr_i2c0, // I2C 0 24
(void *) (0UL), // Reserved 25
(void *) (0UL), // Reserved 26
(void *) (0UL), // Reserved 27
(void *) (0UL), // Reserved 28
(void *) (0UL), // Reserved 29
(void *) isr_adc0_seq0, // ADC 0 Seq 0 30
(void *) isr_adc0_seq1, // ADC 0 Seq 1 31
(void *) isr_adc0_seq2, // ADC 0 Seq 2 32
(void *) isr_adc0_seq3, // ADC 0 Seq 3 33
(void *) isr_wdt, // WDT 0 and 1 34
(void *) isr_timer0a, // 16/32 bit timer 0 A 35
(void *) isr_timer0b, // 16/32 bit timer 0 B 36
(void *) isr_timer1a, // 16/32 bit timer 1 A 37
(void *) isr_timer1b, // 16/32 bit timer 1 B 38
(void *) isr_timer2a, // 16/32 bit timer 2 A 39
(void *) isr_timer2b, // 16/32 bit timer 2 B 40
(void *) isr_comp0, // Analog comparator 0 41
(void *) isr_comp1, // Analog comparator 1 42
(void *) (0UL), // Reserved 43
(void *) isr_sysctl, // System control 44
(void *) isr_flashctl, // Flash + EEPROM control 45
(void *) isr_gpio_portf, // GPIO Port F 46
(void *) (0UL), // Reserved 47
(void *) (0UL), // Reserved 48
(void *) isr_uart2, // UART 2 49
(void *) isr_ssi2, // SSI 1 50
(void *) isr_timer3a, // 16/32 bit timer 3 A 51
(void *) isr_timer3b, // 16/32 bit timer 3 B 52
(void *) isr_i2c1, // I2C 1 53
(void *) (0UL), // Reserved 54
(void *) isr_can0, // CAN 0 55
(void *) (0UL), // Reserved 56
(void *) (0UL), // Reserved 57
(void *) (0UL), // Reserved 58
(void *) isr_hibernate, // Hibernation module 59
(void *) isr_usb, // USB 60
(void *) (0UL), // Reserved 61
(void *) isr_udma_sw, // UDMA SW 62
(void *) isr_udma_error, // UDMA Error 63
(void *) isr_adc1_seq0, // ADC 1 Seq 0 64
(void *) isr_adc1_seq1, // ADC 1 Seq 1 65
(void *) isr_adc1_seq2, // ADC 1 Seq 2 66
(void *) isr_adc1_seq3, // ADC 1 Seq 3 67
(void *) (0UL), // Reserved 68
(void *) (0UL), // Reserved 69
(void *) (0UL), // Reserved 70
(void *) (0UL), // Reserved 71
(void *) (0UL), // Reserved 72
(void *) isr_ssi2, // SSI 2 73
(void *) isr_ssi3, // SSI 3 74
(void *) isr_uart3, // UART 3 75
(void *) isr_uart4, // UART 4 76
(void *) isr_uart5, // UART 5 77
(void *) isr_uart6, // UART 6 78
(void *) isr_uart7, // UART 7 79
(void *) (0UL), // Reserved 80
(void *) (0UL), // Reserved 81
(void *) (0UL), // Reserved 82
(void *) (0UL), // Reserved 83
(void *) isr_i2c2, // I2C 2 84
(void *) isr_i2c4, // I2C 4 85
(void *) isr_timer4a, // 16/32 bit timer 4 A 86
(void *) isr_timer4b, // 16/32 bit timer 4 B 87
(void *) (0UL), // Reserved 88
(void *) (0UL), // Reserved 89
(void *) (0UL), // Reserved 90
(void *) (0UL), // Reserved 91
(void *) (0UL), // Reserved 92
(void *) (0UL), // Reserved 93
(void *) (0UL), // Reserved 94
(void *) (0UL), // Reserved 95
(void *) (0UL), // Reserved 96
(void *) (0UL), // Reserved 97
(void *) (0UL), // Reserved 98
(void *) (0UL), // Reserved 99
(void *) (0UL), // Reserved 100
(void *) (0UL), // Reserved 101
(void *) (0UL), // Reserved 102
(void *) (0UL), // Reserved 103
(void *) (0UL), // Reserved 104
(void *) (0UL), // Reserved 105
(void *) (0UL), // Reserved 106
(void *) (0UL), // Reserved 107
(void *) isr_timer5a, // 16/32 bit timer 5 A 108
(void *) isr_timer5b, // 16/32 bit timer 5 B 109
(void *) isr_wtimer0a, // 32/64 bit timer 0 A 110
(void *) isr_wtimer0b, // 32/64 bit timer 0 B 111
(void *) isr_wtimer1a, // 32/64 bit timer 1 A 112
(void *) isr_wtimer1b, // 32/64 bit timer 1 B 113
(void *) isr_wtimer2a, // 32/64 bit timer 2 A 114
(void *) isr_wtimer2b, // 32/64 bit timer 2 B 115
(void *) isr_wtimer3a, // 32/64 bit timer 3 A 116
(void *) isr_wtimer3b, // 32/64 bit timer 3 B 117
(void *) isr_wtimer4a, // 32/64 bit timer 4 A 118
(void *) isr_wtimer4b, // 32/64 bit timer 4 B 119
(void *) isr_wtimer5a, // 32/64 bit timer 5 A 120
(void *) isr_wtimer5b, // 32/64 bit timer 5 B 121
(void *) isr_sysex, // System Exception 122
(void *) (0UL), // Reserved 123
(void *) (0UL), // Reserved 124
(void *) (0UL), // Reserved 125
(void *) (0UL), // Reserved 126
(void *) (0UL), // Reserved 127
(void *) (0UL), // Reserved 128
(void *) (0UL), // Reserved 129
(void *) (0UL), // Reserved 130
(void *) (0UL), // Reserved 131
(void *) (0UL), // Reserved 132
(void *) (0UL), // Reserved 133
(void *) (0UL), // Reserved 134
(void *) (0UL), // Reserved 135
(void *) (0UL), // Reserved 136
(void *) (0UL), // Reserved 137
(void *) (0UL), // Reserved 138
(void *) (0UL), // Reserved 139
(void *) (0UL), // Reserved 140
(void *) (0UL), // Reserved 141
(void *) (0UL), // Reserved 142
(void *) (0UL), // Reserved 143
(void *) (0UL), // Reserved 144
(void *) (0UL), // Reserved 145
(void *) (0UL), // Reserved 146
(void *) (0UL), // Reserved 147
(void *) (0UL), // Reserved 148
(void *) (0UL), // Reserved 149
(void *) (0UL), // Reserved 150
(void *) (0UL), // Reserved 151
(void *) (0UL), // Reserved 152
(void *) (0UL), // Reserved 153
(void *) (0UL) // Reserved 154
(void *) isr_gpio_porta, /* GPIO Port A 16 */
(void *) isr_gpio_portb, /* GPIO Port B 17 */
(void *) isr_gpio_portc, /* GPIO Port C 18 */
(void *) isr_gpio_portd, /* GPIO Port D 19 */
(void *) isr_gpio_porte, /* GPIO Port E 20 */
(void *) isr_uart0, /* UART 0 21 */
(void *) isr_uart1, /* UART 1 22 */
(void *) isr_ssi0, /* SSI 0 23 */
(void *) isr_i2c0, /* I2C 0 24 */
(void *) (0UL), /* Reserved 25 */
(void *) (0UL), /* Reserved 26 */
(void *) (0UL), /* Reserved 27 */
(void *) (0UL), /* Reserved 28 */
(void *) (0UL), /* Reserved 29 */
(void *) isr_adc0_seq0, /* ADC 0 Seq 0 30 */
(void *) isr_adc0_seq1, /* ADC 0 Seq 1 31 */
(void *) isr_adc0_seq2, /* ADC 0 Seq 2 32 */
(void *) isr_adc0_seq3, /* ADC 0 Seq 3 33 */
(void *) isr_wdt, /* WDT 0 and 1 34 */
(void *) isr_timer0a, /* 16/32 bit timer 0 A 35 */
(void *) isr_timer0b, /* 16/32 bit timer 0 B 36 */
(void *) isr_timer1a, /* 16/32 bit timer 1 A 37 */
(void *) isr_timer1b, /* 16/32 bit timer 1 B 38 */
(void *) isr_timer2a, /* 16/32 bit timer 2 A 39 */
(void *) isr_timer2b, /* 16/32 bit timer 2 B 40 */
(void *) isr_comp0, /* Analog comparator 0 41 */
(void *) isr_comp1, /* Analog comparator 1 42 */
(void *) (0UL), /* Reserved 43 */
(void *) isr_sysctl, /* System control 44 */
(void *) isr_flashctl, /* Flash + EEPROM control 45 */
(void *) isr_gpio_portf, /* GPIO Port F 46 */
(void *) (0UL), /* Reserved 47 */
(void *) (0UL), /* Reserved 48 */
(void *) isr_uart2, /* UART 2 49 */
(void *) isr_ssi2, /* SSI 1 50 */
(void *) isr_timer3a, /* 16/32 bit timer 3 A 51 */
(void *) isr_timer3b, /* 16/32 bit timer 3 B 52 */
(void *) isr_i2c1, /* I2C 1 53 */
(void *) (0UL), /* Reserved 54 */
(void *) isr_can0, /* CAN 0 55 */
(void *) (0UL), /* Reserved 56 */
(void *) (0UL), /* Reserved 57 */
(void *) (0UL), /* Reserved 58 */
(void *) isr_hibernate, /* Hibernation module 59 */
(void *) isr_usb, /* USB 60 */
(void *) (0UL), /* Reserved 61 */
(void *) isr_udma_sw, /* UDMA SW 62 */
(void *) isr_udma_error, /* UDMA Error 63 */
(void *) isr_adc1_seq0, /* ADC 1 Seq 0 64 */
(void *) isr_adc1_seq1, /* ADC 1 Seq 1 65 */
(void *) isr_adc1_seq2, /* ADC 1 Seq 2 66 */
(void *) isr_adc1_seq3, /* ADC 1 Seq 3 67 */
(void *) (0UL), /* Reserved 68 */
(void *) (0UL), /* Reserved 69 */
(void *) (0UL), /* Reserved 70 */
(void *) (0UL), /* Reserved 71 */
(void *) (0UL), /* Reserved 72 */
(void *) isr_ssi2, /* SSI 2 73 */
(void *) isr_ssi3, /* SSI 3 74 */
(void *) isr_uart3, /* UART 3 75 */
(void *) isr_uart4, /* UART 4 76 */
(void *) isr_uart5, /* UART 5 77 */
(void *) isr_uart6, /* UART 6 78 */
(void *) isr_uart7, /* UART 7 79 */
(void *) (0UL), /* Reserved 80 */
(void *) (0UL), /* Reserved 81 */
(void *) (0UL), /* Reserved 82 */
(void *) (0UL), /* Reserved 83 */
(void *) isr_i2c2, /* I2C 2 84 */
(void *) isr_i2c4, /* I2C 4 85 */
(void *) isr_timer4a, /* 16/32 bit timer 4 A 86 */
(void *) isr_timer4b, /* 16/32 bit timer 4 B 87 */
(void *) (0UL), /* Reserved 88 */
(void *) (0UL), /* Reserved 89 */
(void *) (0UL), /* Reserved 90 */
(void *) (0UL), /* Reserved 91 */
(void *) (0UL), /* Reserved 92 */
(void *) (0UL), /* Reserved 93 */
(void *) (0UL), /* Reserved 94 */
(void *) (0UL), /* Reserved 95 */
(void *) (0UL), /* Reserved 96 */
(void *) (0UL), /* Reserved 97 */
(void *) (0UL), /* Reserved 98 */
(void *) (0UL), /* Reserved 99 */
(void *) (0UL), /* Reserved 100 */
(void *) (0UL), /* Reserved 101 */
(void *) (0UL), /* Reserved 102 */
(void *) (0UL), /* Reserved 103 */
(void *) (0UL), /* Reserved 104 */
(void *) (0UL), /* Reserved 105 */
(void *) (0UL), /* Reserved 106 */
(void *) (0UL), /* Reserved 107 */
(void *) isr_timer5a, /* 16/32 bit timer 5 A 108 */
(void *) isr_timer5b, /* 16/32 bit timer 5 B 109 */
(void *) isr_wtimer0a, /* 32/64 bit timer 0 A 110 */
(void *) isr_wtimer0b, /* 32/64 bit timer 0 B 111 */
(void *) isr_wtimer1a, /* 32/64 bit timer 1 A 112 */
(void *) isr_wtimer1b, /* 32/64 bit timer 1 B 113 */
(void *) isr_wtimer2a, /* 32/64 bit timer 2 A 114 */
(void *) isr_wtimer2b, /* 32/64 bit timer 2 B 115 */
(void *) isr_wtimer3a, /* 32/64 bit timer 3 A 116 */
(void *) isr_wtimer3b, /* 32/64 bit timer 3 B 117 */
(void *) isr_wtimer4a, /* 32/64 bit timer 4 A 118 */
(void *) isr_wtimer4b, /* 32/64 bit timer 4 B 119 */
(void *) isr_wtimer5a, /* 32/64 bit timer 5 A 120 */
(void *) isr_wtimer5b, /* 32/64 bit timer 5 B 121 */
(void *) isr_sysex, /* System Exception 122 */
(void *) (0UL), /* Reserved 123 */
(void *) (0UL), /* Reserved 124 */
(void *) (0UL), /* Reserved 125 */
(void *) (0UL), /* Reserved 126 */
(void *) (0UL), /* Reserved 127 */
(void *) (0UL), /* Reserved 128 */
(void *) (0UL), /* Reserved 129 */
(void *) (0UL), /* Reserved 130 */
(void *) (0UL), /* Reserved 131 */
(void *) (0UL), /* Reserved 132 */
(void *) (0UL), /* Reserved 133 */
(void *) (0UL), /* Reserved 134 */
(void *) (0UL), /* Reserved 135 */
(void *) (0UL), /* Reserved 136 */
(void *) (0UL), /* Reserved 137 */
(void *) (0UL), /* Reserved 138 */
(void *) (0UL), /* Reserved 139 */
(void *) (0UL), /* Reserved 140 */
(void *) (0UL), /* Reserved 141 */
(void *) (0UL), /* Reserved 142 */
(void *) (0UL), /* Reserved 143 */
(void *) (0UL), /* Reserved 144 */
(void *) (0UL), /* Reserved 145 */
(void *) (0UL), /* Reserved 146 */
(void *) (0UL), /* Reserved 147 */
(void *) (0UL), /* Reserved 148 */
(void *) (0UL), /* Reserved 149 */
(void *) (0UL), /* Reserved 150 */
(void *) (0UL), /* Reserved 151 */
(void *) (0UL), /* Reserved 152 */
(void *) (0UL), /* Reserved 153 */
(void *) (0UL) /* Reserved 154 */
};
/** @} */

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